JP2003234272A - Semiconductor apparatus and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor apparatus being position detecting channels by which an alignment mark can more easily and precisely recognized, and a manufacturing method for the semiconductor apparatus for overlaying patterns, using the position detecting channels. <P>SOLUTION: This semiconductor board includes an underlayer wire 13 on a base film 11, and a position detecting channels 15 indicating a reference position of the processing pattern as well as a contact hole 14 is pattern-formed on an interlayer insulation film 12 formed on the upper surface. This position detecting channel 15 is constructed such that a set of a plurality of bar type channels each with a different opening aperture width is provided with four sets along four sides of a square SQ. Then each of sets comprises three kinds of channels each with a different opening aperture, and these constructs the position detecting channel 15, being provided in turn from a wider one in a opening width, radially to each direction of four sides from a center of the square SQ. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a position detecting groove for superposing a plurality of patterns on a semiconductor substrate, and using this position detecting groove. The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with the high integration of semiconductor devices, their fine processing technology has become more and more important. In order to further promote the miniaturization, a technique for flattening the entire semiconductor substrate becomes more important in each manufacturing process of the semiconductor device. A chemical mechanical polishing (CMP) method has been attracting attention as a technique for accurately performing this flattening. The CMP method is a technology in which an etching method and a mechanical polishing method are combined, and by using this, the semiconductor substrate can be globally planarized.

On the other hand, in order to promote miniaturization of the above semiconductor device, in a photolithography process, a pattern formed on a semiconductor substrate and a photomask of a pattern formed on the semiconductor substrate are overlapped with each other, and the overlay error is eliminated. Accurate measurement is becoming more and more important. Such an overlay error of the photomask is measured by detecting an alignment mark formed on the substrate.

Here, various patterns formed on the substrate can be used as the alignment mark. However, for example, when a semitransparent or opaque wiring material is uniformly formed on the entire surface of the substrate in the step of forming the wiring, the pattern formed in the lower layer of the formed wiring material cannot be detected. . Therefore, the pattern cannot be used as an alignment mark. Therefore, conventionally, a position detection groove is formed in advance in a film on which the same wiring material is deposited, and this is used as an alignment mark. By forming such a position detection groove, even when an opaque wiring material is formed above the position detection groove, a step (a dent) can be generated in the position detection groove, and this step difference is formed. It becomes possible to measure the overlay error of the pattern based on.

Hereinafter, as an example of a general usage of the alignment mark formed by the position detecting groove, an upper layer wiring pattern (superposition pattern) and an insulating film in which contact holes and the like are formed corresponding to the lower layer wiring pattern are formed. A case of superimposing it on the processing pattern (reference pattern) will be described.

FIG. 11 is an enlarged partial sectional view of an alignment mark portion of the above-mentioned semiconductor device in which patterns are superposed. In this superposition, first
As shown in FIG. 11A, a lower layer wiring (not shown) is patterned on a base film 101 above a semiconductor substrate, and then an interlayer insulating film 102 for flattening the surface is formed thereon. Then, a photoresist 103 is applied on the upper surface of the photoresist 103, and the photoresist 103 is exposed and developed to form a pattern. As a result, a mask for forming the reference pattern and the position detection groove, which serves as a reference for superposition, is printed on the interlayer insulating film 102.

Then, as shown in FIG. 11 (b),
By anisotropically etching the interlayer insulating film 102, a reference pattern (not shown) and a position detection groove 104 are formed.
To form. In this case, the shape of the position detection groove 104 is 1
It is a square punching pattern (box pattern) having a side of “20 μm”, and this is a target pattern 105 indicating the reference position of the reference pattern.

Subsequently, as shown in FIG. 11 (c),
After forming an opaque conductive film 106 on the surface, a photoresist (not shown) is applied again on the surface, and this is patterned by exposure and development to bake a mask for forming an upper circuit pattern (not shown). ). At the same time, “10 μm” is formed inside the target pattern 105.
Position accuracy pattern 107 of the target pattern 1
Bake aiming at the central part of 05.

When measuring the position, the position accuracy pattern 10 with respect to the target pattern 105 is used.
The deviation amount of 7 is optically measured as a superposition error, and the superposition accuracy is evaluated based on the optical deviation. Further, if necessary, this overlay error is fed back as a position control parameter at the time of exposure for printing the mask of the upper layer wiring pattern. This makes it possible to prevent manufacturing defects due to overlay defects, and improve overlay accuracy in the subsequent steps.

By the way, in the process of manufacturing a semiconductor device, when a step of flattening the entire surface of the substrate is provided as in the CMP method described above, it is difficult to measure the amount of deviation at the time of overlaying using the target pattern. May be.

For example, when electrically connecting the upper layer wiring pattern to the lower layer wiring pattern through the contact hole formed in the interlayer insulating film, while forming the plug wiring in the contact hole, the wiring layer of the upper layer wiring is formed. In some cases, it may be necessary to secure excellent electrical conductivity.
In this case, usually, different conductive materials are used for the plug wiring and the wiring layer of the upper wiring, so that after filling the contact holes with the conductive material, the interlayer insulating film is exposed on the entire surface of the substrate. Until then, a step of polishing and flattening is provided. However, at this time,
Since the entire surface of the substrate is planarized substantially uniformly by the semitransparent or opaque conductive film, it becomes difficult to accurately recognize the position of the target pattern. After all, it becomes difficult to accurately measure the above-mentioned pattern overlay error.

However, even in this case, as the target pattern, a box-shaped target pattern 108 having a wide opening whose planar shape is shown in FIG.
In the case of using, as shown in the cross-sectional shape of FIG. 12B, even if the flattening by the CMP method is performed,
A depression 109 called dishing is formed in the opening of the target pattern 108. Thus the depression 10
If 9 occurs, the overlay error between the upper layer wiring pattern and the reference pattern can be measured based on this.

In this case, however, the target pattern 1
Due to the structure that 08 is a large area concave pattern, a non-uniform error may occur in the plane of the substrate when measuring the overlay error. That is, when the target pattern 108 shown in FIG. 12A is used, the dent 109 generated after the flattening by the CMP method is shown in FIG.
2 (b), the target pattern 108
The cross-sectional shape is often asymmetric with respect to. In such a case, the peak detection position of the signal obtained corresponding to the edge portion (outer pattern) of the target pattern 108 when the image recognition process is performed also shifts asymmetrically from the ideal position. . Moreover, the tendency that the peak detection position deviates from the ideal position is non-uniform in the substrate surface. Therefore, when measuring the displacement amount of the position accuracy pattern with respect to the target pattern and evaluating it, Non-uniform error will also be included. The occurrence of such a non-uniform error is a major obstacle to the miniaturization of semiconductor devices.

Therefore, conventionally, in order to reduce the non-uniform error in the plane of the substrate, instead of the box-shaped target pattern 108, elongated rectangular grooves are combined to form four sides of a quadrangle. Attempts have also been made to use bar-shaped target patterns (for example, "S
PIE Vol. 3677 pp. 107-115 (1
999) "and the like).

13A and 13B are a plan view and a cross-sectional view, respectively, illustrating the shape of the bar-shaped target pattern. As shown in FIG.
The bar-shaped target pattern 110 is formed of, for example, a groove having an opening width of about “1 μm”. Then, a conductive film is embedded in the target pattern 110, and the displacement amount of the position accuracy pattern is measured with reference to the depressions corresponding to the positions of the grooves formed when the surface is planarized by the CMP method. . As a result, it becomes possible to reduce the above-mentioned non-uniform measurement error in the substrate surface.

However, in the case of the bar-shaped target pattern 110, it is difficult to select the optimum groove width capable of forming the depressions corresponding to the positions of the grooves on the substrate surface flattened by the CMP method or the like.

For example, if the opening width of the bar is too small, there is a high possibility that the surface of the substrate will be completely flattened when the conductive film forming the plug wiring is polished by the CMP method. In such a case, the depression serving as the reference position for measuring the overlay error is not formed, and the overlay error cannot be measured.

FIG. 14 is an enlarged view showing the vicinity of the alignment mark in the sectional structure in the manufacturing process of the semiconductor substrate when the overlay error cannot be measured in this way.

That is, first, as shown in FIG. 14A, a lower layer wiring pattern 112 is formed on a base film 111, and an interlayer insulating film 113 is formed thereon. Then, in order to make a connection from the upper surface to the lower layer wiring pattern 112,
A contact hole 114 is formed in the interlayer insulating film 113, and the bar-shaped target pattern 120 is formed. The processing pattern of the contact hole 114 serves as a reference pattern for the overlay pattern.
Subsequently, as shown in FIG. 14B, a filling metal film 115 for depositing the contact holes 114 is deposited on the entire surface of the substrate. After that, as shown in FIG. 14C, the entire surface of the substrate is polished and flattened by the CMP method. At this time, since the groove width of the target pattern 120 is small,
No depression corresponding to the position of the target pattern 120 is formed on the surface. Therefore, as shown in FIG. 14D, even when the conductive film 116 for forming the upper layer wiring pattern is deposited, the depression corresponding to the position of the target pattern 120 is not formed. Therefore, even if a resist for patterning the conductive film 116 is printed on the surface, the position of the target pattern 120 cannot be recognized, and the overlay error cannot be measured.

On the other hand, when the opening width of the bar is too large, the enlarged cross section of the target pattern in the step corresponding to FIG. 14C has a shape as shown in FIG. 15A. That is, in this case, the depression 122 corresponding to the position of the groove forming the target pattern 121.
Is certainly formed. However, as shown in FIG. 15B, a peak 130 of a signal obtained by performing image recognition processing on the depression 122 has a gentle and asymmetric waveform, and the accuracy of overlay error measurement using this is naturally limited. Will end up.

[0021]

As described above, the position detection groove for generating the alignment mark has its advantages and disadvantages, whether it is the box shape or the bar shape. Therefore, when the alignment mark is generated using the position detection groove, the characteristics of each of the box-shaped target pattern and the bar-shaped target pattern are utilized so as to match the overlapping condition of the target patterns. It is desirable to properly use those patterns. However, the determination of the optimum shape of these target patterns is not easy because it requires specialized knowledge and experience in manufacturing a semiconductor device and, in some cases, it is also necessary to obtain the optimum conditions by trial and error. Further, unless such superposition of patterns can be performed with high accuracy, further advancement of fine processing of semiconductor devices cannot be expected.

The present invention has been made in view of these circumstances, and an object thereof is to utilize a semiconductor device having a position detection groove that makes recognition as an alignment mark easier and more accurate, and the position detection groove. Another object of the present invention is to provide a method of manufacturing a semiconductor device in which patterns are superposed.

[0023]

[Means for Solving the Problems] Means for attaining the above-mentioned objects and their effects will be described below. The invention according to claim 1 is a semiconductor device in which a position detection groove for forming an alignment mark at the time of superposition is provided in a base film above a semiconductor substrate, and each of the position detection grooves has an opening width. The gist is that it consists of a combination of a plurality of different grooves.

The invention described in claim 2 is the same as claim 1
In the semiconductor device described in the paragraph 1, the position detection groove has a plurality of grooves having different opening widths as one set, and the set has a rectangular shape.
The gist is that four sets are arranged along the sides.

The invention described in claim 3 is the same as that of claim 2
2. In the semiconductor device according to [1], in the set of the plurality of grooves having different opening widths, two grooves having the same opening width arranged to face each other with the rectangle sandwiched are arranged from the center of the rectangle. The gist is that they are equally spaced from each other.

According to a fourth aspect of the present invention, the position detection groove is provided as a semiconductor device in which a position detection groove for forming an alignment mark at the time of superposition is provided in the base film above the semiconductor substrate. The gist of the present invention is that it is formed in a groove shape having a predetermined opening width, and that the groove is provided with a widened portion for enlarging the predetermined opening width at each end thereof.

The invention described in claim 5 is the same as claim 4
The gist of the semiconductor device described in (1) is that the widened portion is provided in such a manner that each end of the groove is bent in the same direction.

The invention described in claim 6 is the same as claim 5
In the semiconductor device according to the item (1), the position detection groove is arranged as four grooves along four sides of a rectangle, and the widening portion in each groove has a refraction direction in a direction toward the rectangle. What is set is the gist.

According to a seventh aspect of the present invention, the position detecting groove is provided as a semiconductor device in which a position detecting groove for forming an alignment mark at the time of superposition is provided in a base film above the semiconductor substrate. The gist of the present invention is that it is formed to have a rectangular planar shape, and a projection pattern of an arbitrary shape whose height is less than the depth of the groove is formed at the bottom of the groove.

The invention described in claim 8 is the same as claim 7
The gist of the semiconductor device according to the item (1) is that the protrusion pattern includes a plurality of protrusion patterns. Also,
According to a ninth aspect of the present invention, in the semiconductor device according to the eighth aspect, the plurality of rectangular frame patterns are formed in such a manner that the ridge pattern is sequentially nested along an edge portion of the rectangular groove. The main point is to consist of.

According to a tenth aspect of the invention, in the semiconductor device according to the seventh aspect, the protrusion pattern is
The gist of the invention is that the rectangular groove is composed of a plurality of polygonal patterns that are spaced apart from each other.

According to an eleventh aspect of the present invention, in the semiconductor device according to any one of the seventh to tenth aspects, a distance between the protrusion pattern and an edge of the rectangular groove is adjacent to each other. The distance between the protrusion patterns is
The gist is that the thickness is 0.4 μm or less.

On the other hand, according to the twelfth aspect of the present invention, as a method of manufacturing a semiconductor device, a step of forming a groove array composed of a combination of a plurality of grooves each having a different opening width as a position detection groove in a base film above a semiconductor substrate A step of forming a first film on the upper surface thereof, a step of flattening the first film using the base film as a stopper film, and a step of flattening the first film.
And a step of forming a second film on the second film, wherein the depression formed corresponding to the groove row formed as the position detection groove on the surface of the second film is used as an alignment mark. And

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the twelfth aspect, the position detection groove includes a plurality of grooves having different opening widths as one set.
The gist is that four sets are formed along the four sides of the rectangle.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the thirteenth aspect, a set of a plurality of grooves having different opening widths are the same and face each other across the rectangle. The gist is that two grooves having an opening width are formed so as to be equally spaced from the center of the rectangle.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the twelfth to fourteenth aspects, the recesses formed corresponding to the groove rows formed as the position detecting grooves are formed. The gist is to perform position measurement selectively using the one that can obtain the highest recognition accuracy.

According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the twelfth to fifteenth aspects, the insulating film in which a contact hole is formed together with the position detection groove as the base film. A film is used, a conductive film embedded in a contact hole of the insulating film is used as the first film, and a conductive film formed as a wiring layer on the upper surface of the insulating film is used as the second film. And

According to a seventeenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any of the twelfth to sixteenth aspects, a chemical mechanical polishing method is used for flattening the first film. The summary will be given.

According to the eighteenth aspect of the present invention, as a method of manufacturing a semiconductor device, the base film above the semiconductor substrate has a predetermined opening width as a position detection groove and the predetermined opening at each end thereof. A step of forming a groove having a widened portion for widening the width, and a step of forming a first film on the upper surface thereof,
The method includes a step of flattening the first film using the base film as a stopper film, and a step of forming a second film on the flattened first film. The gist of the invention is to use, as an alignment mark, a recess formed corresponding to the groove formed as the position detection groove.

According to a nineteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighteenth aspect, the widened portion is formed so that each end of the groove is bent in the same direction. Is the gist.

According to a twentieth aspect of the present invention, in the method of manufacturing a semiconductor device according to the nineteenth aspect, four grooves are formed along each of four sides of the rectangle as the position detection grooves, and each of them is formed. The gist of the invention is to set the widened portion of the groove so that all the refraction directions thereof face the rectangle.

The invention according to claim 21 is the method for manufacturing a semiconductor device according to any one of claims 18 to 20, wherein an insulating film in which a contact hole is formed along with the position detection groove as the base film is provided. A film is used, a conductive film embedded in a contact hole of the insulating film is used as the first film, and a conductive film formed as a wiring layer on the upper surface of the insulating film is used as the second film. And

According to a twenty-second aspect of the present invention, in the method of manufacturing a semiconductor device according to any of the eighteenth to twenty-first aspects, a chemical mechanical polishing method is used for flattening the first film. The summary will be given.

According to a twenty-third aspect of the present invention, as a method of manufacturing a semiconductor device, a groove having a rectangular plane shape is formed as a position detection groove in an underlying film above a semiconductor substrate at an inner bottom portion thereof. A step of forming a projection pattern of an arbitrary shape having a height less than the depth, a step of forming a first film on the upper surface thereof, and a step of forming the first film using the base film as a stopper film. And the step of flattening the first
And a step of forming a second film on the second film, wherein the pit formed corresponding to the groove formed as the position detection groove on the surface of the second film is used as an alignment mark. To do.

A twenty-fourth aspect of the present invention is summarized in the method of manufacturing a semiconductor device according to the twenty-third aspect, wherein a plurality of ridge patterns are used as the protrusion patterns.

The invention according to claim 25 is the method for manufacturing a semiconductor device according to claim 24, wherein the protrusion patterns are nested in order along the edges of the rectangular grooves. It is the gist to use the rectangular frame pattern.

According to a twenty-sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the twenty-fifth aspect, a plurality of polygons which are spaced apart from each other in the rectangular groove are provided as the protrusion patterns. The point is to use patterns.

In the structure according to the first aspect, the position detection groove for forming the alignment mark when the plurality of patterns are superposed is formed by a combination of a plurality of grooves each having a different opening width. Therefore, even if an opaque film is deposited as the second film on the upper surface and the film is flattened by the CMP method or the like, the opening widths of those grooves and the material of the film deposited at that time are Corresponding to conditions such as a film forming method, depressions having different shapes are formed in the openings of the plurality of grooves having different opening widths. Accordingly, it is possible to easily and highly accurately recognize the depression as an alignment mark in accordance with a wide range of conditions such as the materials of the first and second films and the film forming method. A semiconductor device having such a position detection groove can be suitably manufactured by using the method described in claim 12.

In the structure described in claim 2, the combination of the plurality of grooves having different opening widths is set as one set,
Four sets are arranged along the four sides of the rectangle. Therefore, the depressions corresponding to the plurality of grooves having different opening widths are formed along the four sides of the rectangle, and the recognition can be performed more easily by the position detection on the two axes orthogonal to each other. become. In addition, each of those grooves,
As in the structure according to claim 3, two grooves having the same opening width and arranged so as to face each other across the rectangle are arranged at equal intervals from the center of the rectangle. By doing so, it is possible to make the recognition of the depression corresponding to it easier. And
A semiconductor device having the position detection groove according to claim 2 or claim 3 is the semiconductor device according to claim 13 or 1 above.
By using the method described in No. 4, it becomes possible to suitably manufacture each of them.

Further, in the method according to any one of claims 12 to 14, like the method according to claim 15, the position measurement is performed by selectively using the depression that can obtain the highest recognition accuracy. If you want to
Under a wide range of conditions such as the materials of the first and second films and the film forming method, high recognition accuracy can be ensured more reliably.

Here, when the method according to any one of claims 12 to 15 is used in correspondence with each film according to claim 16, the contact holes are superposed on the pattern of the underlying film. It is possible to form a wiring layer that is accurately overlapped on the upper surface of the insulating film on which is formed. Further, as the method according to any one of claims 12 to 16, when the entire surface of the substrate is flattened by chemical mechanical polishing as in the method according to claim 17, the method corresponds to each groove. Thus, it becomes possible to appropriately form the depression.

On the other hand, in the structure described in claim 4, the position detecting groove for forming the alignment mark when the plurality of patterns are superposed is formed in a groove shape having a predetermined opening width, and The groove is provided with a widened portion for enlarging the predetermined opening width at each end thereof. For this reason, the recess corresponding to it can be more reliably formed in the upper center part of these grooves.
As a result, it becomes possible to more easily and highly accurately recognize the depressions formed corresponding to the grooves as alignment marks. A semiconductor device having such a position detection groove can be manufactured preferably by using the method described in claim 18.

Further, in the structure according to the fifth aspect, the widened portion is provided in such a manner that each end of the groove is bent in the same direction. As a result, the effect obtained by the structure described in claim 4 can be made more reliable. Further, each of the grooves is defined by the above-mentioned item 6.
As in the structure described in (3), when all the widened portions are set in the direction facing the rectangle, the effect is most surely obtained. Then, a semiconductor device including the position detection groove according to claim 5 and claim 6,
By using the methods described in claims 19 and 20, respectively, each of them can be suitably manufactured.

Here, when the method according to any one of claims 18 to 20 is used in correspondence with each film according to claim 21, the contact holes are superposed on the pattern of the underlying film. It is possible to form a wiring layer that is accurately overlapped on the upper surface of the insulating film on which is formed. Further, for example, as the method according to any one of claims 18 to 21, even when the entire surface of the substrate is planarized by chemical mechanical polishing, as in the method according to claim 22, Accordingly, it becomes possible to suitably form the depression.

On the other hand, in the structure described in claim 7, the position detection groove for forming the alignment mark when the plurality of patterns are superposed has a rectangular planar shape and A protrusion pattern having an arbitrary shape whose height is less than the depth of the groove is formed on the bottom of the groove. For this reason, a large area portion does not exist in the inner bottom portion of the position detection groove, and damage to the base film at the time of forming the groove can be avoided. As a result, recognition as an alignment mark becomes easier and more accurate. A semiconductor device having such a position detection groove can be suitably manufactured by using the method described in claim 23.

Further, in the structure described in claim 8, since the projection pattern is composed of a plurality of ridge patterns, the structure described in claim 7 can be reliably realized. Further, in the structure according to the ninth aspect, each of the ridge patterns is composed of a plurality of rectangular frame patterns formed in a nested manner in order along the edge of the rectangular groove. Therefore, a more reliable implementation of the structure described in claim 8 is achieved. On the other hand, in the structure according to the tenth aspect, the protrusion pattern is composed of a plurality of polygonal patterns which are spaced apart from each other in the rectangular groove. With this structure as well, the structure described in claim 7 can be reliably realized. And these claim 7
As described in claim 11, the distance between the protrusion pattern and the edge of the rectangular groove, and the distance between the protrusion patterns adjacent to each other are
When the thickness is 0.4 μm or less, damage to the underlying film during formation of the position detection groove can be more reliably avoided. In addition, these claim 8, claim 9, and claim 1
The semiconductor device having the position detection groove described in 0 can be suitably manufactured by using the methods described in claim 24, claim 25, and claim 26, respectively. .

[0057]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A first embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to FIGS.

In the semiconductor device of the present embodiment, the wiring is formed in a multi-layered structure, and the wiring of each layer is sequentially connected to the upper wiring of those layers via the plug wiring embedded in the interlayer insulating film. It is connected to the. And
When the pattern of the upper layer wiring is superimposed on the pattern of the lower layer wiring buried under the interlayer insulating film, the pattern of the lower layer wiring and the pattern of the same interlayer insulating film is formed on the interlayer insulating film in order to measure the overlay error. A position detection groove indicating the reference position of is provided.

FIG. 1 is a diagram showing the cross-sectional shape and the planar shape of such a position detecting groove. In the cross-sectional view, a part of the lower layer wiring is also shown on the left side thereof. As illustrated in the cross-sectional view of FIG. 1A, this semiconductor substrate has a base film 1
A lower layer wiring 13 is patterned on the first layer 1, and an interlayer insulating film 12 is formed on the lower layer wiring 13 to flatten the surface irregularities formed by the lower layer wiring 13. Then, a contact hole 14 for ensuring the connection from the upper surface to the lower layer wiring 13 is patterned in the interlayer insulating film 12,
The contact hole 14 is filled with a plug wiring (not shown), and is similarly connected to an upper layer (not shown). Then, together with the contact hole 14, the lower layer wiring 13 and the interlayer insulating film 1 are formed in the interlayer insulating film 12.
A position detection groove 15 indicating the reference position of the formation pattern 2 is provided. In FIG. 1A, a region R1 on the left side of the substrate cross section is a wiring formation region in which the lower layer wiring 13 and the like are formed, and a region R2 on the right side is the wiring formation region R.
It is a position detection groove formation region indicating the reference position of the pattern 1.

The position detecting groove 15 is constructed by providing a plurality of grooves each having a different opening width as one group. Each of the groove sets is a combination of so-called bar-shaped grooves having an elongated rectangular planar shape. Then, as shown in the plan view of FIG. 1B, the bar-shaped groove sets G1 to G4 are formed on the four sides S of the square SQ.
The position detection groove 15 is arranged along Q1 to SQ4. The shaded portion in FIG. 1B is a concave portion, that is, a groove in the surface of the substrate. Further, the position detection groove forming region R shown in FIG.
The cross-sectional view of FIG. 2 corresponds to the cross section taken along the line AA shown in FIG.

By the way, each of the four groove sets G1 to G4 constituting the position detecting groove 15 is composed of a plurality of bar-shaped grooves. In the present embodiment, the plurality of bar-shaped grooves have different openings. It is composed of three types of grooves having widths W1, W2, and W3. That is, these are
Grooves 15a1 to 15a4 having an opening width W1 shown in (b),
Grooves 15b1 to 15b4 having an opening width W2 and an opening width W3
15c1 to 15c4. Further, in these grooves, two grooves having the same opening width and arranged to face each other across the square SQ are the same square SQ.
Are equally arranged from the center of each. For example,
The groove 15a1 is the groove 15a3, and the groove 15b2 is the groove 15b.
4 and the square SQ are equally spaced from the center of the square SQ.

Here, the opening width of each groove is "W1>
W2> W3 ”, and in the present embodiment, the opening widths W1, W2, and W3 are“ 1.5 μm ”,“ 1.0 μm ”, and“ 0.5 μm ”, respectively.
m ". The opening width of each groove forming the position detecting groove 15 is preferably set in the range of “500 nm to 2000 nm”.

Among the grooves having the above three kinds of opening widths, the grooves 15a1 to 15a4 having the widest opening width W1 form the square SQ by one of their long sides. Then, outside the grooves 15a1 to 15a4, the grooves 15b1 to 1 having the narrow opening widths W2 and W3 are sequentially formed in a radial direction from the center of the square SQ toward each of the four sides.
5b4 and the grooves 15c1 to 15c4 are arranged at equal intervals D, and form the position detection groove 15.

Next, a method of manufacturing the semiconductor device having the position detecting groove 15 will be described with reference to FIGS. First, as shown in FIG. 2A, an interlayer insulating film is formed by patterning a lower layer wiring 13 on a base film 11 above a semiconductor substrate and then filling the surface irregularities of the lower layer wiring 13 thereon to planarize it. 12 is formed into a film. In this embodiment, a silicon oxide film is used as the interlayer insulating film 12. Subsequently, a photoresist 16 is applied on the upper surface thereof, and a photomask including a contact hole for ensuring the connection with the lower layer wiring 13 and a position detection groove indicating the reference position of the formation pattern of the contact hole is used to form a photoresist. Expose and develop. Next, FIG.
As shown in (b), the interlayer insulating film 12 is formed using the photoresist 16 patterned by this development as a mask.
Are etched to form the contact hole 14 and the position detection groove 15. And after that, photoresist 1
Remove 6. Further, as shown in FIG. 2C, a conductive film 17 for filling the contact hole 14 with the plug wiring is deposited on the surface where the contact hole 14 and the position detection groove 15 are formed. In the present embodiment, as the conductive film 17, tungsten (W) of “400 is used.
nm ”, for example, using a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method.

By the way, in this case, as the conductive film 17, W
Alternatively, aluminum (Al) or the like may be used in a single layer, but titanium / titanium nitride is used for the purpose of improving adhesion to the interlayer insulating film 12, resistance to electromigration (EM) and resistance to stress migration (SM). A film such as a (Ti / TiN) alloy may be simultaneously formed to form a multi-layer. The conductive film 17 to be multi-layered is made of copper (Cu), Ti, iron (Fe) or the like having low resistance and high stress resistance when sufficient barrier properties can be obtained for the interlayer insulating film 12. May be. Furthermore, EM resistance and S
When improving the M resistance, the above W or TiN may be used in a single layer.

Then, as shown in FIG. 3A, this surface is polished by chemical mechanical polishing (CMP) to be planarized. At this time, a point of time when a large area of the interlayer insulating film 12 is exposed is an end point of this polishing process. As a result, the position detection groove 15 having different opening widths has a recess of the conductive film 17 embedded in the position detection groove 15 according to the opening width of each groove in the opening. In this case, the groove 15a1 having the widest opening width W1 (“1.5 μm”)
The recesses 18a1 to 18a4 having a comparatively gentle curved cross-sectional shape are formed in the openings of the holes 15a4 to 15a4 (FIG. 3A).
(Indicated by depressions 18a1 and 18a3). Further, the groove 15b having the second widest opening width W2 (“1.0 μm”)
The grooves 15a1 to 15a4 are provided in the openings of 1 to 15b4.
The recesses 18b1 to 18b4 having a narrower cross-sectional shape than the recesses 18a1 to 18a4 generated corresponding to are generated (illustrated by the recesses 18b1 and 18b3 in FIG. 3A). Then, these two types of grooves 15a1 to 15a4 and the groove 15
Opening width W3 (“0.5 μ
The grooves 15c1 to 15c4 having m ") and the contact hole 14 do not have a depression at the opening.

Further, as shown in FIG. 3B, a conductive film 19 made of Al, silicon (Si), and Cu is formed on the surface including the depressions 18a1 to 18a4 and the depressions 18b1 to 18b4 to form the upper wiring. To be deposited as. At this time, the depression 18a1 is formed on the surface on which the conductive film 19 is deposited.
~ 18a4 and depressions 18b1-18b4,
Recesses 20a1 to 20a4 and Recesses 20b1 to 20b4
Occurs.

Then, in order to pattern the upper layer wiring, these depressions 20a1 to 20a4 and depressions 20b1 are formed.
A photoresist is applied to the surface of the conductive film 19 containing 20 to 20b4, and the photoresist is exposed using a photolithography technique.
develop. Thereby, together with the mask 21 for forming the pattern of the upper layer wiring, the position accuracy pattern 2 for measuring the overlay error of the upper layer wiring with respect to the lower layer wiring.
2 is formed. After that, the relative position of the position accuracy pattern 22 is measured with respect to the depression formed corresponding to the position of the position detection groove 15. Thus, based on the amount of deviation of the position accuracy pattern 22 from the ideal position, the lower layer wiring 13
The overlay error of the pattern of the upper layer wiring with respect to the pattern of is measured.

When the overlay error measured in this way is within a predetermined range, the conductive film 19 is subsequently etched by using the developed photoresist as a mask to pattern the upper wiring (not shown). If the overlay error exceeds a predetermined value, the entire surface of the photoresist is removed, a new photoresist is applied, and then exposure and development are performed again to re-form the mask. . Then, when the measured overlay error is within a predetermined range, the conductive film 19 is etched using the mask.

Further, the information of the overlay error obtained in this way is fed back as a position control parameter at the time of exposure of the upper layer wiring with respect to the semiconductor substrate which will be performed thereafter. As a result, in those semiconductor substrates, it is possible to reduce the overlay error of the pattern of the upper layer wiring with respect to the pattern of the lower layer wiring.

By the way, in the present embodiment, when the conductive film 19 for forming the upper layer wiring is deposited, the widths corresponding to the plurality of grooves forming the position detection groove 15 having different opening widths are formed. The case where a plurality of depressions 20a1 to 20a4 and depressions 20b1 to 20b4 are different is illustrated. Then, when measuring the overlay error of the pattern of the upper layer wiring with respect to the pattern of the lower layer wiring 13, one that can obtain the highest recognition accuracy by an image recognition device (not shown) is selectively used. In the present embodiment, among the depressions formed on the surface of the conductive film 19,
The above-mentioned overlay error is measured using the narrower recesses 20b1 to 20b4. As a result, more accurate measurement can be performed as compared with the case of using the gentle depressions 20a1 to 20a4 having a wider width.
In other words, it is possible to realize a more accurate overlay of the pattern of the lower layer wiring 13 and the pattern of the upper layer wiring.

As described above, according to the semiconductor device and the method of manufacturing the same according to the first embodiment, the following effects can be obtained. (1) As the position detection groove 15, a groove having different opening widths is set as one set, and the groove sets G1 to G4 are combined. Therefore, when the conductive film 19 for forming the upper layer wiring is deposited, the position detection groove 1 can be easily and surely formed.
The depression corresponding to the position of 5 can be obtained.

(2) Further, since the position detection groove 15 is formed by combining the groove groups G1 to G4, the same is used to more surely obtain a recess corresponding to the position of the position detection groove 15. The area occupied by the position detection groove 15 on the substrate surface can be minimized.

(3) When a plurality of recesses having different widths are obtained corresponding to the position of the position detection groove 15, the position among the recesses reflecting the position detection groove 15 is obtained. It is possible to select one that can recognize the highest accuracy and use it as the reference position of the pattern of the lower layer wiring 13. Thereby, the reference position of the pattern of the lower layer wiring 13 can be recognized more accurately. In the example shown in the present embodiment, two types of depressions 20a1 having different widths are provided.
20a4 and 20b1 to 20b4 of narrower width are used as the reference position of the pattern of the lower layer wiring 13 to measure the overlay error of the pattern of the upper layer wiring with respect to it more accurately. Will be able to.

(4) The four groove groups G1 to G4 are arranged along the four sides of the square SQ. Therefore, the depressions corresponding to the plurality of grooves having different opening widths are formed along the four sides of the square SQ, and the recognition can be easily performed by the position detection on the two axes orthogonal to each other. Become. Further, in each of the grooves of each set, two grooves having the same opening width, which are arranged to face each other across the square SQ, are arranged at equal intervals from the center of the same square SQ. ing. Then, each bar-shaped groove is separated by an equal distance D,
The squares SQ are sequentially arranged from the center of the square SQ in a radial direction toward the four sides in a direction from a groove having a wide opening width to a groove having a narrow opening width. For this reason, it is possible to make the recognition of the depression that occurs corresponding to the position detection groove 15 even easier.

(Second Embodiment) Next, a semiconductor device and a method of manufacturing the same according to the second embodiment of the present invention will be described with reference to FIG. 4 focusing on the points different from the first embodiment. ~ It demonstrates using FIG.

Also in the semiconductor device of the second embodiment, the wiring is formed in a multi-layer structure, and the wiring of each layer is sequentially formed through the plug wiring embedded in the interlayer insulating film. Is connected to the upper wiring.
And when superimposing the pattern of the upper layer wiring on the pattern of the lower layer wiring buried under the interlayer insulating film,
In order to measure the overlay error, the interlayer insulating film is provided with a position detection groove that indicates the reference position of the lower wiring and the pattern of the interlayer insulating film.

FIG. 4 is a diagram showing a planar shape of such a position detecting groove. In FIG. 4 as well, the hatched area is the groove. In the semiconductor device illustrated in the present embodiment, the laminated cross-sectional structure of the upper layer wiring and the lower layer wiring sandwiching the interlayer insulating film is basically the same as that of the semiconductor device described in the first embodiment. Is the same.

As shown in FIG. 4, the position detecting groove 25 provided in this semiconductor device has an opening width W (“1.0 μm”).
4 of the same shape are arranged along the four sides of the square. And these grooves 25a-25d
Each have two grooves arranged so as to be opposed to each other in a planar shape symmetrical with respect to the opposed center.

In the present embodiment, the groove 25
The distance L between a and the groove 25c and between the groove 25b and the groove 25d
1 is set to “20 μm” between the axes of the grooves. The opening width W of these grooves is “0.5 μm to 2.0 μm”.
It is preferable to set in the range of.

By the way, each of the grooves 25a to 25a forming the position detecting groove 25 provided in the semiconductor device of the present embodiment.
5d is provided with a planar "key" portion in which each end portion is bent at a right angle in the direction toward the square. In a groove provided with such a "key" portion, when a conductive film is embedded in the groove and the conductive film is polished and flattened by a CMP method or the like, a dent is formed in the vicinity of the central portion of the opening of the groove. It has been confirmed by experiments by the inventors that they are easily formed.

In the present embodiment, the length L2 of the "key" portion is set to "1 μm". The length L2 of the “key” portion is preferably set in the range of “0.5 μm to 3.0 μm”. Further, when the conductive film is flattened, a depression corresponding to the position detection groove 25 is likely to be formed by bending the “key” provided in each of the grooves 25a to 25d in a direction facing a square. It was also confirmed by experiments by the inventors that the case becomes more remarkable.

FIG. 5 is a graph for explaining such a tendency.
It is a figure which shows notionally the relationship between the planar shape of each said groove | channel 25a-25d, and the shape of depression 38a-38d produced corresponding to it. As shown in Figure 5, the "key" provided in the groove
Is provided in a direction facing the square, the depression 38
Good formation of a to 38d (FIG. 5C). Also,
In the case where the recesses 38a to 38d are provided outward, the curved shapes of the recesses 38a to 38d are gentler (FIG. 5B). On the other hand, when the “key” is not provided, the depressions 38a to 38d are not formed (FIG. 5).
(A)). That is, as shown in FIG. 5C, when the “key” portion is provided in the direction of the square with respect to the bar-shaped groove, the depression formed corresponding to the “key” portion can be more reliably and accurately formed. You will be able to recognize.

Next, a method of manufacturing a semiconductor device having the position detecting groove 25 will be described with reference to FIGS. 6A and 6B showing the sectional structure of each step corresponding to the section taken along the line BB in FIG. This will be described with reference to FIG. The method of manufacturing the semiconductor device according to the second embodiment is also basically the same as that described in the first embodiment. Therefore, regarding the material of each film and the film forming method thereof exemplified in the present embodiment,
Since the example in the first embodiment can be used, the description thereof is omitted.

That is, first, as shown in FIG.
After the lower layer wiring 33 is patterned on the base film 31 above the semiconductor substrate, an interlayer insulating film 32 is formed on the lower layer wiring 33 for filling the surface irregularities of the lower layer wiring 33 and flattening the surface. Subsequently, a photoresist 36 is applied on the upper surface thereof, and a photomask including a contact hole for securing the connection with the lower layer wiring 33 and a position detection groove indicating the reference position of the formation pattern of the contact hole is used to form a photoresist. Expose and develop. Next, as shown in FIG.
Photoresist 3 patterned by this development
The interlayer insulating film 32 is etched by using 6 as a mask to form the contact hole 34 and the position detection groove 25. After that, the photoresist 36 is removed. Further, as shown in FIG. 6C, a conductive film 37 for filling the contact hole 34 with the plug wiring is formed on the surface where the contact hole 34 and the position detection groove 25 are formed.
Deposit.

Then, as shown in FIG. 7A, this surface is polished and planarized by the chemical mechanical polishing (CMP) method. At this time, since the position detection groove 25 has a planar shape in which each end of the groove that constitutes the position detection groove 25 is bent in a “key” shape in the direction toward the square, the conductivity embedded in the position detection groove 25. The membrane 37 has a depression 38a at the center of its opening.
Yields ~ 38d. At this time, the contact hole 3
The conductive film 37 embedded in 4 does not have a depression in its opening.

Further, as shown in FIG. 7B, a conductive film 39 for forming an upper layer wiring is deposited on the surface including the depressions 38a to 38d. At this time, depressions 40a to 40d are formed on the surface on which the conductive film 39 is deposited, corresponding to the depressions 38a to 38d.

Then, in order to pattern the upper wiring, a photoresist is applied to the surface of the conductive film 39 including the depressions 40a to 40d, and this is exposed and developed by using a photolithography technique. As a result, the position accuracy pattern 42 for measuring the overlay error of the upper layer wiring with respect to the lower layer wiring is formed together with the mask 41 for forming the pattern of the upper layer wiring. After that, the relative position of the position accuracy pattern 42 is measured with respect to the recess formed corresponding to the position of the position detection groove 35. In this way, the overlay error of the pattern of the upper layer wiring with respect to the pattern of the lower layer wiring 33 is measured based on the amount of deviation of the position accuracy pattern 42 from the ideal position.

Then, similarly to the first embodiment, if the overlay error is within a predetermined range in the present embodiment, subsequently, the conductive film 39 is formed using the developed photoresist as a mask. Is etched to form a pattern of the upper layer wiring (not shown), and when it exceeds a predetermined value, the mask is formed again.

Further, the information of the overlay error obtained in this way can be fed back as a position control parameter at the time of exposure of the upper layer wiring with respect to the semiconductor substrate, which is performed later, as in the case of the first embodiment. It is the same.

As described above, by forming the depression corresponding to the position of the position detection groove 25 on the surface of the conductive film 39 more reliably, the amount of deviation of the position accuracy pattern 42 from the ideal position can be measured more accurately. Therefore, the pattern of the lower layer wiring 13 and the pattern of the upper layer wiring can be more accurately superimposed.

As described above, according to the semiconductor device and the method of manufacturing the same according to the second embodiment, (1) to (1) obtained in the first embodiment described above can be obtained.
The following effects based on the effect of (4) can be obtained.

(1 ') The position detecting groove 25 has a planar "key-shaped" portion in which each of the grooves 25a to 25d constituting the position detecting groove is bent at a right angle in the direction toward the square. There is. Therefore, when the conductive film 37 is buried in the contact hole 34 and the like and is planarized,
Depressions 38a to 38 near the center of the openings of the grooves 25a to 25d
d is easily formed. Therefore, even if the conductive film 39 for forming the upper wiring is further deposited on the surface of the flattened and exposed interlayer insulating film 32, the depressions 40a to 40d corresponding to the positions of the position detection grooves 25 are formed on the surface. Since it is formed more reliably, the position of the same position detection groove 25 can be recognized more easily and with high accuracy.

(4 ') As the position detecting groove 25, grooves 25a to 25d having the same shape and having a predetermined opening width W are square.
Four are arranged along the side. Each of these grooves 25a-2
The groove 5d has a planar shape in which two grooves arranged to face each other are symmetrical with respect to the center of the groove. Therefore, the depressions 40a to 40 corresponding to the position of the same position detection groove 25, which serves as a reference position when measuring the relative position of the position accuracy pattern 42 with respect to the lower layer wiring 33 and the position detection groove 25.
Similarly to the position detection groove 25, d is also formed along the square, and the recognition can be easily performed by the position detection on the two axes orthogonal to each other.

(Third Embodiment) Next, the third embodiment of the semiconductor device and the method of manufacturing the same according to the present invention will be focused on the points different from the first and second embodiments. Will be described with reference to FIGS. 8 to 10, 16 and 17.

As described above, when the pattern overlay error is measured on the substrate surface of the semiconductor substrate, the reference layer (lower layer) that serves as a reference for alignment and the processed layer (upper layer) that is to be aligned with the reference layer are aligned. A mark indicating the reference position for each measurement is provided. Then, the relative position of these marks is measured and used to evaluate the overlay accuracy, so that the precise position accuracy of each layer pattern is maintained. At this time, as the target mark formed on the reference layer, a square pattern having a side length of several tens of micrometers is often used, and the position accuracy mark to be superposed on the square pattern has a square shape having a half size thereof. Is often used. The position of the position accuracy mark with respect to this target mark is optically measured, and this is fed back as a position control parameter of the exposure apparatus in the subsequent alignment.

When a box-shaped pattern is used as the target mark, the size of the processed pattern in the actual device (corresponding to the region R1 in FIG. 1A) is "0.25 μm because the processing is extremely large area. "
It has been found that the following problems are caused in microfabrication as the region approaches the (quarter micron) region. This occurs due to a so-called microloading effect that an extremely large etching rate difference occurs between the processing pattern in the device and the target mark pattern.

FIG. 16 is a graph showing the relationship between the length of one side (horizontal axis) and the corresponding etching depth (vertical axis) when etching such a box-shaped square pattern. In this graph, the value of the etching depth on the vertical axis is shown as a standardized numerical value. Figure 1
As shown in the graph of FIG. 6, for example, in a square pattern having a side length of “0.3 μm”, the etching depth is reduced by about 10% as compared with a square pattern having a sufficiently long side length. ing. In other words, when appropriate etching conditions are applied to form a pattern having a side length of “0.3 μm”, the box-shaped target pattern portion formed together with the pattern is processed. Approximately 10% of the film is etched in terms of film etching. That is, the base of the film to be processed is damaged. Further, as also shown in FIG. 16, the difference in etching depth caused by the microloading effect is that the length of one side of the square pattern is “0.4 μm”.
It can be seen that there is a tendency to appear from the vicinity of about "m".

FIG. 17 is a partial sectional view of the substrate showing how the base is damaged. As shown in FIG. 17A, a film to be processed 143 is deposited on the base film 141 above the semiconductor substrate. Then, a photoresist 146 for etching the same is applied on the upper surface thereof, and the photoresist 146 is exposed and developed by a photolithography technique to be processed into a pattern including a box-shaped target pattern having a long side. Then, using the patterned resist 146 as a mask, the film 143 to be processed is anisotropically etched to form a contact hole 144 and a box-shaped target pattern (position detection groove) 145. At this time, if etching is performed under the condition that the contact hole 144, which is the processing pattern in the device, is formed optimally, the base film 141 is formed on the bottom surface of the target pattern 145 having one side larger than the processing dimension.
A damaged portion 148 is generated at

This phenomenon causes non-uniform peeling of the material in the damaged portion 148 during the subsequent film formation, which greatly reduces the production yield as an integrated circuit device such as an LSI.

Therefore, in the third embodiment, even when the fine patterns are superposed using the box-shaped target pattern, the reference layer and the processed layer can be formed without damaging the base. Accurately measure the overlay error of the patterns, and thus realize highly accurate overlay of both patterns.

Therefore, the semiconductor device of the present embodiment has the position detection groove 5 having the sectional shape and the planar shape shown in FIG.
Have five. The cross-sectional view of FIG. 8A shows a cross section taken along the line CC in the plan view of FIG. That is, in this semiconductor device, as shown in FIG. 8A, a lower layer wiring (not shown) is formed on a base film 51, and an unevenness of the surface due to the lower layer wiring is buried on the lower layer wiring to flatten the interlayer insulating film. 52 is formed. And
A contact hole 54 for ensuring connection from the upper surface to the lower layer wiring is patterned in the interlayer insulating film 52, and the contact hole 54 is filled with a plug wiring (not shown) to similarly connect to an upper layer (not shown). The connection is made. Along with the contact hole 54, the interlayer insulating film 52 is provided with a position detection groove 55 that indicates the reference position of the formation pattern of the lower layer wiring 53 and the interlayer insulating film 52.

Here, the position detection groove 55 is shown in FIG.
As shown in (b), it has a box-shaped target pattern as its planar shape. Then, inside the position detection groove 55, a square frame-shaped frame pattern is formed as an edge portion (outer box pattern) of the position detection groove 55 as a projection pattern 56 whose height is less than the depth of the groove.
The protrusions are formed in a nested manner in order along 55a. As for these frame patterns, three frame patterns 56a, 56b, and 56c are arranged from the outside with a separation distance of “0.3 μm”. That is, these frame patterns 56a
56c together with the outer box pattern 55a of the position detection groove 55 constitute a so-called line-and-space grating layout in which the bottom surface 58 of the position detection groove 55 is fragmented to localize its area.

In the present embodiment, the length of one side of the outer box pattern 55a is “20 μm”,
The width of the frame pattern is “0.3 μm” and the number of frame patterns is actually three or more. However, in order to schematically show this in FIG. 8, the number is shown as three. . Also,
Regarding the processing pattern in the device, the processing dimension of the contact hole 54 and the like is “0.3 μm”. The length of one side of the outer box pattern 55a is preferably set in the range of "18 to 30 µm".

Next, a method of manufacturing the semiconductor device having the position detecting groove 55 will be described with reference to FIGS. First, as shown in FIG. 9A, an interlayer insulating film 52 is formed on a base film 51 above a semiconductor substrate. Also in the present embodiment, as in the first and second embodiments, a silicon oxide film is used as the interlayer insulating film 52, and the film thickness thereof is set to "700 nm", for example. Continuing, a photoresist 61, for example "5
It is applied to a film thickness of "50 nm", which is exposed and developed.
At this time, when the exposure is performed, for example, krypton-
The exposure amount is "42 mJ / cm @ 2" using a fluorine (KrF) excimer laser stepper, and the development is performed by, for example, a dip development of "60 seconds".

Next, using the photoresist 61 as a mask, anisotropic etching is performed using a plasma etching apparatus as shown in FIG. 9B, and then the photoresist 61 is removed. The etching condition at this time is 1
The contact hole 54 having a square planar shape with a side length of “0.3 μm” is set so as to be optimally formed in the interlayer insulating film 52 made of a silicon oxide film with a film thickness of “700 nm”.

By the way, as described above, the protrusion pattern 56 in the position detecting groove 55 of the present embodiment has the same opening width of “0.3 μm” as the processing dimension of the contact hole 54.
m ”, the position detection groove 5 is formed by this etching.
The bottom surface of 5 is not overetched and damaged. At this time, the frame patterns 56a to 56c forming the grating have their upper portions (head portions) cut by the impact of plasma etching, and have a height of about 1/3 of the film thickness of the interlayer insulating film 52.

Then, as shown in FIG. 9C, a conductive film for filling the plug wiring is deposited in the contact hole 54, and the surface is polished and flattened by the CMP method. At this time, a point of time when the surface of the interlayer insulating film 52 is exposed in a region other than the contact hole 54 of the device processed portion is an end point of this polishing process. At this time, in the large-area position detection groove 55, the gratings having small height dimensions, that is, the frame patterns 56a to 56c, remain,
After flattening by polishing, depression 6 by dishing
Yields 2.

Thereafter, the conductive film for forming the upper wiring is deposited by the same steps as those in the first and second embodiments, and the resist is baked for patterning the conductive film. To do. At this time, the conductive film also has a recess corresponding to the edge of the recess 62. Therefore, a peak signal corresponding to the edge of this depression is obtained by the image recognition processing. This makes it possible to correctly recognize the position of the position detection groove 55 and accurately measure the overlay error with the pattern of the upper layer wiring. Then, it becomes possible to superimpose these patterns with high accuracy.

As described above, according to the semiconductor device and the method of manufacturing the same according to the third embodiment, the following effects can be obtained. (5) The frame patterns 56a to 56c are arranged as protrusions inside the position detection groove 55, which is a box-shaped target pattern, as protrusion patterns 56 whose height is less than the depth of the groove 55. There is. Therefore, in order to fill the plug wiring from the upper surface to the contact hole 54,
After depositing a conductive film and polishing and flattening it by the CMP method, a recess 62 is formed in the opening of the position detection groove 55. Further, even after depositing the conductive film of the upper layer wiring on the upper surface thereof, a dent reflecting the position of the dent 62 is formed, and the overlay error when the processing patterns are overlaid can be accurately measured. As a result, these patterns can be superposed with high accuracy.

(6) In the process of forming the groove 55, the protrusion patterns 56 having a height less than the depth of the position detecting groove 55 are removed by anisotropic etching from the upper portions of the frame patterns 56a to 56c. Formed automatically in the form. Therefore, it is possible to prevent the bottom surface of the position detection groove 55 from being over-etched and damaged. Thereby, in a subsequent process, when the conductive film or the like is embedded in the position detection groove 55, it is possible to avoid a phenomenon such as peeling occurring on the bottom surface thereof, and the position detection groove 55 is deposited at the time of depositing the conductive film. It becomes possible to suitably generate a depression corresponding to the above.

(Other Embodiments) The above embodiments may be modified as follows. The material of each film forming the semiconductor device illustrated in each of the above-described embodiments and the forming method thereof may be appropriately changed.

Also, as exemplified in each of the embodiments,
The various grooves and other values such as width, distance, thickness and depth may be changed as appropriate. The cross-sectional structure of the semiconductor device illustrated in each of the above embodiments may be changed as appropriate. Regarding a semiconductor device having an arbitrary laminated structure in which patterns are superposed through a flattening step instead of a structure in which a lower layer wiring, an interlayer insulating film, and an upper layer wiring are laminated on a base film, and a manufacturing method thereof, The invention can be widely applied.

The polishing and flattening of the conductive film at the time of forming the plug wiring illustrated in each of the above-mentioned embodiments do not necessarily have to be performed by the CMP method. -The planar shape as the position detection groove illustrated in each of the above embodiments may be appropriately changed. For example,
The following modifications can be made according to each embodiment.

In the first embodiment, the number of grooves forming each of the groove sets G1 to G4 forming the position detecting groove 15 is not limited to three, but may be two or four or more. Further, the distance between them may not be equal. Further, it is not necessary to sequentially provide the grooves having a narrow opening width in the direction away from the center of the square SQ, and the grooves may be arranged in the reverse order, or the opening widths may be randomly arranged. Further, it is not always necessary to dispose the two grooves having the same opening width and facing each other across the square SQ, equally spaced from the center of the square SQ.

Next, in the second embodiment, the "key" part of each of the grooves forming the position detecting groove 25 at each end is not in the direction facing the square but in the opposite direction, that is, outside the square. It may have a shape that is bent toward. Further, the refraction angle may not be a right angle. Furthermore, the end of each groove may have an arbitrary shape with a widened portion corresponding to the opening width, instead of the bent shape of the groove.

Further, in the third embodiment, it is not necessary that the projection pattern 56 of the position detection groove 55 has a square frame shape. For example, as shown in FIG. 10 (a), a planar shape may be adopted in which a plurality of projection patterns of similar “L-shaped” ridges are arranged. Further, as shown in FIG. 10B, a polygonal (including circular) columnar pattern such as a square may be regularly or randomly arranged to have a planar shape. In short, it is only necessary to fragment the bottom surface of the position detection groove 55 and localize the area thereof to the size of the processing size of the contact hole or the like.

Further, for example, in the above-mentioned first and second embodiments, it is not always necessary to dispose the bar-shaped groove or the set thereof along the four sides of the square, and it has the long side and the short side. They may be arranged along the four sides of the rectangle. Furthermore, regarding the arrangement of the grooves in the first and second embodiments, it is not necessary to arrange the grooves along the four sides of the rectangular shape. In addition, in the third embodiment, the outer box pattern 55a of the position detection groove 55.
Is not necessarily a square, and may be a rectangle having long sides and short sides. In short, after the above-mentioned flattening process, it is only necessary to form a recess corresponding to each position detection groove for highly accurate recognition.

[Brief description of drawings]

FIG. 1 is a view exemplifying a cross-sectional shape and a planar shape of a position detection groove provided in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 shows the semiconductor device of the first embodiment,
The figure which expands and illustrates the partial cross-sectional shape of the position detection groove vicinity in the manufacturing process.

FIG. 3 is an enlarged view illustrating a partial cross-sectional shape of the semiconductor device in the vicinity of a position detection groove in the manufacturing process thereof.

FIG. 4 is a diagram illustrating a planar shape of a position detection groove provided in a semiconductor device according to a second embodiment of the present invention.

5A and 5B are views for explaining the relationship between the shape of the position detection groove and the cross-sectional shape of the depression that occurs correspondingly.

FIG. 6 shows a semiconductor device according to the second embodiment,
The figure which expands and illustrates the partial cross-sectional shape of the position detection groove vicinity in the manufacturing process.

FIG. 7 is an enlarged view illustrating a partial cross-sectional shape of the semiconductor device in the vicinity of the position detection groove in the manufacturing process thereof.

FIG. 8 is a view exemplifying a cross-sectional shape and a plane shape of a position detection groove provided in a semiconductor device according to a third embodiment of the present invention.

FIG. 9 shows a semiconductor device according to the third embodiment,
The figure which expands and illustrates the partial cross-sectional shape of the position detection groove vicinity in the manufacturing process.

FIG. 10 is a diagram illustrating a planar shape of a position detection groove provided in a modification of the semiconductor device according to the third embodiment.

FIG. 11 is a diagram illustrating a cross-sectional shape of a position detection groove in a manufacturing process of a conventional semiconductor device.

FIG. 12 is a diagram for explaining the shape of a recess after flattening that occurs corresponding to a box-shaped position detection groove provided in the conventional semiconductor device.

13A and 13B are a plan view and a cross-sectional view illustrating a shape of a bar-shaped position detection groove provided in a conventional semiconductor device.

FIG. 14 is an enlarged view of a partial cross-sectional shape near a position detection groove in a manufacturing process of a conventional semiconductor device.

FIG. 15 is a diagram exemplifying an image recognition signal of a depression generated in the opening of the position detection groove.

FIG. 16 is a diagram illustrating a microloading effect.

FIG. 17 is an enlarged view of a partial cross-sectional shape near a position detection groove in a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

11 ... Base film, 12 ... Interlayer insulating film, 13 ... Lower layer wiring, 1
4 ... Contact hole, 15 ... Position detection groove, 15a1
15a4, 15b1 to 15b4, 15c1 to 15c4 ...
Grooves, 16 ... Photoresist, 17 ... Conductive film, 18a1
18a4, 18b1 to 18b4 ... hollow, 19 ... conductive film,
20a1 to 20a4, 20b1 to 20b4 ... hollow, 21
... Mask, 22 ... Position accuracy pattern, 25 ... Position detection groove, 25a to 25d ... Groove, 31 ... Underlayer film, 32 ... Interlayer insulating film, 33 ... Lower layer wiring, 34 ... Contact hole, 35
... Position detection groove, 36 ... Photoresist, 37 ... Conductive film,
38a to 38d ... Recess, 39 ... Conductive film, 40a to 40d
... depression, 41 ... mask, 42 ... position accuracy pattern, 51
... Base film, 52 ... Interlayer insulating film, 53 ... Lower layer wiring, 54 ...
Contact hole, 55 ... Position detection groove, 55a ... Outer box pattern, 56 ... Projection pattern, 56a-5
6c ... frame pattern, 58 ... bottom surface, 61 ... photoresist, 62 ... concave.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoshi Shimada             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Hiroomi Toyoba             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F-term (reference) 2H095 BE03                 5F033 HH09 JJ07 JJ08 JJ11 JJ18                       JJ19 JJ33 NN06 NN07 QQ01                       QQ09 QQ37 QQ48 VV00 WW01                       XX01 XX05 XX06 XX15                 5F046 AA20 EA03 EA04 EA06 EA09                       EA12 EA13 EA15 EA18 EA19                       EA22 EB01 EB05 EC05 FA09                       FC03

Claims (26)

[Claims] 1. A semiconductor device in which a position detection groove for forming an alignment mark at the time of superposition is provided in a base film above a semiconductor substrate, wherein the position detection groove has a different opening width. A semiconductor device comprising a combination of a plurality of grooves. 2. The semiconductor device according to claim 1, wherein the position detection groove includes a plurality of grooves having different opening widths as one group, and four groups are provided along four sides of a rectangle. 3. In the set of a plurality of grooves having different opening widths, two grooves having the same opening width and arranged to face each other across the rectangle are equal to each other from the center of the rectangle. The semiconductor device according to claim 2, wherein the semiconductor devices are spaced apart from each other. 4. A semiconductor device in which a position detection groove for forming an alignment mark at the time of superposition is provided in a base film above a semiconductor substrate, wherein the position detection groove has a predetermined opening width. A semiconductor device, wherein the semiconductor device is formed in a groove shape having, and the groove is provided with a widened portion for enlarging the predetermined opening width at each end portion thereof. 5. The semiconductor device according to claim 4, wherein the widened portion is provided in such a manner that each end of the groove is bent in the same direction. 6. The position detecting groove is arranged as four grooves along four sides of a rectangle, and the widening portion of each groove is set such that the refraction directions thereof are all directed to the rectangle. The semiconductor device according to claim 5, wherein 7. A semiconductor device in which a position detection groove for forming an alignment mark at the time of superposition is provided in a base film above a semiconductor substrate, wherein the position detection groove has a rectangular planar shape. A semiconductor device having a projection pattern of an arbitrary shape, the height of which is less than the depth of the groove, and which is formed while being formed. 8. The semiconductor device according to claim 7, wherein the protrusion pattern comprises a plurality of protrusion patterns. 9. The semiconductor device according to claim 8, wherein the ridge pattern comprises a plurality of rectangular frame patterns formed in such a manner that they are sequentially nested along an edge of the rectangular groove. 10. The semiconductor device according to claim 7, wherein the protrusion pattern is composed of a plurality of polygonal patterns which are spaced apart from each other in the rectangular groove. 11. The separation distance between the projection pattern and the edge of the rectangular groove and the separation distance between adjacent projection patterns are 0.4 μm or less.
The semiconductor device according to any one of 1. 12. A step of forming a row of grooves, which is a combination of a plurality of grooves each having a different opening width, as a position detection groove on a base film above a semiconductor substrate, and a step of forming a first film on the upper surface thereof. The method includes a step of flattening the first film using the base film as a stopper film, and a step of forming a second film on the flattened first film. A method for manufacturing a semiconductor device, wherein a recess formed corresponding to a groove array formed as the position detection groove is used as an alignment mark. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the position detection groove has a plurality of grooves each having a different opening width as one group, and four groups are formed along four sides of a rectangle. . 14. A set of a plurality of grooves having different opening widths is formed such that two grooves facing each other across the rectangle and having the same opening width are equally spaced from the center of the rectangle. The method for manufacturing a semiconductor device according to claim 13, wherein 15. The position measurement is performed by selectively using one of the depressions formed corresponding to the groove row formed as the position detection groove that can obtain the highest recognition accuracy. 15. The method for manufacturing a semiconductor device according to any one of 14. 16. An insulating film in which a contact hole is formed along with the position detection groove is used as the base film, and a conductive film embedded in a contact hole of the insulating film is used as the first film, and the second film is used. 13. A conductive film formed as a wiring layer on the upper surface of the insulating film is used as the film of claim 12.
16. The method for manufacturing a semiconductor device according to any one of 1 to 15. 17. The method of manufacturing a semiconductor device according to claim 12, wherein a chemical mechanical polishing method is used for flattening the first film. 18. A step of forming, as a position detection groove, a groove having a predetermined opening width and having a widened portion for enlarging the predetermined opening width at each end thereof in a base film above a semiconductor substrate. A step of forming a first film on the upper surface thereof, a step of planarizing the first film by using the base film as a stopper film, and a step of forming a second film on the planarized first film. A method of manufacturing a semiconductor device, comprising a step of forming a film, wherein a recess formed corresponding to the groove formed as the position detection groove on the surface of the second film is used as an alignment mark. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the widened portion is formed such that each end of the groove is bent in the same direction. 20. As the position detection groove, four grooves are formed along each of the four sides of the rectangle, and the widened portions of each of the grooves are set such that the refraction directions are all in the direction of the rectangle. 20. The method for manufacturing a semiconductor device according to item 19. 21. An insulating film in which a contact hole is formed along with the position detection groove is used as the base film, and a conductive film embedded in a contact hole of the insulating film is used as the first film, and the second film is used. 19. A conductive film formed as a wiring layer on the upper surface of the insulating film is used as the film of claim 18.
21. The method for manufacturing a semiconductor device according to any one of 20 to 20. 22. The method of manufacturing a semiconductor device according to claim 18, wherein a chemical mechanical polishing method is used for flattening the first film. 23. An underlying film above a semiconductor substrate is provided with a groove having a rectangular planar shape as a position detecting groove, and a projection pattern of an arbitrary shape having a height less than the depth of the groove is provided on the inner bottom portion thereof. Mode, a step of forming a first film on the upper surface thereof, a step of planarizing the first film using the base film as a stopper film, and the planarized first film And a step of depositing a second film on the upper surface of the second film, wherein a depression formed corresponding to the groove formed as the position detection groove on the surface of the second film is used as an alignment mark. 24. The method of manufacturing a semiconductor device according to claim 23, wherein a plurality of protrusion patterns are used as the protrusion patterns. 25. The method of manufacturing a semiconductor device according to claim 24, wherein a plurality of rectangular frame patterns that are sequentially nested along the edges of the rectangular groove are used as the ridge patterns. 26. The method of manufacturing a semiconductor device according to claim 25, wherein a plurality of polygonal patterns that are spaced apart from each other in the rectangular groove are used as the protrusion patterns.