CN114200796A - Alignment mark and forming method thereof - Google Patents

Alignment mark and forming method thereof Download PDF

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Publication number
CN114200796A
CN114200796A CN202010911176.8A CN202010911176A CN114200796A CN 114200796 A CN114200796 A CN 114200796A CN 202010911176 A CN202010911176 A CN 202010911176A CN 114200796 A CN114200796 A CN 114200796A
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China
Prior art keywords
opening
mark
layer
forming
processed
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CN202010911176.8A
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CN114200796B (en
Inventor
张瑞麟
邢滨
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

An alignment mark and a forming method thereof comprise: providing a substrate, wherein the substrate comprises a mark area, and a layer to be processed is arranged on the mark area; forming a first mark opening in the layer to be processed on the mark area; and forming a second mark opening in the layer to be processed on the mark area by taking the first mark opening as an alignment mark, wherein the first mark opening and the second mark opening are separated from each other. Through forming first mark opening and second mark opening in the mark zone, and first mark opening and second mark opening are mutually independent, make first mark opening with second mark opening can not produce the overlap, avoids because of repeated sculpture the sculpture that causes in the mark zone pierces through, and then has avoided because of the sculpture pierces through the production of the sculpture environmental pollution that causes and residue, has avoided the influence that causes the device structure in the residue in the mark zone enters into the device zone, has effectively promoted the performance of the semiconductor structure of final formation.

Description

Alignment mark and forming method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an alignment mark and a forming method thereof.
Background
The photolithography technique is a crucial technique in the semiconductor manufacturing technology, and can transfer a pattern from a mask to the surface of a silicon wafer to form a semiconductor product meeting design requirements. In the photoetching process, firstly, through an exposure step, light irradiates on a silicon wafer coated with photoresist through a light-transmitting or light-reflecting area in a mask and performs photochemical reaction with the photoresist; then, through a developing step, a photoetching pattern is formed by utilizing the dissolution degree of photosensitive and non-photosensitive photoresist to a developer, so that the transfer of a mask pattern is realized; and then, etching the silicon wafer based on the photoetching pattern formed by the photoresist layer through an etching step, and further transferring the mask plate pattern onto the silicon wafer.
Before photolithography, the wafer must be aligned so that the pattern can be accurately transferred to the photoresist layer of the wafer. In the prior art, there are two kinds of alignment marks, namely a zero layer mark and a scribing groove mark.
However, the alignment mark formed by the prior art still has many problems.
Disclosure of Invention
The invention provides an alignment mark and a forming method thereof, which can effectively improve the performance of a finally formed semiconductor structure.
To solve the above problems, the present invention provides an alignment mark, including: the substrate comprises a mark area, and the mark area is provided with a layer to be processed; a first mark opening in the layer to be processed on the mark region; and the first mark opening and the second mark opening are separated from each other.
Optionally, the substrate further includes: a device region; the mark region surrounds the device region, the layer to be processed is also located on the device region, and the first mark opening and the second mark opening are located at corner positions of the device region.
Optionally, the device further includes a plurality of first device openings and a plurality of second device openings located in the layer to be processed on the device region.
Optionally, the first marker opening comprises: the liquid crystal display panel comprises a first opening extending along a first direction and a second opening extending along a second direction, wherein the first direction is vertical to the second direction, and the side wall of the second opening is exposed out of the first opening.
Optionally, the second marker opening comprises: a third opening and a fourth opening extending along the first direction, the fourth opening exposing a sidewall of the third opening, the first opening and the third opening being arranged in parallel along the second direction, the third opening having a first width dimension along the second direction, the fourth opening having a second width dimension along the second direction, the second width dimension being greater than the first width dimension; the second opening and the fifth opening are arranged in parallel along the first direction, the fifth opening has a third width dimension along the first direction, the sixth opening has a fourth width dimension along the first direction, and the fourth width dimension is greater than the third width dimension.
Optionally, the first width dimension ranges from 0.3 μm to 0.5 μm; the third width dimension is in a range of 0.3 μm to 0.5 μm.
Optionally, the first mark opening and the second mark opening have a first spacing dimension therebetween.
Optionally, the first spacing dimension is a spacing dimension between the first opening and the third opening, or a spacing dimension between the second opening and the fifth opening.
Optionally, the first pitch size ranges from 0.2 μm to 0.4 μm.
Optionally, the method further includes: and the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are separated from each other.
Optionally, a second spacing dimension is provided between the third mark opening and the second mark opening, and a third spacing dimension is provided between the fourth mark opening and the third mark opening.
Optionally, the third marker opening comprises: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
Optionally, the fourth marker opening comprises: the liquid crystal display device comprises an eleventh opening extending along the first direction, a twelfth opening extending along the second direction, wherein the twelfth opening exposes a side wall of the eleventh opening, a thirteenth opening extending along the first direction, the thirteenth opening exposes a side wall of the twelfth opening, and a fourteenth opening extending along the second direction, and the fourteenth opening exposes a side wall of the thirteenth opening.
Optionally, the device further includes a plurality of third device openings and a plurality of fourth device openings located in the layer to be processed on the device region.
Optionally, the substrate further includes: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the layer to be etched.
Optionally, the layer to be etched includes: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
Optionally, the method further includes: a first stop layer between the substrate and the device layer; a second stop layer between the device layer and the hard mask layer; and the third stop layer is positioned between the hard mask layer and the layer to be processed.
Correspondingly, the technical scheme of the invention also provides a method for forming the alignment mark, which comprises the following steps: providing a substrate, wherein the substrate comprises a mark area, and a layer to be processed is arranged on the mark area; forming a first mark opening in the layer to be processed on the mark area by adopting first patterning processing; and carrying out second patterning treatment on the layer to be treated by taking the first mark opening as an alignment mark, and forming a second mark opening in the layer to be treated on the mark area, wherein the first mark opening and the second mark opening are mutually separated.
Optionally, the first graphic processing method includes: forming a first patterning layer on the layer to be processed, wherein the first patterning layer exposes a part of the top surface of the layer to be processed; etching the layer to be processed by taking the first patterning layer as a mask, and forming a first mark opening in the layer to be processed; removing the first patterning layer after forming the first mark opening.
Optionally, before forming the first patterned layer, the method further includes: and forming a first sacrificial layer and a first anti-reflection layer positioned on the first sacrificial layer on the layer to be processed, wherein the first patterning layer is positioned on the first anti-reflection layer.
Optionally, the second graphic processing method includes: forming a second patterned layer on the layer to be processed, wherein the second patterned layer exposes a part of the top surface of the layer to be processed; etching the layer to be processed by taking the second patterning layer as a mask, and forming a second mark opening in the layer to be processed; removing the second patterned layer after forming the second mark opening.
Optionally, before forming the second patterned layer, the method further includes: and forming a second sacrificial layer on the layer to be processed, wherein the second sacrificial layer fills the first mark opening and a second anti-reflection layer positioned on the second sacrificial layer, and the second patterning layer is positioned on the second anti-reflection layer.
Optionally, the substrate further includes: a device region; the mark region surrounds the device region, the layer to be processed is also located on the device region, and the first mark opening and the second mark opening are located at corner positions of the device region.
Optionally, in the process of forming the first mark opening, the method further includes: a plurality of first device openings are formed in the layer to be processed on the device region.
Optionally, in the process of forming the second mark opening, the method further includes: and forming a plurality of second device openings in the layer to be processed on the device area.
Optionally, the first marker opening comprises: the liquid crystal display panel comprises a first opening extending along a first direction and a second opening extending along a second direction, wherein the first direction is vertical to the second direction, and the side wall of the second opening is exposed out of the first opening.
Optionally, the second marker opening comprises: a third opening and a fourth opening extending along the first direction, the fourth opening exposing a sidewall of the third opening, the first opening and the third opening being arranged in parallel along the second direction, the third opening having a first width dimension along the second direction, the fourth opening having a second width dimension along the second direction, the second width dimension being greater than the first width dimension; the second opening and the fifth opening are arranged in parallel along the first direction, the fifth opening has a third width dimension along the first direction, the sixth opening has a fourth width dimension along the first direction, and the fourth width dimension is greater than the third width dimension.
Optionally, the first width dimension ranges from 0.3 μm to 0.5 μm; the third width dimension is in a range of 0.3 μm to 0.5 μm.
Optionally, the first mark opening and the second mark opening have a first spacing dimension therebetween.
Optionally, the first spacing dimension is a spacing dimension between the first opening and the third opening, or a spacing dimension between the second opening and the fifth opening.
Optionally, the first pitch size ranges from 0.2 μm to 0.4 μm.
Optionally, after forming the first mark opening and the second mark opening, the method further includes: performing third patterning processing on the layer to be processed by taking the second mark opening as an alignment mark, and forming a third mark opening in the layer to be processed; and performing fourth patterning processing on the layer to be processed by taking the third mark opening as an alignment mark, and forming a fourth mark opening in the layer to be processed, wherein the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are separated from each other.
Optionally, a second spacing dimension is provided between the third mark opening and the second mark opening, and a third spacing dimension is provided between the fourth mark opening and the third mark opening.
Optionally, the third marker opening comprises: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
Optionally, the fourth marker opening comprises: the liquid crystal display device comprises an eleventh opening extending along the first direction, a twelfth opening extending along the second direction, wherein the twelfth opening exposes a side wall of the eleventh opening, a thirteenth opening extending along the first direction, the thirteenth opening exposes a side wall of the twelfth opening, and a fourteenth opening extending along the second direction, and the fourteenth opening exposes a side wall of the thirteenth opening.
Optionally, in the process of forming the third mark opening, the method further includes: and forming a plurality of third device openings in the layer to be processed on the device area.
Optionally, in the process of forming the fourth mark opening, the method further includes: and forming a plurality of fourth device openings in the layer to be processed on the device area.
Optionally, the substrate further includes: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the layer to be etched.
Optionally, the layer to be etched includes: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
Optionally, the method further includes: a first stop layer between the substrate and the device layer; a second stop layer between the device layer and the hard mask layer; and the third stop layer is positioned between the hard mask layer and the layer to be processed.
Optionally, after forming the first device opening, the second device opening, the third device opening, and the fourth device opening, the method further includes: and forming first side walls on the side walls of the first device opening, the second device opening, the third device opening and the fourth device opening.
Optionally, in the process of forming the first sidewall, the method further includes: and forming second side walls on the side walls of the first mark opening, the second mark opening, the third mark opening and the fourth mark opening.
Optionally, after the first side wall and the second side wall are formed, the method further includes: removing the layer to be treated; and etching the substrate by using the first side wall and the second side wall as masks, and forming a patterned opening in the substrate.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the structure of the technical scheme, the first mark opening and the second mark opening are positioned in the mark area and are separated from each other, so that the first mark opening and the second mark opening are not overlapped, etching penetration caused by repeated etching of the same position in the mark area is avoided, further, etching environment pollution and residue generation caused by etching penetration are avoided, the influence on a device structure caused by the fact that the residue in the mark area enters the device area is avoided, and the performance of the finally formed semiconductor structure is effectively improved.
In the forming method of the technical scheme, the first mark opening and the second mark opening are formed in the mark area and are separated from each other, so that the first mark opening and the second mark opening are not overlapped, etching penetration caused by repeated etching of the same position in the mark area is avoided, further, etching environment pollution and residue generation caused by etching penetration are avoided, the influence of the residue in the mark area entering the device area on the device structure is avoided, and the performance of the finally formed semiconductor structure is effectively improved.
Drawings
Fig. 1 to 3 are schematic structural views of an alignment mark;
fig. 4 to 16 are schematic structural diagrams of steps of an alignment mark forming method according to an embodiment of the invention.
Detailed Description
As described in the background, however, the alignment marks formed by the prior art still have problems. The following detailed description will be made in conjunction with the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a mark region, and the substrate has a layer 101 to be processed; forming a first sacrificial layer 102 on the layer to be processed 101; forming a first patterning layer 103 on the first sacrificial layer 102, wherein the first patterning layer 103 exposes a portion of a top surface of the first sacrificial layer 102; and etching the first sacrificial layer 102 and the layer to be processed 101 by using the first patterning layer 103 as a mask, and forming a first mark opening 104 in the layer to be processed 101.
Referring to fig. 2, after the first mark opening 104 is formed, the first patterning layer 103 and the first sacrificial layer 102 are removed; forming a second sacrificial layer 105 on the layer to be processed 101, wherein the second sacrificial layer 105 fills the first mark opening 104; forming a second patterning layer 106 on the second sacrificial layer 105, the second patterning layer 106 exposing a top surface of a portion of the second sacrificial layer 105; and etching the second sacrificial layer 105 and the layer to be processed 101 by using the second patterning layer 106 as a mask, and forming a second mark opening 107 in the layer to be processed 101, wherein the first mark opening 104 and the second mark opening 107 are overlapped.
Referring to fig. 3, after the second mark opening 107 is formed, the second patterning layer 106 and the second sacrificial layer 105 are removed.
In this embodiment, the first mark opening 104 and the second mark opening 107 are used as alignment marks during a photolithography process, so as to facilitate device dimension measurement during a one-pass etching process. However, in this embodiment, since the first mark opening 104 and the second mark opening 107 are overlapped in the layer to be processed, the first mark opening 104 and the second mark opening 107 are both formed at the same position of the layer to be processed 101, and the layer to be processed 101 is easily etched and penetrated, so that an etching solution or an etching gas for etching the second mark opening 107 reacts with a hard mask layer below the layer to be processed, and a substance is easily remained in the hard mask layer, and the remaining substance easily enters a device region to affect a device structure; in addition, the gas generated after the reaction also causes the pollution of the etching environment.
On the basis, the invention provides an alignment mark and a forming method thereof, wherein a first mark opening and a second mark opening are formed in the mark area and are separated from each other, so that the first mark opening and the second mark opening are not overlapped, etching penetration caused by repeatedly etching the same position in the mark area is avoided, further etching environment pollution and residue generation caused by etching penetration are avoided, the influence on a device structure caused by the residue in the mark area entering the device area is avoided, and the performance of the finally formed semiconductor structure is effectively improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 16 are schematic structural diagrams illustrating a process of forming an alignment mark according to an embodiment of the present invention.
Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view taken along line a-a in fig. 4, and fig. 4 is a top view of fig. 5, providing a substrate including a mark region I having a layer 203 to be processed thereon.
In this embodiment, the substrate further includes: a device region II; the mark region I surrounds the device region II, and the layer to be processed 203 is also located on the device region II.
The mark region I is used for forming a corresponding alignment mark in each photoetching process, and provides a measurement reference for a device structure formed in the device region II. The device region II is used for forming a device structure having an actual functional role, and while the device structure is formed in the device region II, the corresponding device structure is also formed in the mark region I due to the process of the global process, but the device structure formed in the mark region I does not have an actual functional role.
In this embodiment, the substrate further includes: the mask comprises a substrate 200 and a layer to be etched, wherein the layer to be etched is located on the substrate 200.
In this embodiment, the layer to be etched includes: the device comprises a device layer 201 and a hard mask layer 202 located on the device layer 201, wherein the layer to be processed 203 is located on the hard mask layer 202.
In this embodiment, the material of the device layer 201 is a low-K dielectric material.
In this embodiment, the hard mask layer 202 is made of titanium nitride; in other embodiments, the hard mask layer may also be made of tantalum nitride.
In this embodiment, the method further includes: a first stop layer 204, the first stop layer 204 being located between the substrate 200 and the device layer 201; a second stop layer 205, the second stop layer 205 being located between the device layer 201 and the hard mask layer 202; a third stop layer 206, the third stop layer 206 being located between the hard mask layer 202 and the layer to be processed 203.
The first stop layer 204, the second stop layer 205 and the third stop layer 206 function to: and stopping each etching process on the corresponding stop layer to avoid the etching process from damaging the lower layer structure.
Referring to fig. 6, 7 and 8, fig. 7 is an enlarged view of a portion a of fig. 6, and fig. 8 is a cross-sectional view taken along line B-B of fig. 7; a first patterning process is used to form a first mark opening 207 in the layer to be processed 203 on the mark region I.
In this embodiment, the first graphic processing method includes: forming a first patterning layer (not shown) on the layer to be processed 203, the first patterning layer exposing a portion of a top surface of the layer to be processed 203; etching the layer to be processed 203 by using the first patterning layer as a mask, and forming the first mark opening 207 in the layer to be processed 203; after the first mark opening 207 is formed, the first patterning layer is removed.
In this embodiment, the material of the first patterning layer is photoresist.
In this embodiment, before forming the first patterned layer, the method further includes: a first sacrificial layer, a first anti-reflection layer (not shown) on the first sacrificial layer, and the first patterning layer on the first anti-reflection layer are formed on the layer to be processed 203.
In this embodiment, the first sacrificial layer is made of amorphous carbon, and the first sacrificial layer acts on and provides a flat top surface for etching the layer to be processed 203.
In this embodiment, the first anti-reflection layer has a function of reducing light reflection during photolithography exposure, thereby improving the photolithography effect.
In this embodiment, the first mark opening 207 includes: a first opening 207a extending along a first direction X, and a second opening 207b extending along a second direction Y, the first direction X being perpendicular to the second direction Y, the first opening 207a exposing a sidewall of the second opening 207 b.
In this embodiment, in the process of forming the first mark opening 207, the method further includes: first device openings (not shown) are formed in the layer to be processed 203 over the device region II.
Referring to fig. 9 and 10, fig. 10 is a schematic cross-sectional view taken along line C-C in fig. 9, the first mark opening 207 is used as an alignment mark to perform a second patterning process on the layer to be processed 203, a second mark opening 208 is formed in the layer to be processed 203 on the mark region I, and the first mark opening 207 and the second mark opening 208 are separated from each other.
By forming the first mark opening 207 and the second mark opening 208 in the mark region and separating the first mark opening 207 and the second mark opening 208 from each other, the first mark opening 207 and the second mark opening 208 do not overlap, etching penetration caused by repeated etching at the same position in the mark region I is avoided, further etching environmental pollution and residue caused by etching penetration are avoided, the residue in the mark region enters the device region to influence the device structure, and the performance of the finally formed semiconductor structure is effectively improved.
In this embodiment, the second graphic processing method includes: forming a second patterned layer (not shown) on the layer to be processed 203, the second patterned layer exposing a portion of the top surface of the layer to be processed 203; etching the layer to be processed 203 by using the second patterning layer as a mask, and forming the second mark opening 208 in the layer to be processed 203; after forming the second mark opening 208, the second patterning layer is removed.
In this embodiment, the material of the second patterned layer is photoresist.
In this embodiment, before forming the second patterned layer, the method further includes: a second sacrificial layer is formed on the layer to be processed 203, the second sacrificial layer fills the first mark opening 207, a second anti-reflection layer (not shown) is located on the second sacrificial layer, and the second patterning layer is located on the second anti-reflection layer.
In this embodiment, the second mark opening 208 includes: a third opening 208a and a fourth opening 208b extending along the first direction X, the fourth opening 208b exposing a sidewall of the third opening 208a, the first opening 207a and the third opening 208a being arranged in parallel along the second direction Y, the third opening 208a having a first width dimension d1 along the second direction Y, the fourth opening 208b having a second width dimension d2 along the second direction Y, the second width dimension d2 being greater than the first width dimension d 1; a fifth opening 208c and a sixth opening 208d extending along the second direction Y, the sixth opening 208d exposing a sidewall of the fifth opening 208c, the second opening 207b and the fifth opening 208c being arranged in parallel along the first direction X, the fifth opening 208c having a third width dimension d3 along the first direction X, the sixth opening 208d having a fourth width dimension d4 along the first direction X, the fourth width dimension d4 being greater than the third width dimension d 3.
In the present embodiment, the first width dimension d1 ranges from 0.3 μm to 0.5 μm; the third width dimension d3 ranges from 0.3 μm to 0.5 μm. The first width dimension and the third width dimension in the range of 0.3 μm to 0.5 μm facilitate center recognition of the image.
In the present embodiment, the first mark opening 207 and the second mark opening 208 have a first spacing dimension s1 therebetween. The first spacing dimension s1 is a spacing dimension between the first opening 207a and the third opening 208a, or a spacing dimension between the second opening 207b and the fifth opening 208 c.
In the present embodiment, the first pitch dimension s1 ranges from 0.2 μm to 0.4 μm.
When the first spacing dimension s1 is smaller than 0.2 μm, the formed processing window is smaller, which brings certain difficulty to the process; when the first pitch dimension s1 is greater than 0.4 μm, the center recognition of the image may be affected.
In this embodiment, in the process of forming the second mark opening 208, the method further includes: second device openings (not shown) are formed in the layer to be processed 203 over the device region II.
In this embodiment, the first mark opening 207 and the second mark opening 208 are located at corner positions of the device region II.
Referring to fig. 11 and 12, fig. 12 is a schematic cross-sectional view taken along a line D-D in fig. 11, after the first mark opening 207 and the second mark opening 208 are formed, a third patterning process is performed on the layer to be processed 203 by using the second mark opening 208 as an alignment mark, and a third mark opening 209 is formed in the layer to be processed 203.
In this embodiment, the third mark opening 209 includes: a seventh opening 209a extending along the first direction X, an eighth opening 209b extending along the second direction Y, the eighth opening 209b exposing a sidewall of the seventh opening 209a, a ninth opening 209c extending along the first direction X, the ninth opening 209c exposing a sidewall of the eighth opening 209b, and a tenth opening 209d extending along the second direction Y, the tenth opening 209d exposing a sidewall of the ninth opening 209 c.
In this embodiment, the third mark opening 209 and the second mark opening 208 have a second spacing dimension s2 therebetween.
In the present embodiment, the second pitch dimension s2 ranges from 0.2 μm to 0.4 μm.
In this embodiment, in the process of forming the third mark opening 209, the method further includes: third device openings (not shown) are formed in the layer to be processed 203 over the device region II.
Referring to fig. 13 and 14, fig. 14 is a schematic cross-sectional view taken along line E-E in fig. 13, the third mark opening 209 is used as an alignment mark to perform a fourth patterning process on the layer to be processed, a fourth mark opening 210 is formed in the layer to be processed 203, and the first mark opening 207, the second mark opening 208, the third mark opening 209 and the fourth mark opening 210 are separated from each other.
In this embodiment, the fourth mark opening 210 includes: an eleventh opening 210a extending along the first direction X, a twelfth opening 210b extending along the second direction Y, the twelfth opening 210b exposing a sidewall of the eleventh opening 210a, a thirteenth opening 210c extending along the first direction X, the thirteenth opening 210c exposing a sidewall of the twelfth opening 210b, and a fourteenth opening 210d extending along the second direction Y, the fourteenth opening 210d exposing a sidewall of the thirteenth opening 210 c.
In the present embodiment, the fourth mark opening 210 and the third mark opening 209 have a third spacing dimension s3 therebetween.
In the present embodiment, the third pitch dimension s3 ranges from 0.2 μm to 0.4 μm.
In the present embodiment, 4 photolithography processes are used as an example, so that the number of the formed mark openings also includes 4. In other embodiments, the photolithography process may be performed less than 4 times or more than 4 times, and thus, the number of the correspondingly formed mark openings may be less than 4 or more than 4.
In this embodiment, the third mark opening 209 and the fourth mark opening 210 are also located at the corner positions of the device region II, the pattern formed by the whole of the first mark opening 207, the second mark opening 208, the third mark opening 209 and the fourth mark opening 210 is "L" shaped, and when 4 wafers are spliced together, the pattern formed by the mark openings at the corner positions of the 4 wafers will be a "+" shaped structure.
In this embodiment, in the process of forming the fourth mark opening 210, the method further includes: fourth device openings (not shown) are formed in the layer to be processed 203 over the device region II.
Referring to fig. 15, the view directions of fig. 15 and fig. 14 are the same, and after the first device opening, the second device opening, the third device opening and the fourth device opening are formed, first side walls (not shown) are formed on the side walls of the first device opening, the second device opening, the third device opening and the fourth device opening.
In this embodiment, in the process of forming the first sidewall, the method further includes: a second sidewall 211 is formed on sidewalls of the first mark opening 207, the second mark opening 208, the third mark opening 209 and the fourth mark opening 210.
In this embodiment, the method for forming the first and second sidewalls 211 includes: forming initial side walls (not shown) in the first device opening, the second device opening, the third device opening, the fourth device opening, the first mark opening 207, the second mark opening 208, the third mark opening 209 and the fourth mark opening 210 and on the top surface of the layer to be processed 203; and etching back the initial side walls until the top surfaces of the layer to be processed 203 and the third stop layer 206 are exposed, so as to form the first side walls and the second side walls 211.
In this embodiment, the first sidewall is formed on the sidewalls of the first device opening, the second device opening, the third device opening, and the fourth device opening, and functions as: spatial frequency doubling of the lithographic pattern is achieved by Self-aligned Double imaging (SADP), i.e. after one lithography step, using successively non-lithographic process steps (thin film deposition, etching, etc.).
Referring to fig. 16, after the first and second sidewalls 211 are formed, the layer to be processed 203 is removed; and etching the substrate by using the first side wall and the second side wall 211 as masks, and forming a patterned opening 212 in the substrate.
In this embodiment, the process of removing the layer to be processed 203 adopts a wet etching process; in other embodiments, the process of removing the layer to be processed may also adopt a dry etching process.
In this embodiment, the process of etching the substrate with the first and second sidewalls 211 as masks adopts a wet etching process; in other embodiments, the process of etching the substrate with the first and second sidewalls as masks may also adopt a dry etching process.
Accordingly, an embodiment of the present invention further provides an alignment mark, please continue to refer to fig. 13 and 14, including: the substrate comprises a mark area I, and the mark area I is provided with a layer to be processed 203; a first mark opening 207 in the layer 203 to be processed on the mark region I; a second mark opening 208 located in the layer 203 to be processed on the mark region I, wherein the first mark opening 207 and the second mark opening 208 are separated from each other.
Through the first mark opening 207 and the second mark opening 208 which are positioned in the mark area, and the first mark opening 207 and the second mark opening 208 are mutually separated, the first mark opening 207 and the second mark opening 208 can not be overlapped, etching penetration caused by repeated etching at the same position in the mark area I is avoided, further, etching environment pollution and residue generation caused by etching penetration are avoided, the influence on a device structure caused by the fact that the residue in the mark area enters the device area is avoided, and the performance of the finally formed semiconductor structure is effectively improved.
In this embodiment, the substrate further includes: a device region II; the mark region I surrounds the device region II, the layer to be processed 203 is also located on the device region II, and the first mark opening 207 and the second mark opening 208 are located at corner positions of the device region II.
In this embodiment, the device further includes a plurality of first device openings and a plurality of second device openings located in the layer to be processed 103 on the device region II.
In this embodiment, the first mark opening 207 includes: a first opening 207a extending along a first direction X, and a second opening 207b extending along a second direction Y, the first direction X being perpendicular to the second direction Y, the first opening 207a exposing a sidewall of the second opening 207 b.
In this embodiment, the second mark opening 208 includes: a third opening 208a and a fourth opening 208b extending along the first direction X, the fourth opening 208b exposing a sidewall of the third opening 208a, the first opening 207a and the third opening 208a being arranged in parallel along the second direction Y, the third opening 208a having a first width dimension d1 along the second direction Y, the fourth opening 208b having a second width dimension d2 along the second direction Y, the second width dimension d2 being greater than the first width dimension d 1; a fifth opening 208c and a sixth opening 208d extending along the second direction Y, the sixth opening 208d exposing a sidewall of the fifth opening 208c, the second opening 207b and the fifth opening 208c being arranged in parallel along the first direction X, the fifth opening 208c having a third width dimension d3 along the first direction X, the sixth opening 208d having a fourth width dimension d4 along the first direction X, the fourth width dimension d4 being greater than the third width dimension d 3.
In the present embodiment, the first width dimension d1 ranges from 0.3 μm to 0.5 μm; the third width dimension d3 ranges from 0.3 μm to 0.5 μm.
In the present embodiment, the first mark opening 207 and the second mark opening 208 have a first spacing dimension s1 therebetween.
In the present embodiment, the first spacing dimension s1 is a spacing dimension between the first opening 207a and the third opening 208a, or a spacing dimension between the second opening 207b and the fifth opening 208 c.
In the present embodiment, the first pitch dimension s1 ranges from 0.2 μm to 0.4 μm.
In this embodiment, the method further includes: a third mark opening 209 and a fourth mark opening 210 in the layer 203 to be processed on the mark region I, wherein the first mark opening 207, the second mark opening 208, the third mark opening 209 and the fourth mark opening 210 are separated from each other.
In the present embodiment, a second spacing dimension s2 is provided between the third mark opening 209 and the second mark opening 208, and a third spacing dimension s3 is provided between the fourth mark opening 210 and the third mark opening 209.
In this embodiment, the third mark opening 209 includes: a seventh opening 209a extending along the first direction X, an eighth opening 209b extending along the second direction Y, the eighth opening 209b exposing a sidewall of the seventh opening 209a, a ninth opening 209c extending along the first direction X, the ninth opening 209c exposing a sidewall of the eighth opening 209b, and a tenth opening 209d extending along the second direction Y, the tenth opening 209d exposing a sidewall of the ninth opening 209 c.
In this embodiment, the fourth mark opening 210 includes: an eleventh opening 210a extending along the first direction X, a twelfth opening 210b extending along the second direction Y, the twelfth opening 210b exposing a sidewall of the eleventh opening 210a, a thirteenth opening 210c extending along the first direction X, the thirteenth opening 210c exposing a sidewall of the twelfth opening 210b, and a fourteenth opening 210d extending along the second direction Y, the fourteenth opening 210d exposing a sidewall of the thirteenth opening 210 c.
In this embodiment, a plurality of third device openings and a plurality of fourth device openings are further included in the layer to be processed 203 on the device region II.
In this embodiment, the substrate further includes: the etching mask comprises a substrate 200 and a layer to be etched positioned on the substrate 200, wherein the layer to be processed 203 is positioned on the layer to be etched.
In this embodiment, the layer to be etched includes: the device comprises a device layer 201 and a hard mask layer 202 located on the device layer 201, wherein the layer to be processed 203 is located on the hard mask layer 202.
In this embodiment, the method further includes: a first stop layer 204, the first stop layer 204 being located between the substrate 200 and the device layer 201; a second stop layer 205, the second stop layer 205 being located between the device layer 201 and the hard mask layer 202; a third stop layer 206, the third stop layer 206 being located between the hard mask layer 202 and the layer to be processed 203.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (43)

1. An alignment mark, comprising:
the substrate comprises a mark area, and the mark area is provided with a layer to be processed;
a first mark opening in the layer to be processed on the mark region;
and the first mark opening and the second mark opening are separated from each other.
2. The alignment mark of claim 1, wherein the substrate further comprises: a device region; the mark region surrounds the device region, the layer to be processed is also located on the device region, and the first mark opening and the second mark opening are located at corner positions of the device region.
3. The alignment mark of claim 2, further comprising a plurality of first device openings and a plurality of second device openings located in a layer to be processed over the device region.
4. The alignment mark of claim 1, wherein the first mark opening comprises: the liquid crystal display panel comprises a first opening extending along a first direction and a second opening extending along a second direction, wherein the first direction is vertical to the second direction, and the side wall of the second opening is exposed out of the first opening.
5. The alignment mark of claim 4, wherein the second mark opening comprises: a third opening and a fourth opening extending along the first direction, the fourth opening exposing a sidewall of the third opening, the first opening and the third opening being arranged in parallel along the second direction, the third opening having a first width dimension along the second direction, the fourth opening having a second width dimension along the second direction, the second width dimension being greater than the first width dimension; the second opening and the fifth opening are arranged in parallel along the first direction, the fifth opening has a third width dimension along the first direction, the sixth opening has a fourth width dimension along the first direction, and the fourth width dimension is greater than the third width dimension.
6. The alignment mark of claim 5, wherein the first width dimension is in a range of 0.3 μm to 0.5 μm; the third width dimension is in a range of 0.3 μm to 0.5 μm.
7. The alignment mark of claim 5, wherein the first mark opening and the second mark opening have a first pitch dimension therebetween.
8. The alignment mark of claim 7, wherein the first pitch dimension is a pitch dimension between the first opening and the third opening or a pitch dimension between the second opening and the fifth opening.
9. The alignment mark of claim 7, wherein the first pitch dimension is in a range from 0.2 μm to 0.4 μm.
10. The alignment mark of claim 4, further comprising: and the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are separated from each other.
11. The alignment mark of claim 10 wherein the third mark opening and the second mark opening have a second pitch dimension therebetween and the fourth mark opening and the third mark opening have a third pitch dimension therebetween.
12. The alignment mark of claim 10, wherein the third mark opening comprises: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
13. The alignment mark of claim 10, wherein the fourth mark opening comprises: the liquid crystal display device comprises an eleventh opening extending along the first direction, a twelfth opening extending along the second direction, wherein the twelfth opening exposes a side wall of the eleventh opening, a thirteenth opening extending along the first direction, the thirteenth opening exposes a side wall of the twelfth opening, and a fourteenth opening extending along the second direction, and the fourteenth opening exposes a side wall of the thirteenth opening.
14. The alignment mark of claim 2, further comprising a plurality of third device openings and a plurality of fourth device openings located in a layer to be processed over the device region.
15. The alignment mark of claim 1, wherein the substrate further comprises: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the layer to be etched.
16. The alignment mark of claim 15, wherein the layer to be etched comprises: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
17. The alignment mark of claim 16, further comprising: a first stop layer between the substrate and the device layer; a second stop layer between the device layer and the hard mask layer; and the third stop layer is positioned between the hard mask layer and the layer to be processed.
18. A method for forming an alignment mark, comprising:
providing a substrate, wherein the substrate comprises a mark area, and a layer to be processed is arranged on the mark area;
forming a first mark opening in the layer to be processed on the mark area by adopting first patterning processing;
and carrying out second patterning treatment on the layer to be treated by taking the first mark opening as an alignment mark, and forming a second mark opening in the layer to be treated on the mark area, wherein the first mark opening and the second mark opening are mutually separated.
19. The method for forming an alignment mark according to claim 18, wherein the first patterning process comprises: forming a first patterning layer on the layer to be processed, wherein the first patterning layer exposes a part of the top surface of the layer to be processed; etching the layer to be processed by taking the first patterning layer as a mask, and forming a first mark opening in the layer to be processed; removing the first patterning layer after forming the first mark opening.
20. The method of forming an alignment mark of claim 19, further comprising, prior to forming the first patterned layer: and forming a first sacrificial layer and a first anti-reflection layer positioned on the first sacrificial layer on the layer to be processed, wherein the first patterning layer is positioned on the first anti-reflection layer.
21. The method for forming an alignment mark according to claim 18, wherein the second patterning process comprises: forming a second patterned layer on the layer to be processed, wherein the second patterned layer exposes a part of the top surface of the layer to be processed; etching the layer to be processed by taking the second patterning layer as a mask, and forming a second mark opening in the layer to be processed; removing the second patterned layer after forming the second mark opening.
22. The method of forming an alignment mark of claim 21, further comprising, prior to forming the second patterned layer: and forming a second sacrificial layer on the layer to be processed, wherein the second sacrificial layer fills the first mark opening and a second anti-reflection layer positioned on the second sacrificial layer, and the second patterning layer is positioned on the second anti-reflection layer.
23. The method of forming an alignment mark of claim 18, wherein the substrate further comprises: a device region; the mark region surrounds the device region, the layer to be processed is also located on the device region, and the first mark opening and the second mark opening are located at corner positions of the device region.
24. The method of forming an alignment mark according to claim 23, further comprising, during the forming of the first mark opening: a plurality of first device openings are formed in the layer to be processed on the device region.
25. The method for forming an alignment mark according to claim 24, further comprising, during the forming of the second mark opening: and forming a plurality of second device openings in the layer to be processed on the device area.
26. The method of forming an alignment mark of claim 25, wherein the first mark opening comprises: the liquid crystal display panel comprises a first opening extending along a first direction and a second opening extending along a second direction, wherein the first direction is vertical to the second direction, and the side wall of the second opening is exposed out of the first opening.
27. The method of forming an alignment mark of claim 26, wherein the second mark opening comprises: a third opening and a fourth opening extending along the first direction, the fourth opening exposing a sidewall of the third opening, the first opening and the third opening being arranged in parallel along the second direction, the third opening having a first width dimension along the second direction, the fourth opening having a second width dimension along the second direction, the second width dimension being greater than the first width dimension; the second opening and the fifth opening are arranged in parallel along the first direction, the fifth opening has a third width dimension along the first direction, the sixth opening has a fourth width dimension along the first direction, and the fourth width dimension is greater than the third width dimension.
28. The method of forming an alignment mark of claim 27, wherein the first width dimension ranges from 0.3 μm to 0.5 μm; the third width dimension is in a range of 0.3 μm to 0.5 μm.
29. The method of forming an alignment mark of claim 27, wherein the first mark opening and the second mark opening have a first pitch dimension therebetween.
30. The method of claim 29, wherein the first pitch dimension is a pitch dimension between the first opening and the third opening, or a pitch dimension between the second opening and the fifth opening.
31. The method of forming an alignment mark of claim 29, wherein the first pitch dimension ranges from 0.2 μm to 0.4 μm.
32. The method of forming an alignment mark of claim 26, further comprising, after forming the first mark opening and the second mark opening: performing third patterning processing on the layer to be processed by taking the second mark opening as an alignment mark, and forming a third mark opening in the layer to be processed; and performing fourth patterning processing on the layer to be processed by taking the third mark opening as an alignment mark, and forming a fourth mark opening in the layer to be processed, wherein the first mark opening, the second mark opening, the third mark opening and the fourth mark opening are separated from each other.
33. The method of forming an alignment mark of claim 32, wherein the third mark opening and the second mark opening have a second pitch dimension therebetween, and the fourth mark opening and the third mark opening have a third pitch dimension therebetween.
34. The method of forming an alignment mark of claim 32, wherein the third mark opening comprises: a seventh opening extending in the first direction, an eighth opening extending in the second direction, the eighth opening exposing a sidewall of the seventh opening, a ninth opening extending in the first direction, the ninth opening exposing a sidewall of the eighth opening, and a tenth opening extending in the second direction, the tenth opening exposing a sidewall of the ninth opening.
35. The method of forming an alignment mark of claim 32, wherein the fourth mark opening comprises: the liquid crystal display device comprises an eleventh opening extending along the first direction, a twelfth opening extending along the second direction, wherein the twelfth opening exposes a side wall of the eleventh opening, a thirteenth opening extending along the first direction, the thirteenth opening exposes a side wall of the twelfth opening, and a fourteenth opening extending along the second direction, and the fourteenth opening exposes a side wall of the thirteenth opening.
36. The method of forming an alignment mark according to claim 32, further comprising, in forming the third mark opening: and forming a plurality of third device openings in the layer to be processed on the device area.
37. The method for forming an alignment mark according to claim 36, further comprising, in forming the fourth mark opening: and forming a plurality of fourth device openings in the layer to be processed on the device area.
38. The method of forming an alignment mark of claim 18, wherein the substrate further comprises: the device comprises a substrate and a layer to be etched, wherein the layer to be processed is positioned on the layer to be etched.
39. The method of forming an alignment mark as claimed in claim 38, wherein the layer to be etched comprises: the device comprises a device layer and a hard mask layer positioned on the device layer, wherein the layer to be processed is positioned on the hard mask layer.
40. The method of forming an alignment mark of claim 39, further comprising: a first stop layer between the substrate and the device layer; a second stop layer between the device layer and the hard mask layer; and the third stop layer is positioned between the hard mask layer and the layer to be processed.
41. The method of forming an alignment mark of claim 37, further comprising, after forming the first, second, third, and fourth device openings: and forming first side walls on the side walls of the first device opening, the second device opening, the third device opening and the fourth device opening.
42. The method for forming an alignment mark according to claim 41, wherein in the process of forming the first sidewall spacers, the method further comprises: and forming second side walls on the side walls of the first mark opening, the second mark opening, the third mark opening and the fourth mark opening.
43. The method for forming an alignment mark of claim 42, further comprising, after forming the first sidewall and the second sidewall: removing the layer to be treated; and etching the substrate by using the first side wall and the second side wall as masks, and forming a patterned opening in the substrate.
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