JPH1131645A - Method for forming alignment mark - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely recognize an alignment mark, even when a wiring layer is formed on the alignment mark by making a recessed part on the inner peripheral surface of an opening formed in the surface of a semiconductor substrate. SOLUTION: An organic SOG film, for example as a lower layer insulation film 3 and a SiO2 film, for example, as an upper layer insulation film 4 are formed (a) on a SiO2 insulation film 23 formed in advance on a substrate 1. Next, (b) an alignment mark is made on the insulation films 2, 3, 4 by etching. Since the lower layer insulation film 3 is etched earlier than the upper layer insulation film 4, the pattern edge 4a of the upper layer insulation film 4 makes eaves for the lower layer insulation film 3 to form a recessed part U. For the alignment mark formed in this manner, a barrier metal layer 5 is formed (c) on the upper layer insulation film 4 and on the inner surface except for the recessed part U. When a wiring layer 6 is formed on the barrier metal layer 5, the flow of wiring material is stopped at the recessed part U (d), and hence the pattern edge 4a can be better recognized, which improves the accuracy and the reproducibility of overlaying.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an alignment mark, and more particularly, to a method for forming an alignment mark provided on a surface of a semiconductor substrate so as to overlap various masks.

[0002]

2. Description of the Related Art In a process of manufacturing a large-scale integrated circuit, for example, a complicated circuit pattern is formed by overlapping a large number of masks. Therefore, the smaller the processing accuracy becomes, the more the relative positional deviation from the mask to be overlaid affects the product yield. In order to perform this relative alignment, an alignment mark is provided on the substrate, which is a reference when the masks are superimposed. An operator can read the alignment mark by an image pickup means such as a CCD and perform alignment with the mask.

As the shape of the alignment mark, for example, a so-called box-in-box as shown in FIG. 2 is used. FIG. 4 is a diagram for explaining a method of forming the alignment mark. When the alignment mark is formed, first, an insulating film 42 such as SiO ₂ is formed on the substrate 41 by a CVD method or the like.
(State of (a)).

Next, a positioning mark M shown in FIG. 2 is formed at a predetermined position of the insulating film 42 by etching. That is, for example, the width 2 corresponding to the alignment mark M
An opening 43 having a thickness of about 0 μm and a depth of about 0.5 to 1.0 μm is formed in the insulating film 42 (the state shown in FIG. 4B).

[0005]

On the alignment mark M formed as described above, a barrier metal layer 44 of TiN or the like is further formed by sputtering or the like (the state of FIG. 4C). Further, the wiring material is melted on the barrier metal layer 44 by high-temperature flow sputtering or Al reflow in the wiring step, and the barrier metal layer 44 is melted.
The wiring layer 45 is formed thereon (the state of FIG. 4D).

The barrier metal layer 44 is made of Al and S
In addition to preventing the reaction with i from deteriorating the characteristics as the wiring, it functions to promote the spread of Al during Al flow. However, in the conventional example, the barrier metal layer 44 that promotes the spread of Al during the flow has the opening 4.
3D is also formed on the side surface 43a of FIG.
As shown in (1), the wiring material flows into the mark M when the wiring layer 45 is formed.

When the wiring material flows into the mark M, irregularities appear on the pattern lines as shown in FIG. 5, for example. When such irregularities appear, the visibility of the alignment mark via a CCD or the like is significantly reduced, so that it is difficult to accurately determine the mark position, and as a result, the mark overlay accuracy is reduced. Of course, after forming the wiring layer 45, it is possible to further perform etching or the like on the alignment mark M to make the alignment mark M clear, but this requires extra cost and labor. Therefore, it cannot be said to be a preferable method.

In order to solve the problems in the prior art, the present invention improves a method of forming an alignment mark, and ensures reliable visibility of the mark even when a wiring layer is formed on the alignment mark. It is an object of the present invention to provide an alignment mark forming method that can be performed.

[0009]

According to one aspect of the present invention, there is provided an alignment mark forming method for forming a concave portion on an inner peripheral surface of an opening formed in a surface of a semiconductor substrate. I have. According to a second aspect of the present invention, there is provided an alignment mark forming method serving as a reference when overlapping masks, wherein an opening is formed in a surface of a semiconductor substrate and a portion of a side surface of the opening except at least an upper portion is provided. It is configured as an alignment mark forming method for forming a concave portion.

According to a third aspect of the present invention, there is provided an alignment mark forming method serving as a reference when overlapping masks, wherein the alignment mark is formed on a film including a lower film and an upper film laminated on the surface of the semiconductor substrate. Simultaneously with or after the patterning, an alignment mark forming method for forming a concave portion in which the edge of the lower layer film is recessed from the edge of the pattern in the formed upper layer film.

According to a fourth aspect of the present invention, there is provided an alignment mark forming method serving as a reference when overlaying a mask, wherein a laminating step of laminating a lower layer film and an upper layer film on a surface of a semiconductor substrate; Simultaneously with or after the patterning of the alignment mark for the film including the upper film,
A recess forming step of forming a recess in which the edge of the lower layer film is recessed from the edge of the pattern in the formed upper layer film.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, in particular, the lower film and the upper film laminated in the laminating step are insulating films having different etching rates, and This is a method of forming an alignment mark in which the formation of a concave portion in a process is performed by etching. According to a sixth aspect of the present invention, there is provided an alignment mark forming method serving as a reference when overlaying masks, wherein an insulating mark formed on the surface of the semiconductor substrate is formed on the insulating film.
A step of laminating a lower layer film and an upper layer film having different etching rates, and etching of the alignment mark on the film including the insulating film, the lower layer film and the upper layer film, and a pattern edge of the insulating film and the upper film from the edge of the pattern. And forming a concave portion in which the edge of the lower layer film is recessed.

Further, the invention according to claim 7 is the invention according to any one of claims 3 to 7, wherein at least one of the lower film and the upper film is itself formed as a multilayer. This is an alignment mark forming method. According to the invention described in any one of claims 1 to 7,
For example, even when the wiring material tries to flow into the opening or the alignment mark when forming the wiring such as Al or Al-Si, the flow is stopped by the concave portion provided on the inner peripheral surface of the opening or the alignment mark. Therefore, the wiring material does not flow into the opening or the mark from the edge as in the related art, and the pattern line at the edge is not unclear.

By using the lower layer film and the upper layer film having different etching rates, the concave portion can be easily formed. The openings and the alignment marks are formed on the surface of the semiconductor substrate itself, that is, an insulating film, a conductive film, a semiconductor film, or the like, on which the mask is to be superimposed.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings to provide an understanding of the present invention.
The following embodiment is a specific example of the present invention and does not limit the technical scope of the present invention. Here, FIG. 1 is a view for explaining the steps of the alignment mark forming method according to one embodiment of the present invention.

As shown in FIG. 1, a method of forming an alignment mark according to an embodiment of the present invention is a method of forming a mask in a lithography process before forming a conductive layer on a surface of a semiconductor substrate by a reflow process. 1. A method of forming an alignment mark, which is a reference of (1), comprising: a laminating step of laminating a lower insulating film 3 and an upper insulating film 4 on an insulating film 2 formed on a semiconductor substrate 1 (the state of FIG. 1A); Simultaneously with or after the patterning of the alignment mark M with respect to the lower insulating film 3 and the upper insulating film 4, the concave portion U in which the edge 3a of the lower insulating film 3 is recessed from the pattern edge 4a of the formed upper insulating film 4 is formed. This is particularly different from the prior art in that it includes a recess forming step (the state shown in FIG. 1B).

Hereinafter, the details of the above-described alignment mark forming method will be described. First, a lower insulating film 3 and an upper insulating film 4 having different etching rates are formed.
(State of (a)). More specifically, the CV is previously placed on the substrate 1.
The SiO ₂ insulating film 2 having a thickness of about 4000 ° is formed by the method D or the like. An organic SOG film having a thickness of about 2000 ° is formed on the insulating film 2 as a lower insulating film 3 by spin coating and heat treatment. Organic S
The OG film is made of S, which is a material of the insulating film 2 and the upper insulating film 4.
It is known that it is softer than iO _{2 and} has a higher etching rate than SiO ₂ . Further, an SiO ₂ film having a thickness of about 4000 ° is formed as an upper insulating film 4 on the lower insulating film 3.

Next, the alignment mark M is etched with respect to the insulating film 2, the lower insulating film 3, and the upper insulating film 4 (the state shown in FIG. 1B). Note that a fluorocarbon-based gas is used for etching the insulating films 2, 3, and 4 described above. By this etching, organic SOG
Since the lower insulating film 3, which is a film, is etched faster than the upper insulating film 4, the edge 3a of the lower insulating film 3 is
The pattern edge 4a of the upper insulating film 4 is receded by about 500 ° from the pattern edge 4a of the upper insulating film 4, which is an O ₂ film, so that the pattern edge 4a of the upper insulating film 4 becomes eaves-like with respect to the lower insulating film 3, and the alignment mark M
, A concave portion U is formed.

In the alignment mark M formed as described above, a barrier metal layer 5 such as TiN is formed on the upper insulating film 4 by sputtering or the like in a wiring forming step, and the mark M excluding the concave portion U is formed. (FIG. 1 (c)). Then, the barrier metal layer 5 is formed by Al reflow or the like in a wiring forming process.
The wiring layer 6 is formed thereon (the state shown in FIG. 1D). At this time, since the barrier metal layer 5 for promoting the spread of the wiring material does not exist in the concave portion U, the flow of the wiring material is reduced.
It stops at the concave portion U. Therefore, as shown in FIG. 2, no irregularities that obscure the pattern of the alignment mark M are not formed, and the visibility of the pattern edge 4a is improved. As a result, overlay accuracy and repeatability of measurement are improved.

As described above, in the alignment mark forming method according to the present embodiment, since the concave portion U is formed under the pattern edge 4a, the flow of the wiring material is stopped in the concave portion U, and the alignment with good visibility is achieved. The mark can be easily formed.

[0021]

In the above embodiment, the lower insulating film 3 is made of S
Although the SOG film is used as the iO ₂ film and the upper insulating film 4, a combination of other insulating films may of course be used. For example, when wet etching is used, the lower insulating film 3 and the upper insulating film 4 are coated with TEOS (tetraethyl orthosilicate),
The combination of SiN, TEOS, BPSG (boro-phospho
It is possible to use a combination of silicate glass). In addition, BPS is performed using Cl-based plasma etching.
It is also possible to use a combination of G and TEOS. Such an alignment mark forming method is also an example of the alignment mark forming method in the present invention.

In the above embodiment, TiN is used for the barrier metal layer 5. However, other high melting point metals such as Ti and Mo or a laminated film of these materials such as TiN / Ti are used. Is also good. Further, the material of the wiring layer 6 is not limited to Al.
Alternatively, an Al-Si-Cu alloy or the like may be used. Such an alignment mark forming method is also an example of the alignment mark forming method in the present invention.

In the above embodiment, the lower insulating film 3 is provided on the insulating film 2. However, as shown in FIG. 3, the lower insulating film 3 and the upper insulating film 4 are directly formed on the semiconductor substrate 1. Is also good. Of course, these upper and lower layers 3 and 4 may be provided on a semiconductor layer, a conductive layer, or an insulating layer formed as a single layer or a multilayer. Further, although the lower insulating film 3 and the upper insulating film 4 in the above embodiment are provided in a single layer, each layer may be of a multilayer. Such an alignment mark forming method is also an example of the alignment mark forming method in the present invention.

It should be noted that the alignment mark M
The size, shape, and the like of are not limited to those in the above-described embodiment. Further, the present invention provides a method of forming an opening having a new concave portion on a semiconductor substrate on which a layer portion such as the insulating layer or the semiconductor layer is already formed on the surface,
For those with openings already formed in the above layer,
This includes the case where a new concave portion is formed.

[0025]

As described above, according to the alignment mark forming method of the present invention, even when a wiring material such as Al or Al-Si is formed in the alignment mark pattern, the wiring material tries to flow into the mark. Since this inflow is stopped at the concave portion formed at the pattern edge, the wiring material does not flow into the opening from the pattern edge to make the pattern itself unclear as in the prior art, and the visibility of the mark is secured. As a result, the overlay accuracy of a mask or the like can be improved.

Further, in the above-described alignment mark forming method, a concave portion can be easily formed by using insulating films having different etching rates in the lower film and the upper film laminated in the laminating step.

[Brief description of the drawings]

FIG. 1 is a view for explaining steps of an alignment mark forming method according to an embodiment of the present invention.

FIG. 2 is a plan view showing a shape of an alignment mark formed by the alignment mark forming method.

FIG. 3 is a diagram for explaining one embodiment of the present invention.

FIG. 4 is a view for explaining steps of a conventional alignment mark forming method.

FIG. 5 is a plan view showing the shape of an alignment mark formed by a conventional alignment mark forming method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 3 ... Lower insulating film 3a ... Edge of lower insulating film 4 ... Upper insulating film 4a ... Pattern edge of upper insulating film 5 ... Barrier metal layer M ... Alignment mark U ... Depression

Claims (7)

[Claims] 1. A method for forming an alignment mark, wherein a concave portion is formed on an inner peripheral surface of an opening formed on a surface of a semiconductor substrate. 2. A method according to claim 1, wherein an opening is formed in a surface of the semiconductor substrate and a recess is formed in a side surface of the opening except at least an upper portion. Alignment mark forming method. 3. A method for forming an alignment mark, which is a reference when overlaying a mask, is performed simultaneously with or after patterning of an alignment mark on a film including a lower film and an upper film laminated on a surface of a semiconductor substrate. In addition, a method of forming an alignment mark for forming a concave portion in which the edge of the lower film is recessed from the edge of the pattern in the upper film. 4. A method for forming an alignment mark serving as a reference when overlaying a mask, a laminating step of laminating a lower film and an upper film on a surface of a semiconductor substrate, and positioning the film including the lower film and the upper film. Forming a recess in which the edge of the lower layer film is recessed from the edge of the pattern in the formed upper layer film simultaneously with or after the patterning of the mark. 5. The position according to claim 4, wherein the lower film and the upper film laminated in the laminating step are insulating films having different etching rates, and the formation of the recess in the recess forming step is performed by etching. Alignment mark forming method. 6. A method of forming an alignment mark serving as a reference when overlapping masks, a step of laminating a lower film and an upper film having different etching rates on an insulating film formed on a surface of a semiconductor substrate; Insulating film, lower layer film,
Forming an alignment mark on the film including the upper layer film and forming a recess in which the edge of the lower layer film is recessed from the edge of the pattern in the insulating film and the upper layer film. Method. 7. The alignment mark forming method according to claim 3, wherein at least one of the lower layer film and the upper layer film is formed as a multilayer itself.