KR101594335B1 - 반도체 장치 및 그 제조 방법 - Google Patents
반도체 장치 및 그 제조 방법 Download PDFInfo
- Publication number
- KR101594335B1 KR101594335B1 KR1020080118723A KR20080118723A KR101594335B1 KR 101594335 B1 KR101594335 B1 KR 101594335B1 KR 1020080118723 A KR1020080118723 A KR 1020080118723A KR 20080118723 A KR20080118723 A KR 20080118723A KR 101594335 B1 KR101594335 B1 KR 101594335B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- insulating layer
- single crystal
- crystal semiconductor
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/667—Vertical DMOS [VDMOS] FETs having substrates comprising insulating layers, e.g. SOI-VDMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
Landscapes
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Recrystallisation Techniques (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2007-312762 | 2007-12-03 | ||
| JP2007312762 | 2007-12-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20090057903A KR20090057903A (ko) | 2009-06-08 |
| KR101594335B1 true KR101594335B1 (ko) | 2016-02-16 |
Family
ID=40491094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020080118723A Expired - Fee Related KR101594335B1 (ko) | 2007-12-03 | 2008-11-27 | 반도체 장치 및 그 제조 방법 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8304832B2 (https=) |
| EP (1) | EP2068366A3 (https=) |
| JP (1) | JP5433220B2 (https=) |
| KR (1) | KR101594335B1 (https=) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009158853A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 半導体装置 |
| US8513090B2 (en) * | 2009-07-16 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate, and semiconductor device |
| TWI512997B (zh) | 2009-09-24 | 2015-12-11 | 半導體能源研究所股份有限公司 | 半導體裝置,電源電路,和半導體裝置的製造方法 |
| KR101396096B1 (ko) * | 2009-10-09 | 2014-05-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제조 방법 |
| KR101876473B1 (ko) | 2009-11-06 | 2018-07-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
| CN102648525B (zh) | 2009-12-04 | 2016-05-04 | 株式会社半导体能源研究所 | 显示装置 |
| EP2513966B1 (en) | 2009-12-18 | 2020-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| TWI787452B (zh) | 2011-01-26 | 2022-12-21 | 日商半導體能源研究所股份有限公司 | 半導體裝置及其製造方法 |
| US9082663B2 (en) * | 2011-09-16 | 2015-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| WO2013039126A1 (en) * | 2011-09-16 | 2013-03-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| DE102014205130A1 (de) | 2014-03-19 | 2015-09-24 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Speicherzelle |
| SG11201913769RA (en) * | 2017-07-14 | 2020-01-30 | Sunedison Semiconductor Ltd | Method of manufacture of a semiconductor on insulator structure |
| CN114609843A (zh) * | 2022-03-07 | 2022-06-10 | 江西晶浩光学有限公司 | 一种可变光圈、摄像模组及电子设备 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2941048B2 (ja) | 1990-11-27 | 1999-08-25 | シャープ株式会社 | Soi基板の作製方法 |
| KR100445506B1 (ko) * | 2001-09-28 | 2004-08-21 | 미쓰비시덴키 가부시키가이샤 | 반도체장치의 제조방법 |
| JP4366954B2 (ja) | 2003-02-18 | 2009-11-18 | セイコーエプソン株式会社 | 複合半導体基板の製造方法 |
| KR101341199B1 (ko) | 2006-10-30 | 2013-12-12 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 단결정 실리콘 태양전지의 제조 방법 및 단결정 실리콘 태양전지 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878455A (ja) * | 1981-10-08 | 1983-05-12 | Nec Corp | 半導体装置の製造方法 |
| US4503154A (en) * | 1982-01-05 | 1985-03-05 | Biorganic Energy, Inc. | Anaerobic digestion of organic waste for biogas production |
| JPH11163363A (ja) | 1997-11-22 | 1999-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
| JP2000012864A (ja) * | 1998-06-22 | 2000-01-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| US6255195B1 (en) * | 1999-02-22 | 2001-07-03 | Intersil Corporation | Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method |
| JP2002057309A (ja) | 2000-08-08 | 2002-02-22 | Sony Corp | Soi基板の作製方法 |
| EP1244139A2 (en) * | 2001-03-23 | 2002-09-25 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method of semiconductor film |
| KR100746220B1 (ko) * | 2004-01-12 | 2007-08-03 | 삼성전자주식회사 | 적층된 노드 콘택 구조체들과 적층된 박막 트랜지스터들을채택하는 반도체 집적회로들 및 그 제조방법들 |
| JP4349278B2 (ja) * | 2004-12-24 | 2009-10-21 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| JP4687259B2 (ja) * | 2005-06-10 | 2011-05-25 | カシオ計算機株式会社 | 液晶表示装置 |
| JP2007312762A (ja) | 2006-05-26 | 2007-12-06 | Masato Oishi | マグロ用多翼式カイト曳き縄。 |
-
2008
- 2008-11-27 KR KR1020080118723A patent/KR101594335B1/ko not_active Expired - Fee Related
- 2008-12-01 JP JP2008305824A patent/JP5433220B2/ja not_active Expired - Fee Related
- 2008-12-01 US US12/325,729 patent/US8304832B2/en not_active Expired - Fee Related
- 2008-12-02 EP EP08020904.2A patent/EP2068366A3/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2941048B2 (ja) | 1990-11-27 | 1999-08-25 | シャープ株式会社 | Soi基板の作製方法 |
| KR100445506B1 (ko) * | 2001-09-28 | 2004-08-21 | 미쓰비시덴키 가부시키가이샤 | 반도체장치의 제조방법 |
| JP4366954B2 (ja) | 2003-02-18 | 2009-11-18 | セイコーエプソン株式会社 | 複合半導体基板の製造方法 |
| KR101341199B1 (ko) | 2006-10-30 | 2013-12-12 | 신에쓰 가가꾸 고교 가부시끼가이샤 | 단결정 실리콘 태양전지의 제조 방법 및 단결정 실리콘 태양전지 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5433220B2 (ja) | 2014-03-05 |
| KR20090057903A (ko) | 2009-06-08 |
| US8304832B2 (en) | 2012-11-06 |
| EP2068366A2 (en) | 2009-06-10 |
| JP2009158942A (ja) | 2009-07-16 |
| EP2068366A3 (en) | 2015-07-01 |
| US20090140337A1 (en) | 2009-06-04 |
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