KR101505214B1 - Electrical connection body and method for fabricating the same - Google Patents

Electrical connection body and method for fabricating the same Download PDF

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Publication number
KR101505214B1
KR101505214B1 KR1020097022670A KR20097022670A KR101505214B1 KR 101505214 B1 KR101505214 B1 KR 101505214B1 KR 1020097022670 A KR1020097022670 A KR 1020097022670A KR 20097022670 A KR20097022670 A KR 20097022670A KR 101505214 B1 KR101505214 B1 KR 101505214B1
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South Korea
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less
conductive film
conductive particles
anisotropic conductive
surface roughness
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KR1020097022670A
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Korean (ko)
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KR20100077129A (en
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미사오 고니시
요시토 다나카
쇼부 사이토
신야 가와하라
에츠코 이시카와
Original Assignee
데쿠세리아루즈 가부시키가이샤
니혼 엘렉트로플레이팅 엔지니어스 가부시키가이샤
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Publication of KR20100077129A publication Critical patent/KR20100077129A/en
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Publication of KR101505214B1 publication Critical patent/KR101505214B1/en

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Abstract

이방성 도전막에 포함되는 도전성 입자의 입자경이 작은 경우에도 이것을 균일하게 찌부러뜨릴 수 있어, 양호한 도통 특성을 얻을 수 있는 전기적 접속체를 제공한다. 전기적 접속체는, 제 1 전자 부재인 반도체 소자 (1) 와 제 2 전자 부재인 배선 기판 (3) 이 이방성 도전막 (5) 을 개재하여 전기적으로 접속되어 구성된다. 어느 일방의 전자 부재 (여기서는 반도체 소자 (1)) 에는, 범프 (돌기 전극) (2) 가 형성되어 있고, 범프 (2) 의 정상부는, 표면 거칠기 Ra 가 0.05 ㎛ 이하인 평탄면으로 되어 있다. 이방성 도전막 (5) 에 포함되는 도전성 입자 (6) 의 평균 입경은 4 ㎛ 이하이다.Provided is an electrical connecting body capable of uniformly crushing the conductive particles contained in the anisotropic conductive film even when the particle diameter is small, and obtaining good conduction characteristics. The electrical connecting body is constituted such that a semiconductor element 1 as a first electronic member and a wiring substrate 3 as a second electronic member are electrically connected via an anisotropic conductive film 5. Bumps (protruding electrodes) 2 are formed on one of the electronic members (here, the semiconductor element 1), and the tops of the bumps 2 are flat surfaces having a surface roughness Ra of 0.05 m or less. The average particle diameter of the conductive particles 6 contained in the anisotropic conductive film 5 is 4 占 퐉 or less.

반도체 소자, 배선 기판, 이방성 도전막, 돌기 전극 A semiconductor element, a wiring board, an anisotropic conductive film,

Description

전기적 접속체 및 그 제조 방법{ELECTRICAL CONNECTION BODY AND METHOD FOR FABRICATING THE SAME}BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an electrical connecting body,

본 발명은, 반도체 소자나 전자 기판 등의 전자 부재끼리가 전기적으로 접속된 전기적 접속체에 관한 것으로, 특히 돌기 전극 (범프) 및 이방성 도전막을 이용하여 전기적인 접속을 실시한 전기적 접속체에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical connection body in which electronic components such as semiconductor elements and electronic boards are electrically connected to each other. More particularly, the present invention relates to an electrical connection body in which electrical connection is made using protruding electrodes (bumps) and anisotropic conductive films.

종래부터, 예를 들어 반도체 소자 등의 전자 부재를 배선 기판에 실장하는 경우에는, 와이어 본딩에 의해 반도체 소자의 단자 전극과 배선 기판의 전극을 전기적으로 접속하는 것이 널리 실시되고 있다. 단, 이런 종류의 와이어 본딩에 의한 접속에서는, 전극 사이를 일일이 본딩 와이어로 접속해야 해서 접속 공정이 번잡한 것, 고밀도 실장에 따른 단자 전극의 미세화, 좁은 피치화 등에 대한 대응이 곤란한 것 등의 문제가 있어 그 개선이 요망되고 있다.BACKGROUND ART [0002] Conventionally, for example, when an electronic member such as a semiconductor element is mounted on a wiring board, it is widely practiced to electrically connect the terminal electrode of the semiconductor element and the electrode of the wiring substrate by wire bonding. However, in this kind of wire bonding connection, it is necessary to connect the electrodes with each other through a bonding wire, so that the connection process is troublesome, and it is difficult to cope with miniaturization of the terminal electrode due to high-density mounting, There is a need for improvement.

이와 같은 상황에서, 반도체 소자를 이른바 페이스 다운 상태로 배선 기판 상에 실장하는 플립칩 실장법이 제안되어 있다. 이 플립칩 실장법은, 반도체 소자의 단자 전극, 혹은 배선 기판의 전극 중 어느 일방에 범프라고 하는 돌기 전극을 형성하고, 이 돌기 전극이 타방의 전극과 대향하도록 배치하여, 일괄하여 전기적으로 접속하는 방법이다. 돌기 전극은 Au 이나 Cu, 땜납 등을 도금함으로 써 형성되고, 그 높이는 수 ㎛ ∼ 수십 ㎛ 정도이다.In such a situation, a flip chip mounting method in which a semiconductor element is mounted on a wiring board in a so-called face-down state has been proposed. In this flip chip mounting method, a protruding electrode called a bump is formed on either one of a terminal electrode of a semiconductor element or an electrode of a wiring board, and the protruding electrode is disposed so as to face the other electrode, Method. The protruding electrodes are formed by plating Au, Cu, or solder, and the height thereof is about several 탆 to several tens of 탆.

이와 같은 플립칩 실장법에 있어서는, 접속 신뢰성을 높이는 것 등을 목적으로 이방성 도전막이 사용되고 있다. 이방성 도전막은, 접착제로서 기능하는 절연성 수지 중에 도전성 입자를 분산시킨 것으로, 돌기 전극과 대향하는 전극 사이에 이것을 끼워넣고, 가열, 가압하면 도전성 입자가 전극 사이에서 눌려 찌부러져 전기적인 접속이 도모된다. 돌기 전극이 없는 부분에서는, 도전성 입자는 절연성 수지 중에 분산된 상태가 유지되어, 전기적으로 절연된 상태가 유지되므로, 돌기 전극이 있는 부분에서만 전기적 도통이 도모되게 된다.In such a flip chip mounting method, an anisotropic conductive film is used for the purpose of improving connection reliability and the like. The anisotropic conductive film is formed by dispersing conductive particles in an insulating resin functioning as an adhesive. When the conductive particles are sandwiched between the protruding electrodes and the opposed electrodes and heated and pressed, the conductive particles are pressed and broken between the electrodes. In the portion where the projection electrode is not present, the conductive particles remain dispersed in the insulating resin, and the electrically insulated state is maintained. Therefore, electrical conduction can be achieved only at the portion where the projection electrode is present.

이방성 도전막을 사용한 플립칩 실장법에 의하면, 상기 서술한 바와 같이, 다수의 전극 사이를 일괄하여 전기적으로 접속할 수 있어, 와이어 본딩과 같이 전극 사이를 일일이 본딩 와이어로 접속할 필요가 없고, 또한 고밀도 실장에 따른 단자 전극의 미세화, 좁은 피치화 등에 대한 대응도 비교적 용이하다.According to the flip chip mounting method using the anisotropic conductive film, as described above, a plurality of electrodes can be electrically connected together at one time, and there is no need to connect the electrodes with each other by bonding wires like wire bonding, It is relatively easy to cope with miniaturization of the terminal electrode and narrow pitching.

이와 같은 이방성 도전막을 사용한 플립칩 실장법에서는, 전기적 접속의 신뢰성 확보를 위해, 돌기 전극 상에 있어서의 도전성 입자의 포착성을 높일 필요가 있어, 각 방면에서 검토가 진행되고 있다. 예를 들어 돌기 전극의 높이가 불균일하면 접속에 문제가 생기기 때문에, 돌기 전극의 높이를 균일하게 하는 기술이 제안되어 있다 (예를 들어 특허 문헌 1 내지 특허 문헌 6 등 참조).In the flip chip mounting method using such an anisotropic conductive film, in order to secure the reliability of the electrical connection, it is necessary to increase the ability to capture the conductive particles on the protruding electrodes, and studies have been made in various respects. For example, when the heights of the protruding electrodes are not uniform, a problem arises in connection, so that a technique of uniformizing the height of the protruding electrodes has been proposed (see, for example, Patent Documents 1 to 6).

구체적으로는, 특허 문헌 1 에는, 전극부를 갖는 반도체 소자를 전극 패턴을 갖는 기판 상에 실장하는 방법이 개시되어 있다. 특히, 이 실장 방법에 있어서는, 반도체 소자의 전극부에 반도체 소자 표면보다 돌출된 도전성 돌출부를 형성하 고, 이 돌출부를 강체 표면에 일단 밀어넣고, 기판 혹은 반도체 소자의 적어도 일방에 접착용 수지를 도포하고, 돌출부와 전극 패턴이 접촉하도록 반도체 소자와 기판을 가압하여 접합시킨 후, 접착용 수지를 경화시키도록 하고 있다.Specifically, Patent Document 1 discloses a method of mounting a semiconductor element having an electrode portion on a substrate having an electrode pattern. Particularly, in this mounting method, a conductive protruding portion protruding from the surface of the semiconductor element is formed in the electrode portion of the semiconductor element, the protruding portion is once pushed into the surface of the rigid body, the adhesive resin is applied to at least one of the substrate or the semiconductor element The semiconductor element and the substrate are pressed and bonded to each other so that the projecting portion and the electrode pattern are in contact with each other, and then the resin for bonding is cured.

또한 특허 문헌 2 에는, 기판 표면에 형성된 다수의 전로(電路) 상에 반도체 소자의 전극과의 접합에 사용하는 범프를 형성하는 방법으로서, 범프가 가압에 의해 높이가 일치된 것으로 되어 있는 것을 특징으로 하는 범프의 제법이 개시되어 있다.Patent Document 2 discloses a method of forming a bump used for bonding with an electrode of a semiconductor element on a plurality of electric paths formed on a surface of a substrate, A bump forming method is disclosed.

또한 특허 문헌 3 에는, 내부에 도체가 충전된 스루홀을 갖는 세라믹 회로 기판의 적어도 범프 형성면을 연마하고, 표면에 노출된 스루홀 도체 상에 금속 소편을 납땜하는 것을 특징으로 하는 범프 형성 기판의 제조 방법이 개시되어 있다.In Patent Document 3, at least a bump forming surface of a ceramic circuit board having a through hole filled with a conductor therein is polished, and a piece of metal is soldered on the through hole conductor exposed on the surface of the bump forming substrate. A manufacturing method is disclosed.

그리고 또한 특허 문헌 4 에는, 하층에 은 도금층을 형성함과 함께, 그 상 층에 니켈 도금층을 형성하고, 또한 그 상층에 금 도금층을 형성한 구성을 갖는 리드 표면에 있어서, 페이스 다운 본딩에 의해 탑재되는 반도체 장치의 전극 패드와 대향하는 부분에 금 도금에 의해 기둥 형상의 돌기 전극을 형성하고, 또한, 이 돌기 전극을 반도체 장치 실장 기판의 상방향으로부터 평판에 의해 가압하여, 반도체 장치의 전극 패드와의 접촉면이 되는 복수 개의 돌기 전극의 표면을 동일 평면 내에 일치시키도록 평탄화하는 기술이 개시되어 있다.Patent Document 4 discloses a lead surface having a structure in which a silver plating layer is formed on a lower layer and a nickel plating layer is formed on the upper layer and a gold plating layer is formed on the upper layer, A protruding electrode in a columnar shape is formed by gold plating on a portion of the semiconductor device facing the electrode pad and the protruding electrode is pressed by the flat plate from the upward direction of the semiconductor device mounting substrate, And the surface of the plurality of protruding electrodes, which are the contact surfaces of the protruding electrodes, are matched in the same plane.

또한 특허 문헌 5 에는, 땜납 돌기 전극의 높이를 일치시킴으로써 실장 불량을 저감시키고, 전기 접속 저항을 저감시킴과 함께 접속 강도를 향상시키는 것을 목적으로 하여, 땜납 돌기 전극에 대하여 접촉함으로써 전기 특성 검사를 실시한 후에, 땜납 돌기 전극의 적어도 정상부를 연마 처리하는 기술이 개시되어 있다.Patent Document 5 discloses a solder bump electrode in which the electrical property is inspected by contacting the solder bump electrode to reduce solder failure by reducing the height of the solder bump electrode to reduce the electrical connection resistance and improve the connection strength Thereafter, at least a top portion of the solder bump electrode is polished.

또한 특허 문헌 6 에는, 범프의 높이를 효율적으로 일치시키는 것을 목적으로 하여, 촬상 수단이 범프의 정상부에 초점을 맞춤과 함께, 그 때의 절삭 수단의 위치를 원점으로 하고, 그 원점을 기준으로 절삭 수단을 구동하여 범프의 절삭을 실시하는 기술이 개시되어 있다.Patent Document 6 discloses a technique in which, with the aim of efficiently matching the bump height, the image pickup means focuses on the top of the bump, and the position of the cutting means at that time is set as the origin, And driving the means to cut the bumps.

또한, 이들 특허 문헌 1 내지 특허 문헌 6 에 기재된 기술 외에, 돌기 전극과 접속 단자 사이에서 도전성 입자의 포착성을 높이기 위해, 돌기 전극에 요철을 형성하는 것도 시도되었다 (예를 들어 특허 문헌 7 내지 특허 문헌 10 등 참조).In addition to the techniques described in Patent Documents 1 to 6, attempts have also been made to form protrusions and protrusions on protruding electrodes in order to enhance the ability to capture conductive particles between protruding electrodes and connection terminals (see, for example, Patent Documents 7 to 6 10).

예를 들어 특허 문헌 7 에는, 액정 셀의 전극과 플렉시블 기판의 전극을 접속하여 이루어지는 액정 표시 장치에 있어서, 플렉시블 기판의 전극은, 조면화된 표면을 갖는 것을 특징으로 하는 액정 표시 장치가 개시되어 있다.For example, Patent Document 7 discloses a liquid crystal display device in which an electrode of a liquid crystal cell is connected to an electrode of a flexible substrate, and the electrode of the flexible substrate has a roughened surface .

또한 특허 문헌 8 에는, 지립을 갖는 연마 시트를 구비한 평면 토대 상에, 범프가 연마 시트에 맞닿도록 반도체 장치 (IC 기판) 를 페이스 다운으로 설치하고, 반도체 장치를 평면 토대에 가압하면서, 가압하는 방향과 수직인 평면 내에서 평면 토대를 초음파 진동시킴으로써 범프의 선단면에 요철면을 형성하는 것이 개시되어 있다.In Patent Document 8, a semiconductor device (IC substrate) is provided face down on a flat base having abrasive sheets having abrasive grains so that the bumps come into contact with the polishing sheet, and the semiconductor device is pressed Discloses that ultrasonic vibration is applied to a flat base in a plane perpendicular to the direction of the bump to form an uneven surface on the front end face of the bump.

또한 특허 문헌 9 에는, 반도체 장치의 전극 상에 금 범프를 형성하는 공정과, 회로 기판 상에 이방성 도전막을 부착하는 공정과, 금 범프보다 단단한 재료로 이루어지고 이방성 도전막의 도전 입자의 직경보다 작은 요철이 형성된 가압용 기판을 반도체 장치의 금 범프의 선단면에 가압함으로써, 금 범프의 선단면에 요철부 를 형성하는 공정과, 금 범프와 회로 기판의 전극을 위치 맞춤한 후, 반도체 장치를 이방성 도전막을 부착한 회로 기판에 가압하고 가열하는 공정을 구비하는 반도체 장치의 실장 방법이 개시되어 있다.Patent Document 9 discloses a method of manufacturing a semiconductor device, which comprises a step of forming a gold bump on an electrode of a semiconductor device, a step of attaching an anisotropic conductive film on a circuit board, Forming a concave-convex portion on the end face of the gold bump by pressing the formed pressing substrate against the front end face of the gold bump of the semiconductor device; and aligning the gold bump and the electrode of the circuit board, And a step of pressing and heating the circuit board with the film attached thereto.

그리고 또한 특허 문헌 10 에는, 범프 전극의 형성시에, 배선 전극 상에 미리 패시베이션 막으로 이루어지는 뿔 형상 혹은 사다리꼴 형상의 볼록부를 복수 형성하고, 이 상태에서 범프 하지 금속층을 퇴적시키고, 또한 그 위에 도금 성장에 의해 금 전극을 형성하여 범프 전극으로 하는 기술이 개시되어 있다. 이로써, 범프 전극의 전극 표면에는, 배선 전극 상에 형성한 요철부에 대응하여 요철부가 형성되게 된다.Patent Document 10 discloses a method in which a plurality of convex portions of a horn or trapezoidal shape made of a passivation film are previously formed on the wiring electrodes at the time of forming the bump electrodes and in this state, To form a gold electrode, thereby forming a bump electrode. As a result, a concavo-convex portion is formed on the electrode surface of the bump electrode corresponding to the concavo-convex portion formed on the wiring electrode.

특허 문헌 1 : 일본 공개특허공보 평1-278034호 Patent Document 1: JP-A-1-278034

특허 문헌 2 : 일본 공개특허공보 평1-295433호 Patent Document 2: JP-A-1-295433

특허 문헌 3 : 일본 공개특허공보 평4-33395호 Patent Document 3: JP-A-4-33395

특허 문헌 4 : 일본 공개특허공보 평5-291262호 Patent Document 4: JP-A-5-291262

특허 문헌 5 : 일본 공개특허공보 제2000-114313호 Patent Document 5: Japanese Patent Application Laid-Open No. 2000-114313

특허 문헌 6 : 일본 공개특허공보 제2006-324397호 Patent Document 6: JP-A-2006-324397

특허 문헌 7 : 일본 공개실용신안공보 소63-174328호 Patent Document 7: Japanese Utility Model Publication No. 63-174328

특허 문헌 8 : 일본 공개특허공보 평6-283537호 Patent Document 8: JP-A-6-283537

특허 문헌 9 : 일본 공개특허공보 평11-16946호 Patent Document 9: JP-A-11-16946

특허 문헌 10 : 일본 공개특허공보 제2004-14778호Patent Document 10: Japanese Laid-Open Patent Publication No. 2004-14778

발명의 개시DISCLOSURE OF INVENTION

그런데, 상기 서술한 플립칩 실장에 사용되는 이방성 도전막에 있어서, 도전성 입자의 입경은 통상 5 ㎛ ∼ 10 ㎛ 의 범위로 되어 있지만, 최근 파인 피치의 요청에 대응하기 위해, 도전성 입자의 비율을 적게 하거나, 도전성 입자의 입자경을 작게 할 것이 요구되고 있다. 예를 들어 도전성 입자의 비율이 많고, 또한 도전성 입자의 입자경이 크면, 파인 피치의 플립칩 실장에 있어서 돌기 전극 사이에 도전성 입자가 막혀, 전기적인 단락 (쇼트) 이 발생한다는 문제가 생긴다.However, in the anisotropic conductive film used for the flip chip mounting described above, the particle diameter of the conductive particles is usually in the range of 5 탆 to 10 탆. However, in order to meet the request of the recent fine pitch, Or to reduce the particle diameter of the conductive particles. For example, when the ratio of the conductive particles is large and the particle diameter of the conductive particles is large, the conductive particles are clogged between the protruding electrodes in the flip chip mounting with a fine pitch, thereby causing a short circuit.

이 경우, 도전성 입자의 비율을 적게 하는 것은 도전성 입자의 포착성에 직결되기 때문에, 도전성 입자의 입자경을 작게 하는 것이 타당하다. 도전성 입자의 입자경을 작게 하면, 돌기 전극 사이 간극의 도전성 입자는 절연성 수지 (접착제) 중에 분산된 상태가 되고, 돌기 전극 사이에서 도전성 입자끼리가 접촉하는 것에 의한 쇼트의 문제는 회피된다.In this case, decreasing the proportion of the conductive particles is directly related to the trapping property of the conductive particles, so it is appropriate to reduce the particle diameter of the conductive particles. When the particle diameter of the conductive particles is reduced, the conductive particles in the gap between the projection electrodes are dispersed in the insulating resin (adhesive), and the problem of shorting due to contact of the conductive particles with each other between the projection electrodes is avoided.

그러나, 도전성 입자의 입자경을 작게 한 경우에는, 돌기 전극의 높이 편차나 실장 정밀도 등에 따라 도전성 입자가 균일하게 찌부러지지 않아, 도통 저항이 불안정해지는 현상이 발생하기 쉽다는 문제가 새롭게 발생한다. 각 돌기 전극 표면의 높이에는 ±2 ㎛ 정도의 편차가 있어 (종래의 돌기 전극의 표면 거칠기 Ra 는 0.3 ㎛ 정도여서), 예를 들어 도전성 입자의 평균 입자경이 4 ㎛ 이하로 되면, 균일하게 눌러 찌부러뜨리는 것은 곤란하다.However, when the particle diameter of the conductive particles is reduced, there arises a problem that the conductive particles are not uniformly crushed by the height deviation of the projection electrodes, the mounting accuracy, and the like, and the phenomenon that the conductive resistance becomes unstable easily occurs. The height of each protruding electrode has a deviation of about 2 占 퐉 (the surface roughness Ra of the conventional protruding electrode is about 0.3 占 퐉). For example, when the average particle diameter of the conductive particles becomes 4 占 퐉 or less, It is difficult to raise.

이와 같은 도전성 입자의 소직경화를 생각한 경우, 상기 서술한 특허 문헌 1 내지 특허 문헌 6 에 기재된 기술과 같은 돌기 전극의 높이를 균일하게 하는 기술로는 대응할 수 없다. 이들 특허 문헌 1 내지 특허 문헌 6 에 기재된 기술에 있어서는, 돌기 전극 사이의 높이 편차를 작게 할 수는 있지만, 돌기 전극 정상부 (선단 평면부) 의 표면 거칠기에서 기인되는 높이 편차는 해소할 수 없어, 돌기 전극 정상부에는 표면 거칠기에 따른 편차가 존재하게 된다. 따라서, 도전성 입자의 입자경이 작아지면, 돌기 전극 상의 도전성 입자가 균일하게 찌부러지지 않는다는 문제는 해결되지 않은 채로 남아 있다. Considering such a small-sized curing of the conductive particles, it is not possible to cope with the technique of making the height of the protruding electrodes uniform, such as the technique described in the above-described Patent Documents 1 to 6. In the techniques described in Patent Documents 1 to 6, although the height deviation between the protruding electrodes can be made small, the height deviation caused by the surface roughness of the protruding electrode top portion (front end flat portion) can not be eliminated, There is a deviation according to the surface roughness at the top of the electrode. Therefore, if the particle diameter of the conductive particles is reduced, the problem that the conductive particles on the protruded electrodes do not collapse uniformly remains unresolvable.

한편, 상기 서술한 특허 문헌 7 내지 특허 문헌 10 에 기재된 기술과 같이, 도전성 입자의 포착성을 높이기 위해 돌기 전극에 요철을 형성하는 기술에서는, 돌기 전극의 표면 거칠기를 크게 하는 방향이며, 이 경우, 포착된 도전성 입자가 요철 내에 비집고 들어가기 때문에 균일하게 찌부러뜨릴 수 없어, 도전성 입자의 소직경화에 대응하는 것은 곤란하다.On the other hand, in the technique of forming the projections and depressions on the projection electrodes in order to enhance the trapping property of the conductive particles as in the above-described technologies described in the above-described Patent Documents 7 to 10, the surface roughness of the projection electrodes is increased. The trapped conductive particles can not be uniformly crushed because they enter into the concave and convex portions, and it is difficult to cope with the hardening of the conductive particles.

또한 반도체 소자 등을 실장할 때에는, 돌기 전극의 경도가 균일해지도록 조정할 목적으로 어닐링 처리를 실시하는 것이 통상적이다. 그러나, 돌기 전극은, 그 정상부를 절삭 등의 처리를 실시함으로써 표면 거칠기를 저감시킬 수 있었다고 해도, 어닐링 처리를 실시함으로써 표면 거칠기가 대폭 증대되어 버린다는 문제도 있었다.When mounting a semiconductor element or the like, annealing is generally performed for the purpose of adjusting the hardness of the protruding electrode to be uniform. However, even if the projecting electrode can reduce the surface roughness by performing a treatment such as cutting, the surface roughness of the projecting electrode is significantly increased by performing the annealing treatment.

본 발명은 이와 같은 실정을 감안하여 이루어진 것으로서, 이방성 도전막에 포함되는 도전성 입자의 입자경이 작은 경우에도 이것을 균일하게 찌부러뜨릴 수 있고, 어닐링 처리를 할지의 여부에 관계없이 양호한 도통 특성을 얻을 수 있는 전기적 접속체 및 그 제조 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and it is an object of the present invention to provide a method of manufacturing an anisotropic conductive film by which even when the particle diameter of the conductive particles contained in the anisotropic conductive film is small, It is another object of the present invention to provide an electrical connecting body and a manufacturing method thereof.

본원 발명자는, 상기 서술한 목적을 달성하기 위해 장기간에 걸쳐서 예의 검토를 거듭해 왔다. 그 결과, 돌기 전극의 표면에 요철을 형성한 경우, 도전성 입자의 포착성에 대해서는 향상되는 케이스도 있지만, 오히려 요철에 의해 돌기 전극 주위에 위치하는 부분의 도전성 입자에 충분한 압력이 전달되지 않아, 돌기 전극 상의 도전성 입자가 균일하게 찌부러지지 않는 것, 반대로 돌기 전극의 표면을 각별히 평활하게 함으로써, 도전성 입자의 입경이 작은 경우에, 찌부러짐에 의해 유효하게 작용하는 도전성 입자의 비율이 증가하고, 포착성에 대해서도 거의 문제가 없는 것을 알아내기에 이르렀다.The inventors of the present invention have conducted intensive studies over a long period of time in order to attain the above-mentioned object. As a result, there is a case in which irregularities are formed on the surface of the protruding electrode, but there is a case where the trapping property of the conductive particles is improved. Rather, the irregularities do not transfer sufficient pressure to the conductive particles in the portion located around the protruding electrode, On the other hand, the surface of the protruding electrode is made particularly smooth so that when the particle diameter of the conductive particles is small, the proportion of the conductive particles effectively acting by crushing increases, I came to find out that there is almost no problem.

본 발명은, 이와 같은 지견에 기초하여 완성된 것이다. 즉, 상기 서술한 목적을 달성하는 본 발명에 관련된 전기적 접속체는, 제 1 전자 부재와 제 2 전자 부재가 이방성 도전막을 개재하여 전기적으로 접속되어 이루어지는 전기적 접속체로서, 어느 일방의 전자 부재에는 돌기 전극이 형성되어 있고, 상기 돌기 전극의 정상부는, 어닐링 처리 후의 표면 거칠기 Ra 가 0.05 ㎛ 이하인 평탄면으로 되어 있는 것을 특징으로 한다.The present invention has been completed on the basis of such findings. That is, the electrical connecting body according to the present invention for achieving the above-mentioned object is an electrical connecting body in which a first electronic member and a second electronic member are electrically connected via an anisotropic conductive film, And the top of the protruding electrode is a flat surface having a surface roughness Ra of 0.05 m or less after the annealing treatment.

또한, 상기 서술한 목적을 달성하는 본 발명에 관련된 전기적 접속체의 제조 방법은, 제 1 전자 부재와 제 2 전자 부재의 어느 일방에, 도금에 의해 정상부의 표면 거칠기 Ra 가 0.05 ㎛ 이하인 평탄면으로 된 돌기 전극을 형성하는 공정과, 상기 제 1 전자 부재와 상기 제 2 전자 부재 사이에 이방성 도전막을 개재시키는 공정과, 가압에 의해 상기 돌기 전극과 대향하는 이방성 도전막의 도전성 입자를 눌러 찌부러뜨려, 상기 제 1 전자 부재와 상기 제 2 전자 부재를 전기적으로 접속하는 공정을 구비하는 것을 특징으로 한다.The method for manufacturing an electrical contact according to the present invention for achieving the above object is a method for manufacturing an electrical connecting body according to any one of the first to fifth aspects of the present invention, wherein a top surface having a surface roughness Ra of 0.05 m or less Forming a protruding electrode on the protruded electrode; forming an anisotropic conductive film between the first electronic member and the secondelectronic member; pressing the conductive particles of the anisotropic conductive film opposed to the protruded electrode by pressing; And a step of electrically connecting the first electronic member and the second electronic member.

입경이 작은 도전성 입자가 분산된 이방성 도전막을 사용하였을 경우, 돌기 전극의 표면 거칠기 Ra 가 크고, 표면에 요철이 형성되어 있으면, 제 1 전자 부재와 제 2 전자 부재 사이에 이방성 도전막을 끼워넣고, 상기 돌기 전극과 대향하는 전극 사이에서 상기 이방성 도전막을 가압하였을 때에, 돌기 전극 표면의 예를 들어 오목부에 비집고 들어간 도전성 입자에 압력이 충분히 전달되지 않아 충분히 찌부러지지 않는다. 도전성 입자가 충분히 찌부러지지 않으면 전기적인 접촉 면적 등이 부족하여, 도통 신뢰성을 확보하기 어렵다.When an anisotropic conductive film in which conductive particles with small particle diameters are dispersed is used, an anisotropic conductive film is sandwiched between the first and second electromagnetic members when the surface roughness Ra of the protruding electrodes is large and irregularities are formed on the surface, When the anisotropic conductive film is pressed between the protruding electrode and the opposed electrode, pressure is not sufficiently transmitted to the conductive particles, for example, the concave portion of the surface of the protruding electrode. If the conductive particles are not crushed sufficiently, the electrical contact area or the like is insufficient and it is difficult to secure conduction reliability.

이에 대하여, 본 발명에 있어서는, 돌기 전극의 표면 거칠기 Ra 가 0.05 ㎛ 이하로 되어 매우 평활한 상태로 되어 있다. 특히, 본 발명에 있어서는, 어닐링 처리 후에도 표면 거칠기 Ra 가 0.05 ㎛ 이하로 되어, 어닐링 처리를 할지의 여부에 관계없이 돌기 전극의 정상부가 매우 평활한 상태를 유지할 수 있다. 따라서, 도전성 입자의 입경이 작아도 각 도전성 입자에 균일하게 압력이 가해져 균일한 입자 변형이 실현된다.On the contrary, in the present invention, the surface roughness Ra of the protruding electrode is 0.05 m or less, which is a very smooth state. Particularly, in the present invention, the surface roughness Ra becomes 0.05 m or less even after the annealing process, and the top of the projection electrode can be maintained in a very smooth state regardless of whether the annealing process is performed or not. Therefore, even when the particle diameter of the conductive particles is small, uniform pressure is applied to each of the conductive particles, and uniform particle deformation is realized.

본 발명에 의하면, 이방성 도전막에 포함되는 도전성 입자의 입자경이 작은 경우에도 이것을 균일하게 찌부러뜨릴 수 있어, 양호한 도통 특성을 얻을 수 있다. 따라서, 본 발명에 의하면, 도통 신뢰성이 우수한 전기적 접속체를 제공할 수 있다.According to the present invention, even when the particle diameter of the conductive particles contained in the anisotropic conductive film is small, it can be evenly crushed and good conduction characteristics can be obtained. Therefore, according to the present invention, it is possible to provide an electrical connecting body having excellent conduction reliability.

도 1 은, 전기적 접속체의 일 구성예를 나타내는 개략 단면도이다.1 is a schematic cross-sectional view showing a structural example of an electrical connecting member.

도 2 는, 범프의 표면에 요철이 있는 경우 도전성 입자가 찌부러지는 정도를 모식적으로 나타내는 개략 단면도이다.Fig. 2 is a schematic cross-sectional view schematically showing the degree of collapse of the conductive particles when the surface of the bumps has irregularities.

도 3 은, 실시예 1 에 있어서의 범프 근방의 광학 현미경 이미지이다.3 is an optical microscope image of the vicinity of the bump in the first embodiment.

도 4 는, 비교예 1 에 있어서의 범프 근방의 광학 현미경 이미지이다.4 is an optical microscope image of the vicinity of the bumps in Comparative Example 1. Fig.

도 5 는, 실시예 1 에 있어서의 범프 근방의 다른 광학 현미경 이미지이다.5 is another optical microscope image in the vicinity of the bump in the first embodiment.

도 6 은, 비교예 1 에 있어서의 범프 근방의 다른 광학 현미경 이미지이다.6 is another optical microscope image in the vicinity of the bumps in Comparative Example 1. Fig.

도 7 은, 실시예 1 에 있어서의 범프 단면의 결정립의 모습을 나타내는 도면이다.7 is a view showing a state of crystal grains in the bump section in Example 1. Fig.

발명을 실시하기 위한 최선의 형태BEST MODE FOR CARRYING OUT THE INVENTION

이하, 본 발명을 적용한 구체적인 실시형태에 대하여 도면을 참조하면서 상세히 설명한다. 한편, 본 명세서에 있어서는, 범프와 돌기 전극은 동일한 의미로서 취급하는 것으로 한다.Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. On the other hand, in the present specification, the bump and the protruding electrode are treated as the same meaning.

도 1 은, 전기적 접속체의 일례를 나타내는 것이다. 전기적 접속체는, 예를 들어 반도체 소자 등의 전자 부재를 배선 기판 등의 전자 부재와 전기적 및 기계적으로 접속 고정시킨 것이다. 여기서는, 제 1 전자 부재가 반도체 소자 (IC 칩) 이고, 제 2 전자 부재가 배선 기판인 경우를 예로 들어 설명한다.Fig. 1 shows an example of an electrical connecting body. The electrical connecting body is, for example, an electronic member such as a semiconductor element electrically and mechanically connected and fixed to an electronic member such as a wiring board. Here, the case where the first electronic member is a semiconductor element (IC chip) and the second electronic member is a wiring substrate will be described as an example.

도 1 에 있어서, 제 1 전자 부재인 반도체 소자 (1) 에는, 접속 단자로서 범프 (돌기 전극) (2) 가 형성되어 있다. 한편, 제 2 전자 부재인 배선 기판 (3) 에는, 범프 (2) 와 대향하는 위치에 전극 (4) 이 형성되어 있다. 반도체 소자 (1) 와 배선 기판 (3) 사이에는 이방성 도전막 (5) 이 개재되고, 범프 (2) 와 전극 (4) 이 대향하는 부분에서는, 이 이방성 도전막 (5) 에 포함되는 도전성 입자 (6) 가 눌려 찌부러져 전기적인 도통이 도모된다.In Fig. 1, bumps (protruding electrodes) 2 are formed as connection terminals in a semiconductor element 1 as a first electronic member. On the other hand, the electrodes 4 are formed on the wiring board 3, which is the second electronic member, at positions facing the bumps 2. [ The anisotropic conductive film 5 is interposed between the semiconductor element 1 and the wiring board 3 and the conductive particles 5 contained in the anisotropic conductive film 5 are located at the portions where the bumps 2 and the electrodes 4 face each other. (6) is crushed and broken, so that electrical conduction is achieved.

범프 (2) 는, 예를 들어 Au 이나 Cu, 땜납 등의 도전성 금속에 의해 형성되고, 그 높이는 5 ㎛ 내지 50 ㎛ 정도이다. 범프 (2) 는, 도금 등에 의해 형성할 수 있고, 예를 들어 표면만을 금 도금으로 할 수도 있다. 범프 (2) 는, 후술하는 바와 같이 표면 평활성이 요구되고, 이와 같은 관점에서도 금 도금으로 하는 것이 바람직하다.The bumps 2 are formed of a conductive metal such as Au, Cu, or solder, and have a height of about 5 탆 to 50 탆. The bumps 2 can be formed by plating or the like. For example, only the surface can be plated with gold. The bump 2 is required to have surface smoothness as described later, and from this viewpoint, it is preferable to use gold plating.

이와 같은 구조의 전기적 접속체에 있어서는, 반도체 소자 (1) 에 형성된 범프 (2) 의 표면 거칠기가 중요하다. 범프 (2) 의 표면 거칠기가 크면, 예를 들어 도 2 에 모식적으로 나타내는 바와 같이, 일부의 도전성 입자 (6) 가 범프 (2) 접속면의 오목부 (2a) 내에 비집고 들어가, 가압해도 압력이 가해지지 않아, 찌부러지지 않은 상태가 되어 도통 저항이 불안정해지는 현상이 발생하기 쉽다. 이에 대하여, 범프 (2) 의 접속면이 평탄하면, 범프 (2) 와 전극 (4) 사이에 포착된 모든 도전성 입자 (6) 가 균일하게 눌려 찌부러져, 도통 신뢰성이 안정적으로 확보된다.In the electrical connecting body having such a structure, the surface roughness of the bumps 2 formed on the semiconductor element 1 is important. If the surface roughness of the bump 2 is large, for example, as shown schematically in FIG. 2, some of the conductive particles 6 may fit into the concave portion 2a of the connection surface of the bump 2, Is not applied and is not collapsed, so that the conductive resistance tends to become unstable. On the other hand, if the connection surface of the bump 2 is flat, all the conductive particles 6 caught between the bump 2 and the electrode 4 are uniformly pressed and crushed, and reliability of conduction is stably ensured.

이와 같은 관점에서, 본 발명에 있어서는, 범프 (2) 의 표면 거칠기를 중심선 평균 거칠기 Ra 로 0.05 ㎛ 이하로 한다. 전기적 접속체에 있어서는, 이 표면 거칠기 Ra 를 0.05 ㎛ 이하로 함으로써, 예를 들어 도전성 입자 (6) 의 평균 입경이 4 ㎛ 이하인 경우에도 균일한 입자 변형을 실현할 수 있게 된다. 또한, 범프 (2) 의 표면 거칠기 Ra 는, 도전성 입자 (6) 의 평균 입자경을 고려하여 설정하는 것이 바람직하고, 특히 0.02 ㎛ 이하인 것이 바람직하다.From this point of view, in the present invention, the surface roughness of the bumps 2 is set to 0.05 m or less in terms of the center line average roughness Ra. In the electrical connecting body, by making the surface roughness Ra equal to or less than 0.05 mu m, it is possible to realize uniform particle deformation even when the average particle diameter of the conductive particles 6 is 4 mu m or less. The surface roughness Ra of the bumps 2 is preferably set in consideration of the average particle diameter of the conductive particles 6, and is preferably 0.02 占 퐉 or less.

범프 (2) 의 표면 거칠기 Ra 는, 예를 들어 Tencor 사 제조 서페이스 프로파일러 등의 접촉식 측정기를 사용함으로써 측정할 수 있다.The surface roughness Ra of the bumps 2 can be measured, for example, by using a contact type measuring instrument such as a surface profiler manufactured by Tencor Corporation.

여기서, 전기적 접속체에 있어서는, 후공정에서 어닐링 처리를 실시하는 경우에는, 만일 어닐링 처리 전의 표면 거칠기 Ra 를 0.05 ㎛ 이하로 형성할 수 있었다고 한 경우라도, 어닐링 처리 후에 표면 거칠기 Ra 가 대폭 증대되어 버리는 것이 통상적이다. 이에 대하여, 본 발명에 관련된 전기적 접속체에 있어서는, 범프 (2) 의 형성시에 도금의 결정 상태를 제어함으로써, 어닐링 처리 전후에 걸쳐서 그 표면 거칠기 Ra 를 0.05 ㎛ 이하, 보다 바람직하게는 0.02 ㎛ 이하로 유지할 수 있게 하고 있다.Here, in the case of performing the annealing treatment in the subsequent step, in the case of the electrical connecting body, even if the surface roughness Ra before the annealing treatment can be formed to 0.05 mu m or less, the surface roughness Ra is greatly increased after the annealing treatment Lt; / RTI > On the other hand, in the electrical connecting body according to the present invention, by controlling the crystal state of the plating at the time of forming the bumps 2, the surface roughness Ra of the bump 2 is 0.05 mu m or less, more preferably 0.02 mu m or less As shown in FIG.

또한 범프 (2) 는, 표면 거칠기 Ra 외에, 그 경도에 대해서도 적정하게 설정하는 것이 바람직하다. 범프 (2) 의 경도는, 범프 (2) 에 사용하는 도전성 재료의 종류나, 예를 들어 도금 형성할 때의 형성 조건 등에 따라 설계할 수 있는데, 도전성 입자 (6) 의 균일한 입자 변형을 실현하기 위해서는, 비커스 경도 Hv 로 40 ∼ 150 으로 하는 것이 바람직하다. 전기적 접속체에 있어서는, 범프 (2) 의 비커스 경도 Hv 를 이 값의 범위 내로 설정함으로써, 도전성 입자 (6) 를 눌러 찌부러뜨릴 때에 가압력이 적정하게 도전성 입자 (6) 에 전달되어, 균일하게 눌러 찌부러뜨릴 수 있게 된다.It is also preferable that the bumps 2 are appropriately set to the hardness in addition to the surface roughness Ra. The hardness of the bumps 2 can be designed in accordance with the kind of the conductive material used for the bumps 2 and the forming conditions for forming the plating, for example, and it is possible to realize uniform particle deformation of the conductive particles 6 It is preferable that the Vickers hardness Hv is 40 to 150. By setting the Vickers hardness Hv of the bump 2 within the range of this value, the pressing force is appropriately transmitted to the conductive particles 6 at the time of pushing the conductive particles 6 in the electrical connecting body, You can trick.

한편, 전기적 접속체에 있어서, 범프 (2) 와 전극 (4) 사이의 전기적 접속 및 기계적 고정을 도모하기 위해 사용되는 이방성 도전막 (5) 은, 절연성 수지 중에 도전성 입자 (6) 를 분산시킨 것이다. 절연성 수지로는, 예를 들어 우레탄 수지나 폴리에스테르 수지, 클로로프렌 등의 열가소성 핫멜트 수지나, 에폭시 수지 등의 열경화성 수지 등을 사용할 수 있다. 또한, 예를 들어 에폭시 수지로는 BPA 형 에폭시 수지, BPF 형 에폭시 수지, 노볼락형 에폭시 수지, 또는 고무나 우레탄 등의 각종 변성 에폭시 수지 등이 예시되고, 이들을 단독으로 사용해도 되고 2 종 이상을 혼합하여 사용해도 된다.On the other hand, the anisotropic conductive film 5 used for establishing electrical connection and mechanical fixing between the bumps 2 and the electrodes 4 in the electrical connecting body is obtained by dispersing the conductive particles 6 in the insulating resin . As the insulating resin, for example, urethane resin, polyester resin, thermoplastic hot melt resin such as chloroprene, thermosetting resin such as epoxy resin and the like can be used. Examples of the epoxy resin include BPA type epoxy resin, BPF type epoxy resin, novolak type epoxy resin, and various modified epoxy resins such as rubber and urethane. These may be used alone or in combination of two or more kinds. They may be mixed and used.

또한, 이방성 도전막 (5) 중에 잠재성 경화제를 첨가하고, 가열을 실시하여 경화제를 활성화시키도록 해도 된다. 이방성 도전막 (5) 에 잠재성 경화제를 첨가함으로써, 기폭 반응성을 부여할 수 있고, 접속시의 가열 조작에 의해 확실하고 또한 신속하게 경화시킬 수 있게 된다. 이 경우, 잠재성 경화제로는, 이미다졸계 잠재성 경화제 등을 사용할 수 있고, 예를 들어 표면 처리되어 마이크로 캡슐화된 상품명 노바큐아 HX3741 (아사히 화성사 제조), 상품명 노바큐아 HX3921HP (아사히 화성사 제조), 상품명 아미큐아 PN-23 (아지노모토사 제조), 상품명 ACR 하드나 H-3615 (ACR 사 제조) 등을 들 수 있다.Further, a latent curing agent may be added to the anisotropic conductive film 5 and heated to activate the curing agent. By adding a latent curing agent to the anisotropic conductive film 5, it is possible to impart an ignition reactivity, and the curing can be reliably and quickly performed by a heating operation at the time of connection. In this case, as the latent curing agent, an imidazole-based latent curing agent or the like can be used. For example, Novacure HX3741 (manufactured by Asahi Chemical Industry Co., Ltd.), surface-treated and microencapsulated, Nova Cure HX3921HP (manufactured by Asahi Chemical Industry Co., , Trade name Amicia PN-23 (manufactured by Ajinomoto), trade name ACR Hard and H-3615 (manufactured by ACR), and the like.

이방성 도전막 (5) 에 포함되는 절연성 수지의 점도가 높으면, 도통시킬 전극 사이로부터 절연성 수지를 충분히 배제할 수 없게 되어, 도통 신뢰성이 저하될 우려가 있다. 또한, 이방성 도전막 (5) 에 포함되는 절연성 수지의 점도가 높아진 경우, 접속할 전극 사이의 절연성 수지를 충분히 배제시키기 위해 열경화시의 프레스 압력을 높일 필요가 있어, 도전성 입자 (6) 의 범프 (2) 나 전극 (4) 에 대 한 충돌이 강해져 크랙 등이 발생할 우려도 있다. 따라서, 절연성 수지는, 이방성 도전막 (5) 의 열압착 온도에서의 용융 점도가 108 mPa·s 이하인 것이 바람직하고, 107 mPa·s 이하인 것이 보다 바람직하다.If the viscosity of the insulating resin contained in the anisotropic conductive film 5 is high, the insulating resin can not be sufficiently removed from between the electrodes to be conducted, and the reliability of conduction may be lowered. When the viscosity of the insulating resin contained in the anisotropic conductive film 5 is increased, it is necessary to increase the pressing pressure at the time of thermal curing in order to sufficiently remove the insulating resin between the electrodes to be connected. 2 or the electrode 4 may become stronger to cause cracks or the like. Therefore, the insulating resin preferably has a melt viscosity of 10 8 mPa s or less at the thermocompression bonding temperature of the anisotropic conductive film 5, and more preferably 10 7 mPa 쨌 s or less.

한편, 절연성 수지의 열압착시의 용융 점도가 지나치게 낮아지면, 도전성 입자 (6) 가 도통시킬 전극 사이가 벗어나기 쉬워져, 포착성 면에서 문제가 생길 우려가 있다. 따라서 절연성 수지는, 이방성 도전막 (5) 의 열압착 온도에서의 용융 점도가 10 mPa·s 이상인 것이 바람직하다.On the other hand, if the melting viscosity at the time of thermocompression bonding of the insulating resin is excessively low, there is a fear that the electrodes to be electrically connected to the conductive particles 6 are likely to deviate from each other, thereby causing a problem in terms of the trapping property. Therefore, it is preferable that the insulating resin has a melt viscosity of 10 mPa · s or more at the thermocompression bonding temperature of the anisotropic conductive film 5.

이방성 도전막 (5) 을 구성하는 도전성 입자 (6) 로는, 이런 종류의 이방성 도전막에 있어서 사용되고 있는 공지된 도전성 입자를 모두 사용할 수 있다. 예를 들어 니켈, 철, 구리, 알루미늄, 주석, 납, 크롬, 코발트, 은, 금 등 각종 금속이나 금속 합금의 입자, 금속 산화물, 카본, 그라파이트, 유리나 세라믹, 플라스틱 등의 입자 표면에 금속을 코팅한 것, 혹은 이들 입자 표면에 추가로 절연 박막을 코팅한 것 등을 사용할 수 있다.As the conductive particles 6 constituting the anisotropic conductive film 5, any known conductive particles used in this type of anisotropic conductive film can be used. For example, a metal is coated on the surfaces of particles of various metals or metal alloys such as nickel, iron, copper, aluminum, tin, lead, chromium, cobalt, silver and gold, metal oxide, carbon oxide, graphite, glass, ceramic, Or a coating of an insulating thin film on the surface of these particles, or the like.

단, 본 발명에 관련된 전기적 접속체에 있어서는, 도전성 입자 (6) 가 전극 사이에서 눌려 찌부러질 필요가 있기 때문에, 수지 입자의 표면에 금속을 코팅한 것이 바람직하다. 이 경우, 수지 입자로는, 20 % 압축 변형시의 압축 경도가 100 ∼ 1000 kgf/㎟ (1 kgf/㎟ = 9.80665 ㎫) 인 것을 사용하는 것이 바람직하다. 수지 입자의 20 % 압축 변형시의 K 값이 1000 kgf/㎟ 보다 크면, 수지 입자가 적당히 찌부러지지 않기 때문에 전극 표면의 높이 편차를 흡수할 수 없고, 또한, 가압시에 높은 압력이 필요해짐과 함께, 도전성 입자 (6) 의 반발력이 커져 계면 박리를 일으키는 등의 문제가 생길 우려도 있다.However, in the electrical connecting body according to the present invention, it is preferable that the surface of the resin particles is coated with a metal because the conductive particles 6 need to be pressed between the electrodes. In this case, it is preferable that the resin particles have a compression hardness of 100 to 1000 kgf / mm 2 (1 kgf / mm 2 = 9.80665 MPa) at 20% compression deformation. If the K value at 20% compression deformation of the resin particles is larger than 1000 kgf / mm < 2 >, the resin particles are not properly crushed and the height deviation of the electrode surface can not be absorbed. , The repulsive force of the conductive particles 6 becomes large, which may cause problems such as interface delamination.

이와 같은 요구를 만족시키는 수지 입자로는, 예를 들어 에폭시 수지, 페놀 수지, 아크릴 수지, 아크릴로니트릴·스티렌 (AS) 수지, 벤조구아나민 수지, 디비닐벤젠계 수지, 스티렌계 수지 등의 입자를 들 수 있다.Examples of the resin particles satisfying such a requirement include particles of an epoxy resin, a phenol resin, an acrylic resin, an acrylonitrile-styrene (AS) resin, a benzoguanamine resin, a divinylbenzene resin, .

도전성 입자 (6) 의 평균 입경은 임의이지만, 평균 입경이 4 ㎛ 이하인 도전성 입자 (6) 를 사용한 경우에 본 발명의 효과가 크다. 따라서, 도전성 입자 (6) 의 평균 입경은 1 ㎛ ∼ 4 ㎛ 로 하는 것이 바람직하다. 또한, 돌기 전극 정상부의 평탄화에 수반하여, 도전성 입자의 입자경 편차가 도전성 입자의 경도에 따라서는 영향을 받는 경우가 있다. 본 발명의 경우, 도전성 입자의 평균 입자경의 ±1 ㎛ 범위에 전체 입자의 90 % 이상이 포함되어 있는 것이 바람직하다.The average particle diameter of the conductive particles 6 is arbitrary, but the effect of the present invention is large when the conductive particles 6 having an average particle diameter of 4 m or less are used. Therefore, the average particle diameter of the conductive particles 6 is preferably 1 mu m to 4 mu m. In addition, the grain size deviation of the conductive particles may be influenced by the hardness of the conductive particles in accordance with the flattening of the top of the projection electrodes. In the case of the present invention, it is preferable that 90% or more of the total particles are contained in the range of ± 1 μm of the average particle diameter of the conductive particles.

이상과 같은 구성을 구비하는 전기적 접속체에 있어서는, 이방성 도전막 (5) 에 포함되는 도전성 입자 (6) 의 입자경이 예를 들어 4 ㎛ 이하로 작은 경우에도 균일하게 눌러 찌부러뜨릴 수 있어, 양호한 도통 특성을 얻을 수 있다. 따라서, 도통 신뢰성이 우수한 전기적 접속체를 실현할 수 있다.In the electrical connecting body having the above-described configuration, even when the particle diameter of the conductive particles 6 contained in the anisotropic conductive film 5 is as small as 4 m or less, for example, the conductive particles 6 can be uniformly pressed and crushed, Characteristics can be obtained. Therefore, it is possible to realize an electrical connecting body having excellent conduction reliability.

다음으로, 상기 서술한 전기적 접속체의 제조 방법에 대하여 설명한다. 상기 서술한 구성의 전기적 접속체를 제조하려면, 먼저 반도체 소자 (1) 의 전극 상에 범프 (2) 를 형성할 필요가 있다. 이 범프 (2) 는, 도금 등의 수법에 의해 형성하는데, 어닐링 처리 전후에 있어서의 표면 거칠기 Ra 를 0.05 ㎛ 이하로 하기 위해서는 금 도금으로 하는 것이 바람직하고, 또한 도금 조건을 선정함으로 써, 형성되는 범프 (2) 의 표면이 평활해지도록 할 필요가 있다.Next, a method of manufacturing the above described electrical connecting body will be described. In order to manufacture the electrical connection body having the above-described configuration, it is necessary to form the bumps 2 on the electrodes of the semiconductor element 1 first. The bumps 2 are formed by a plating method or the like. In order to reduce the surface roughness Ra before and after the annealing treatment to 0.05 탆 or less, it is preferable to use gold plating. Further, by selecting the plating conditions, It is necessary to make the surface of the bump 2 smooth.

여기서, 금 도금에 있어서는, 결정 상태를 제어하고, 형성되는 범프 (2) 의 표면을 평활하게 하기 위해 이하와 같은 금 도금액이 사용된다.Here, in the gold plating, the following gold plating solution is used to control the crystal state and smooth the surface of the bump 2 to be formed.

금 도금액은, The gold plating solution,

a) 금 화합물a) gold compound

b) 전도염·완충제 b) Conducting salts and buffers

c) 결정 성장제c) Crystal growth agent

d) 유기 광택제d) Organic polish

등을 기본적인 조성으로 하여 구성된다. 금 화합물로는, 예를 들어 아황산금염이나 시안화금염 등이 있다. 또한, 전도염·완충제로는 아황산염, 인산염, 시트르산염, 옥살산염, 황산염, 붕산염, 염산염, 아민염, 킬레이트제 등이 있다. 또한 결정 성장제로는 Tl, Pb, As, Bi, Co, Ni, Fe, Sb 등이 있다. 그리고 또한, 유기 광택제로는, NH 기를 갖는 고분자, 즉, 에톡시화폴리에틸렌이민 (PEIE), 폴리알킬이민 (PAI), 폴리에틸렌이민 (PEI) 등이 있다. 이들의 액 조성으로부터 얻어진 금 도금은, 석출물이 치밀하고 광택성이 있어, 본 발명에서 형성되는 범프 (2) 의 표면을 평활하게 하는 용도로 매우 적합하다.And the like. Examples of the gold compound include a sulfurous acid gold salt and a cyanide gold salt. Conductive salts and buffers include sulfites, phosphates, citrates, oxalates, sulphates, borates, hydrochlorides, amine salts and chelating agents. As the crystal growth agent, there are Tl, Pb, As, Bi, Co, Ni, Fe, and Sb. Examples of the organic brightener include a polymer having an NH group, that is, ethoxylated polyethyleneimine (PEIE), polyalkylimine (PAI), polyethyleneimine (PEI), and the like. The gold plating obtained from these liquid compositions is very suitable for applications in which the precipitates are dense and glossy and the surfaces of the bumps 2 formed in the present invention are smoothed.

범프 (2) 의 형성 후, 반도체 소자 (1) 의 범프 (2) 와 배선 기판 (3) 의 전극 (4) 사이의 접속을 실시하는데, 이 경우에는, 예를 들어 배선 기판 (3) 의 표면에 이방성 도전막 (5) 을 부착하고, 위치 맞춤 및 예비(假)접속을 실시한 후에, 소정의 온도 및 압력으로 열압착을 실시함으로써 도전성 입자 (6) 를 눌러 찌부러뜨 려, 반도체 소자 (1) 의 범프 (2) 와 배선 기판 (3) 의 전극 (4) 을 전기적으로 접속시킨 상태에서 이방성 도전막 (5) 을 구성하는 절연성 수지를 경화시킨다. 열압착시의 온도 및 압력은, 사용하는 이방성 도전막 (5) 의 종류 등에 따라서도 상이하지만, 예를 들어 온도 180 ℃ ∼ 220 ℃, 압력 30 ㎫ ∼ 120 ㎫ 로 하는 것이 바람직하다.After the formation of the bumps 2, the connection between the bumps 2 of the semiconductor element 1 and the electrodes 4 of the wiring board 3 is effected. In this case, for example, the surface of the wiring board 3 After the anisotropic conductive film 5 is attached to the semiconductor element 1 and subjected to positioning and provisional connection, the conductive particles 6 are pressed and pressed by thermocompression at a predetermined temperature and pressure, The insulating resin constituting the anisotropic conductive film 5 is cured while the bumps 2 of the anisotropic conductive film 5 and the electrodes 4 of the wiring board 3 are electrically connected. The temperature and pressure at the time of thermocompression depend on the kind of the anisotropic conductive film 5 to be used and the like, but for example, the temperature and the pressure are preferably from 180 to 220 캜 and from 30 to 120 MPa, respectively.

이상의 공정을 거침으로써, 이방성 도전막 (5) 에 포함되는 도전성 입자 (6) 의 입자경이 작은 경우에도 이것을 균일하게 찌부러뜨릴 수 있어, 제조되는 전기적 접속체에 있어서 양호한 도통 특성을 얻을 수 있다.By carrying out the above steps, even when the particle diameter of the conductive particles 6 contained in the anisotropic conductive film 5 is small, it can be evenly crushed and good conduction characteristics can be obtained in the produced electrical connecting body.

실시예Example

다음으로, 본 발명을 적용한 전기적 접속체의 구체적인 실시에 대하여, 실험 결과에 기초하여 설명한다.Next, concrete implementation of the electrical connecting body to which the present invention is applied will be described based on experimental results.

(실시예 1)(Example 1)

범프의 표면 거칠기 Ra 의 차이에 따른 도전성 입자의 포착성 및 찌부러짐 상태를 평가하기 위해, 이방성 도전막을 개재하여 범프 형성 IC 를 유리에 실장하였다. 이방성 도전막은, 바인더 성분에 도전성 입자를 약 300 만개/㎣ 가 되도록 배합하고, 이것을 필름화하여 형성하였다. 각 성분의 내역은 이하와 같다.In order to evaluate the trapping property and crushing state of the conductive particles according to the difference in the surface roughness Ra of the bumps, the bump-forming IC was mounted on the glass via the anisotropic conductive film. The anisotropic conductive film was formed by compounding the binder component so as to have a conductive particle of about 3,000 particles / square and forming it into a film. Details of each component are as follows.

에폭시 수지 : 재팬 에폭시 레진사 제조, 상품명 EP828 30 중량부Epoxy resin: manufactured by Japan Epoxy Resin Co., Ltd., trade name EP828 30 parts by weight

페녹시 수지 : InChem 사 제조, 상품명 PKHH 40 중량부Phenoxy resin: manufactured by InChem, trade name: PKHH 40 parts by weight

에폭시 경화제 : 아사히 화성사 제조, 상품명 HX3941HP 30 중량부Epoxy curing agent: manufactured by Asahi Chemical Industry Co., Ltd .; trade name: HX3941HP 30 parts by weight

도전성 입자 : Ni/Au 도금 수지 입자Conductive particles: Ni / Au plated resin particles

또한, 도전성 입자로서 평균 입경 4 ㎛ 의 도전성 입자와 평균 입경 2 ㎛ 의 도전성 입자를 사용하여, 2 종류의 이방성 도전막 (이방성 도전막 A 및 이방성 도전막 B) 을 제조하였다.Two kinds of anisotropic conductive films (anisotropic conductive film A and anisotropic conductive film B) were produced using conductive particles having an average particle diameter of 4 占 퐉 and conductive particles having an average particle diameter of 2 占 퐉 as conductive particles.

범프 형성 IC 의 범프는, 금 도금에 의해 형성하였다. 이 금 도금은, 니혼 일렉트로플레이팅·엔지니어스사 제조, 상품명 미크로파브 Au310 을 금 도금액으로서 사용하고, 도금 온도 50 ℃, 전류 밀도 0.4 A/dm2 의 조건으로 실시하였다. 이 결과 얻어진 범프의 접속면의 표면 거칠기 Ra 는 0.0105 ㎛ 였다. 실장시의 압착 조건은, 도달 온도 200 ℃, 압력 40 ㎫, 시간 5 초로 하였다.The bumps of the bump forming IC were formed by gold plating. This gold plating was carried out under the conditions of a plating temperature of 50 캜 and a current density of 0.4 A / dm 2 , using Micropave Au310, manufactured by Nippon Electroplating Engineers Co., Ltd., as a gold plating solution. The resulting surface roughness Ra of the connection surface of the bumps was 0.0105 mu m. The pressing conditions at the time of mounting were as follows: an attained temperature of 200 캜, a pressure of 40 MPa, and a time of 5 seconds.

(실시예 2)(Example 2)

실시예 1 의 금 도금액 및 도금 조건을 변경하여 범프 형성 IC 를 제조하였다. 금 도금은, 니혼 일렉트로플레이팅·엔지니어스사 제조, 상품명 뉴트로네크스 240 을 금 도금액으로서 사용하고, 도금 온도 65 ℃, 전류 밀도 0.5 A/dm2 의 조건으로 실시하였다. 이 결과 얻어진 범프의 접속면의 표면 거칠기 Ra 는 0.004 ㎛ 였다. 그 밖에는 실시예 1 과 동일한 조건으로, 이방성 도전막을 개재하여 범프 형성 IC 를 유리에 실장하였다.A bump-forming IC was produced by changing the gold plating solution and the plating conditions of Example 1. The gold plating was carried out under the conditions of a plating temperature of 65 캜 and a current density of 0.5 A / dm 2 using Neutronax 240, manufactured by Nippon Electroplating Engineers Co., Ltd., as a gold plating solution. The resulting surface roughness Ra of the connection surface of the bump was 0.004 mu m. Otherwise, the bump-forming IC was mounted on the glass through the anisotropic conductive film under the same conditions as in Example 1. [

(비교예 1)(Comparative Example 1)

실시예 1 및 실시예 2 의 금 도금액 및 도금 조건을 변경하여 범프 형성 IC 를 제조하였다. 금 도금은, 니혼 일렉트로플레이팅·엔지니어스사 제조, 상품명 미크로파브 Au100 을 금 도금액으로서 사용하고, 도금 온도 60 ℃, 전류 밀도 0.5 A/dm2 의 조건으로 실시하였다. 이 결과 얻어진 범프의 접속면의 표면 거칠기 Ra 는 0.298 ㎛ 였다. 그 밖에는 실시예 1 과 동일한 조건으로, 이방성 도전막을 개재하여 범프 형성 IC 를 유리에 실장하였다.A bump-forming IC was manufactured by changing the gold plating solution and plating conditions in Example 1 and Example 2. The gold plating was carried out under the conditions of a plating temperature of 60 캜 and a current density of 0.5 A / dm 2 , using Micropave Au100, manufactured by Nippon Electroplating Engineers Co., Ltd., as a gold plating solution. The resulting surface roughness Ra of the connection surface of the bumps was 0.298 mu m. Otherwise, the bump-forming IC was mounted on the glass through the anisotropic conductive film under the same conditions as in Example 1. [

(비교예 2)(Comparative Example 2)

실시예 1 및 실시예 2 그리고 비교예 1 의 금 도금액 및 도금 조건을 변경하여 범프 형성 IC 를 제조하였다. 금 도금은, 니혼 일렉트로플레이팅·엔지니어스사 제조, 상품명 미크로파브 Au660 을 금 도금액으로서 사용하고, 도금 온도 60 ℃, 전류 밀도 0.8 A/dm2 의 조건으로 실시하였다. 이 결과 얻어진 범프의 접속면의 표면 거칠기 Ra 는 0.130 ㎛ 였다. 그 밖에는 실시예 1 과 동일한 조건으로, 이방성 도전막을 개재하여 범프 형성 IC 를 유리에 실장하였다.A bump-forming IC was manufactured by changing the gold plating solution and plating conditions of Example 1, Example 2, and Comparative Example 1. The gold plating was performed under the conditions of a plating temperature of 60 DEG C and a current density of 0.8 A / dm < 2 > using gold microfabric Au660 manufactured by Nippon Electroplating Engineers Co., Ltd. as a gold plating solution. The resulting surface roughness Ra of the connection surface of the bumps was 0.130 mu m. Otherwise, the bump-forming IC was mounted on the glass through the anisotropic conductive film under the same conditions as in Example 1. [

평가evaluation

각 실시예 및 각 비교예로서 제조한 이방성 도전막 A, B 에 대하여, 범프 상에 포착된 도전성 입자를 유리의 이면으로부터 광학 현미경을 사용하여 관찰하고, 입자 포착수를 카운트하여 총입자 포착수를 구하고, 또한 입자의 찌부러짐 상태가 합격인 것을 카운트하여 유효 입자 포착수를 구하였다 (범위 2000 ㎛2). 이 결과를 하기 표 1 및 하기 표 2 에 나타낸다. 또한, 하기 표 1 은 이방성 도전막 A 에 대한 결과를 나타내고, 하기 표 2 는 이방성 도전막 B 에 대한 결과를 나타낸다.The conductive particles captured on the bumps were observed from the back surface of the glass using an optical microscope for each of the anisotropic conductive films A and B prepared as the examples and the comparative examples and the number of particles captured was counted to determine the total number of particles captured , And the particles having passed the crushing state were counted to determine the effective particle trapping number (range: 2000 탆 2 ). The results are shown in Table 1 and Table 2 below. Table 1 shows the results for the anisotropic conductive film A, and Table 2 shows the results for the anisotropic conductive film B.

Figure 112009066468025-pct00001
Figure 112009066468025-pct00001

Figure 112009066468025-pct00002
Figure 112009066468025-pct00002

이들 상기 표 1 및 상기 표 2 로부터 명확한 바와 같이, 범프의 표면 거칠기 Ra 를 0.05 ㎛ 이하로 함으로써, 전기적 접속에 기여하는 유효 도전 입자수가 크게 증가되어 있음을 알 수 있다. 또한, 총입자 포착수에 대해서도 비교예와 동등 이상의 수치로 되어 있다.As apparent from Table 1 and Table 2, it can be seen that the number of effective conductive particles contributing to electrical connection is greatly increased by making the surface roughness Ra of the bumps 0.05 mu m or less. Also, the total number of particles captured is equal to or larger than that of the comparative example.

또한 도 3 에, 실시예 1 (이방성 도전막 A) 에 있어서의 범프 근방의 광학 현미경 이미지를 나타내고, 도 4 에, 비교예 1 (이방성 도전막 B) 에 있어서의 범프 근방의 광학 현미경 이미지를 나타낸다. 이들 도면을 비교하면, 실시예 1 에서는, 범프의 정상부가 매우 평활한 상태로 되어 있는 것이 명백한 반면, 비교예 1 에서는, 범프의 정상부가 거친 모습임을 알 수 있다.Fig. 3 shows an optical microscope image of the vicinity of the bumps in Example 1 (anisotropic conductive film A), and Fig. 4 shows an optical microscope image of the vicinity of the bumps in Comparative Example 1 (anisotropic conductive film B) . Comparing these drawings, it is clear that the top portion of the bump is in a very smooth state in Embodiment 1, whereas in Comparative Example 1, the top portion of the bump is rough.

또한 도 5 에, 실시예 1 (이방성 도전막 A) 에 있어서의 범프 근방의 다른 광학 현미경 이미지를 나타내고, 도 6 에, 비교예 1 (이방성 도전막 B) 에 있어서의 범프 근방의 다른 광학 현미경 이미지를 나타낸다. 어느 도면 (사진) 이나 범프 주변부의 광학 현미경 이미지이다. 이들 도면을 비교하면, 실시예 1 에서는, 범프의 주변부를 포함하여 범프 전체에서 도전성 입자가 균일하게 눌려 찌부러져 있음을 알 수 있다. 이에 대하여, 비교예 1 에서는, 특히 범프 주변부에 있어서 도전성 입자가 찌부러지는 정도가 부족하다.5 shows another optical microscope image in the vicinity of the bumps in Example 1 (anisotropic conductive film A), and FIG. 6 shows another optical microscope image in the vicinity of the bumps in Comparative Example 1 (anisotropic conductive film B) . It is an optical microscope image of any drawing (photograph) or bump periphery. When these figures are compared, it can be seen that in the first embodiment, the conductive particles are uniformly pressed and crushed in the entire bumps including the periphery of the bumps. On the other hand, in Comparative Example 1, the degree of crushing of the conductive particles in the periphery of the bump was insufficient.

어닐링Annealing 처리의 영향 평가 Impact assessment of treatment

다음으로, 범프의 표면 거칠기 Ra 에 대한 어닐링 처리의 영향을 평가하기 위해, 실시예 1 로서 제조한 범프 형성 IC 에 대하여 어닐링 처리를 실시하고, 어닐링 처리 전후에 있어서의 표면 거칠기 Ra 를 측정하였다. 이 결과를 하기 표 3 에 나타낸다.Next, in order to evaluate the influence of the annealing process on the surface roughness Ra of the bumps, the bump forming IC manufactured as Example 1 was annealed to measure the surface roughness Ra before and after the annealing process. The results are shown in Table 3 below.

Figure 112009066468025-pct00003
Figure 112009066468025-pct00003

상기 표 3 으로부터 명확한 바와 같이, 실시예 1 로서 제조한 범프 형성 IC 에 대하여 어닐링 처리를 실시한 경우에는, 어닐링 처리 후에 있어서의 범프의 표면 거칠기 Ra 가 0.0179 ㎛ 로 되고, 예를 들어 정상부를 절삭함으로써 평활하게 한 범프에 대하여 어닐링 처리를 실시하는 등의 종래의 수법과는 상이하게, 0.05 ㎛ 이하의 값으로 유지되어 있다.As is clear from Table 3, when the bump forming IC manufactured as Example 1 is subjected to the annealing treatment, the surface roughness Ra of the bumps after the annealing treatment is 0.0179 占 퐉, and, for example, Which is different from the conventional method such as the annealing process for the bumps formed on the surface of the substrate.

이것은 이하의 이유에 의한 것이다. 즉, 실시예 1 로서 제조한 범프는, 금 도금액의 입자 덩어리 (결정립) 가 쌓여서 형성된 것인데, 정상부를 평활하게 하기 위해, 결정립이 작아지도록 결정 상태를 제어한 금 도금액을 사용하고 있다. 구체적으로는, 실시예 1 로서 제조한 범프에 있어서는, 어닐링 처리 전에 있어서의 범프 단면의 결정립의 모습을 측정하면, 도 7 중 좌측의 분포도에 나타내는 바와 같이, 극히 미세한 결정립이 집합되어 있고, 도 7 중 우측에 나타내는 바와 같이, 그 평균 입경이 0.08 ㎛ 였다. 즉, 실시예 1 로서 제조한 범프는, 어닐링 처리 전에 있어서의 평균 입경이 0.1 ㎛ 이하로 작은 결정립이 극히 미세하게 쌓여서 형성된 것이고, 이로써, 어닐링 처리를 실시해도 도금액의 결정립이 커지지 않고, 어닐링 처리 전후에 걸쳐서 결정립의 크기 변화를 억제할 수 있어, 범프의 표면 거칠기 Ra 가 0.05 ㎛ 이하로 유지되는 것이다.This is due to the following reasons. That is, the bumps manufactured in Example 1 are formed by accumulating grain aggregates (crystal grains) of a gold plating solution. In order to smooth the top portion, a gold plating solution is used in which crystal states are controlled so as to decrease the crystal grains. Specifically, in the bumps manufactured in Example 1, when the shape of the crystal grains in the bump cross section before the annealing treatment is measured, as shown in the distribution chart on the left side in Fig. 7, extremely fine crystal grains are gathered, As shown in the right side of the figure, the average particle size was 0.08 mu m. That is, the bumps manufactured in Example 1 are formed by extremely finely accumulating crystal grains having an average grain size of 0.1 占 퐉 or less before the annealing process. Thus, even if the annealing process is carried out, the crystal grains of the plating solution do not become large before and after the annealing process And the surface roughness Ra of the bumps is maintained at 0.05 mu m or less.

이와 같이, 본 발명은, 어닐링 처리 전후에 걸쳐서 범프의 표면 거칠기 Ra 를 0.05 ㎛ 이하로 할 수 있고, 이방성 도전막에 포함되는 도전성 입자의 입자경이 작은 경우에도 이것을 균일하게 찌부러뜨릴 수 있어, 제조되는 전기적 접속체에 있어서 양호한 도통 특성을 얻을 수 있음이 밝혀졌다.As described above, according to the present invention, the surface roughness Ra of the bumps can be made 0.05 mu m or less before and after the annealing process, and even when the particle diameter of the conductive particles contained in the anisotropic conductive film is small, this can be uniformly crushed It has been found that good conduction characteristics can be obtained in the electrical connecting body.

Claims (11)

제 1 전자 부재와 제 2 전자 부재가 이방성 도전막을 개재하여 전기적으로 접속되어 이루어지는 전기적 접속체로서,An electrical connecting body in which a first electronic member and a second electronic member are electrically connected via an anisotropic conductive film, 어느 일방의 전자 부재에는 평균 입경이 0.1 ㎛ 이하로 작은 결정립이 미세하게 쌓여서 돌기 전극이 형성되어 있고,Crystal grains having an average grain size of 0.1 占 퐉 or less are finely deposited on the electron members of either one of them to form protruding electrodes, 상기 돌기 전극의 정상부는, 금 도금에 의해 형성되고,The top of the protruding electrode is formed by gold plating, 상기 금 도금 조성은 a) 금 화합물, b) 전도염ㆍ완충제, c) 결정 성장제, d) 유기 광택제이고,The gold plating composition is preferably a gold compound, b) a conductive salt / buffering agent, c) a crystal growth agent, d) a) 금 화합물은 아황산금염이나 시안화금연에서 선택되고,a) The gold compound is selected from a sulfite gold salt or cyanide cigarette, b) 전도염ㆍ완충제는 아황산염, 인산염, 시트르산염, 옥살산염, 황산염, 붕산염, 염산염, 아민염, 킬레이트제에서 선택되고,b) Conducting salts and buffering agents are selected from sulfites, phosphates, citrates, oxalates, sulphates, borates, hydrochlorides, amine salts and chelating agents, c) 결정 성장제는 Tl, Pb, As, Bi, Co, Ni, Fe, Sb 에서 선택되고,c) the crystal growth agent is selected from Tl, Pb, As, Bi, Co, Ni, Fe, and Sb, d) 유기 광택제는 에톡시화폴리에틸렌이민 (PEIE), 폴리알킬이민 (PAI), 폴리에틸렌이민 (PEI) 에서 선택되며,d) The organic brightener is selected from ethoxylated polyethyleneimine (PEIE), polyalkylimine (PAI), polyethyleneimine (PEI) 상기 돌기 전극의 정상부는, 어닐링 처리 후의 표면 거칠기 Ra 가 0.05 ㎛ 이하인 평탄면으로 되어 있는 것을 특징으로 하는 전기적 접속체.And the top of the protruding electrode is a flat surface having a surface roughness Ra of 0.05 m or less after the annealing process. 제 1 항에 있어서,The method according to claim 1, 상기 돌기 전극의 정상부는, 어닐링 처리 후의 표면 거칠기 Ra 가 0.02 ㎛ 이하인 평탄면으로 되어 있는 것을 특징으로 하는 전기적 접속체.Wherein a top portion of the protruding electrode is a flat surface having a surface roughness Ra of 0.02 占 퐉 or less after the annealing process. 삭제delete 제 1 항 또는 제 2 항에 있어서,3. The method according to claim 1 or 2, 상기 이방성 도전막에 포함되는 도전성 입자의 평균 입경이 4 ㎛ 이하인 것을 특징으로 하는 전기적 접속체.Wherein the average particle diameter of the conductive particles contained in the anisotropic conductive film is 4 占 퐉 or less. 제 4 항에 있어서,5. The method of claim 4, 상기 도전성 입자는, 수지 입자를 심재 (芯材) 로 하고, 그 표면에 도전층이 형성되어 있는 것을 특징으로 하는 전기적 접속체.Wherein the conductive particles comprise a resin particle as a core material and a conductive layer formed on the surface thereof. 제 5 항에 있어서,6. The method of claim 5, 상기 수지 입자는, 20 % 압축 변형시의 압축 경도가 100 ∼ 1000 kgf/㎟ 인 것을 특징으로 하는 전기적 접속체.Wherein said resin particles have a compression hardness of 20 to 100 kgf / mm < 2 > at the time of compressive deformation at 20%. 제 1 전자 부재와 제 2 전자 부재의 어느 일방에, 평균 입경이 0.1 ㎛ 이하로 작은 결정립이 미세하게 쌓여서 금 도금에 의해 정상부의 표면 거칠기 Ra 가 0.05 ㎛ 이하인 평탄면으로 된 돌기 전극을 형성하는 공정과,A step of forming protruding electrodes having a flat surface with a surface roughness Ra of 0.05 mu m or less by gold plating with fine grains having an average particle diameter of 0.1 mu m or less finely deposited on either one of the first and second electronic members and, 상기 제 1 전자 부재와 상기 제 2 전자 부재 사이에 이방성 도전막을 개재시키는 공정과,Interposing an anisotropic conductive film between the first electronic member and the second electronic member; 가압에 의해 상기 돌기 전극과 대향하는 이방성 도전막의 도전성 입자를 눌러 찌부러뜨려, 상기 제 1 전자 부재와 상기 제 2 전자 부재를 전기적으로 접속하는 공정을 구비하고,Pressing and pressing the conductive particles of the anisotropic conductive film opposed to the protruded electrodes by pressing to electrically connect the first electronic member and the second electronic member, 상기 금 도금 조성은 a) 금 화합물, b) 전도염ㆍ완충제, c) 결정 성장제, d) 유기 광택제이고,The gold plating composition is preferably a gold compound, b) a conductive salt / buffering agent, c) a crystal growth agent, d) a) 금 화합물은 아황산금염이나 시안화금연에서 선택되고,a) The gold compound is selected from a sulfite gold salt or cyanide cigarette, b) 전도염ㆍ완충제는 아황산염, 인산염, 시트르산염, 옥살산염, 황산염, 붕산염, 염산염, 아민염, 킬레이트제에서 선택되고,b) Conducting salts and buffering agents are selected from sulfites, phosphates, citrates, oxalates, sulphates, borates, hydrochlorides, amine salts and chelating agents, c) 결정 성장제는 Tl, Pb, As, Bi, Co, Ni, Fe, Sb 에서 선택되고,c) the crystal growth agent is selected from Tl, Pb, As, Bi, Co, Ni, Fe, and Sb, d) 유기 광택제는 에톡시화폴리에틸렌이민 (PEIE), 폴리알킬이민 (PAI), 폴리에틸렌이민 (PEI) 에서 선택되며,d) The organic brightener is selected from ethoxylated polyethyleneimine (PEIE), polyalkylimine (PAI), polyethyleneimine (PEI) 상기 돌기 전극을 형성하는 공정이 어닐링 처리를 포함하고, 어닐링 처리후의 표면 거칠기 Ra 가 0.05 ㎛ 이하인 평탄면으로 되는 것을 특징으로 하는 전기적 접속체의 제조 방법.Wherein the step of forming the protruding electrode includes an annealing treatment and a flat surface having a surface roughness Ra of 0.05 mu m or less after the annealing treatment. 제 7 항에 있어서,8. The method of claim 7, 상기 돌기 전극의 정상부는, 상기 표면 거칠기 Ra 가 0.02 ㎛ 이하인 평탄면으로 되는 것을 특징으로 하는 전기적 접속체의 제조 방법.Wherein the top of the protruding electrode is a flat surface having a surface roughness Ra of 0.02 占 퐉 or less. 삭제delete 제 7 항 또는 제 8 항에 있어서,9. The method according to claim 7 or 8, 상기 돌기 전극의 정상부는, 어닐링 처리 후의 상기 표면 거칠기 Ra 가 0.02 ㎛ 이하인 평탄면으로 되는 것을 특징으로 하는 전기적 접속체의 제조 방법.Wherein a top portion of the protruding electrode is a flat surface having a surface roughness Ra of 0.02 占 퐉 or less after the annealing process. 제 7 항 또는 제 8 항에 있어서,9. The method according to claim 7 or 8, 상기 돌기 전극을 형성할 때에 사용되는 도금액의 결정립은, 어닐링 처리 전에 있어서의 평균 입경이 0.1 ㎛ 이하인 것을 특징으로 하는 전기적 접속체의 제조 방법.Wherein the crystal grains of the plating liquid used for forming the protruding electrodes have an average particle diameter of 0.1 mu m or less before the annealing treatment.
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