TWI443762B - Electrical connector and method of manufacturing the same - Google Patents

Electrical connector and method of manufacturing the same Download PDF

Info

Publication number
TWI443762B
TWI443762B TW097141683A TW97141683A TWI443762B TW I443762 B TWI443762 B TW I443762B TW 097141683 A TW097141683 A TW 097141683A TW 97141683 A TW97141683 A TW 97141683A TW I443762 B TWI443762 B TW I443762B
Authority
TW
Taiwan
Prior art keywords
electrical connector
bump
conductive particles
electrode
electronic component
Prior art date
Application number
TW097141683A
Other languages
Chinese (zh)
Other versions
TW200935531A (en
Inventor
Misao Konishi
Yoshito Tanaka
Shobu Saito
Shinya Kawahara
Etusko Ishikawa
Original Assignee
Sony Chemicals & Information Device Corp
Electroplating Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Chemicals & Information Device Corp, Electroplating Eng filed Critical Sony Chemicals & Information Device Corp
Publication of TW200935531A publication Critical patent/TW200935531A/en
Application granted granted Critical
Publication of TWI443762B publication Critical patent/TWI443762B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/8388—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01088—Radium [Ra]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)

Description

電性連接體及其製造方法Electrical connector and method of manufacturing same

本發明是有關於一種半導體元件或電子基板等電子零件業已彼此電性連接的電性連接體，且特別是有關於一種利用凸起電極(bump electrodes)及異向性導電膜(Anisotropic Conductive Film、ACF)進行電性連接之電性連接體。The present invention relates to an electrical connector in which an electronic component such as a semiconductor element or an electronic substrate has been electrically connected to each other, and more particularly to a bump electrode and an anisotropic conductive film (Anisotropic Conductive Film, ACF) An electrical connector that is electrically connected.

迄今，例如在將半導體元件等電子零件裝配(assembly)於線路基板時，係廣泛藉由線結合(wire bonding)來進行半導體元件之端子電極與線路基板之電極的電性連接。但是，這種籍線結合的連接，必須將一個一個電極間以線接合連接，連接步驟極其繁複，且有著難以應付隨高密度裝配的端子電極細微化、狹窄間距等的問題，故吾人期待可獲得改善。Heretofore, for example, when an electronic component such as a semiconductor element is assembled to a circuit board, electrical connection between the terminal electrode of the semiconductor element and the electrode of the wiring substrate is widely performed by wire bonding. However, such a connection of the bonding wires must be connected by wire bonding between the electrodes, and the connection step is extremely complicated, and it is difficult to cope with the problem of miniaturization and narrow pitch of the terminal electrodes assembled with high density, so I am expecting Get improved.

根據這種狀況，而有人提出將半導體元件以所謂倒裝狀態裝配於線路基板上的倒裝晶片裝配法。該倒裝晶片裝配法係在半導體元件的端子電極或線路基板的電極之任一邊形成稱為凸起(bump)的凸起電極，並使該凸起電極與另一側電極相向配置，如此總括地電性連接之方法。該凸起電極係以鍍Au、Cu或焊料(錫鉛合金)等所形成，其高度在數μm~數十μm左右。In light of this situation, a flip chip mounting method in which a semiconductor element is mounted on a wiring substrate in a so-called flip-chip state has been proposed. In the flip chip mounting method, a bump electrode called a bump is formed on one of the terminal electrodes of the semiconductor element or the electrode of the circuit substrate, and the bump electrode is disposed to face the other electrode, so that the total The method of geoelectric connection. The bump electrode is formed by plating Au, Cu or solder (tin-lead alloy) or the like, and has a height of about several μm to several tens of μm.

這種倒裝晶片裝配法中，基於提高連接可靠性之目的而使用異向性導電膜。異向性導電膜係將導電性粒子業已分散於作為接著劑功能的絕緣性樹脂中之物，將之夾入與凸起電極相對的電極間並加熱加壓，導電性粒子就會在電極間受壓潰散，而達到電性連接。在沒有凸起電極的部分，導電性粒子維持在分散於絕緣性樹脂中的狀態，而保有電性絕緣的狀態，因此僅具有凸起電極的部分會達到電性導通。In this flip chip mounting method, an anisotropic conductive film is used for the purpose of improving connection reliability. The anisotropic conductive film is one in which the conductive particles are dispersed in an insulating resin functioning as an adhesive, sandwiched between electrodes opposed to the bump electrodes, and heated and pressurized, and the conductive particles are interposed between the electrodes. The pressure is broken and the electrical connection is reached. In the portion where the bump electrode is not provided, the conductive particles are maintained in a state of being dispersed in the insulating resin, and the electrically insulating state is maintained. Therefore, only the portion having the bump electrode is electrically conductive.

依據這種使用異向性導電膜的倒裝晶片裝配法，可如上所述，在多數個電極間總括地電性連接，不需要如線結合般地將一個個電極間以線接合連接，且較容易因應隨高密度裝配的端子電極細微化、狹窄間距等。According to the flip chip mounting method using the anisotropic conductive film, as described above, the electrical connection is collectively connected between the plurality of electrodes, and it is not necessary to wire-bond the electrodes between the electrodes as in the case of wire bonding, and It is easier to make the terminal electrodes that are assembled with high density, such as fineness, narrow pitch, and the like.

在這種利用異向性導電膜的倒裝晶片裝配法中，為了確保電性連接的可靠性，必須提高凸起電極上的導電性粒子之捕捉性，於是從各方面著手進行研討。例如，一旦凸起電極的高度不均一，連接就會發生問題，因此又提出了使凸起電極高度均一化的技術(例如參考專利文獻1至專利文獻6)。In such a flip chip mounting method using an anisotropic conductive film, in order to ensure the reliability of electrical connection, it is necessary to improve the trapping property of the conductive particles on the bump electrodes, and various aspects have been studied. For example, once the height of the bump electrodes is not uniform, a problem occurs in connection, and thus a technique of uniformizing the height of the bump electrodes has been proposed (for example, refer to Patent Document 1 to Patent Document 6).

具體而言，專利文獻1中，揭示了一種在具有電極圖案的基板上裝配具有電極部的半導體元件的方法。尤其在該裝配方法中，係在半導體元件的電極部設置比半導體元件表面更凸出的導電性凸出部，在剛體表面將該凸出部暫時按壓，於基板或半導體元件之至少一邊塗布接著用樹脂，加壓該半導體元件與基板以使該凸出部與電極圖案接觸而接合之後，使該接著用樹脂硬化。Specifically, Patent Document 1 discloses a method of mounting a semiconductor element having an electrode portion on a substrate having an electrode pattern. In particular, in the mounting method, a conductive protruding portion that protrudes more than the surface of the semiconductor element is provided on the electrode portion of the semiconductor element, and the protruding portion is temporarily pressed on the surface of the rigid body to be applied to at least one side of the substrate or the semiconductor element. After the semiconductor element and the substrate are pressed with a resin so that the protruding portion comes into contact with the electrode pattern and joined, the adhesive resin is cured.

又，專利文獻2中，係揭示一種凸起的製法，其係一種形成凸起的方法，該凸起係使用在業已形成於基板表面的多數個電路與半導體元件的電極接合者，其特徵在於該凸起乃藉由加壓而使高度整齊劃一。Further, Patent Document 2 discloses a method of forming a bump which is a method of forming a bump which is used by an electrode of a plurality of circuits and semiconductor elements which have been formed on a surface of a substrate, and is characterized in that The projections are height-aligned by pressurization.

又，專利文獻3中，揭示一種附有凸起之基板的製造方法，係具有內部已充填導體之穿孔的陶瓷電路基板，至少研磨其凸起形成面，並在露出表面的穿孔導體上焊接金屬小片。Further, Patent Document 3 discloses a method of manufacturing a substrate with a bump, which is a ceramic circuit substrate having a through-hole filled with a conductor, at least grinding a convex forming surface thereof, and soldering a metal on the through-hole conductor of the exposed surface. Small piece.

甚且，專利文獻4中，揭示在具有結構為下層設置銀鍍層、同時其上層設置鎳鍍層、更於其上層設置金鍍層的引線表面，在與藉倒裝晶片接合法所搭載的半導體裝置之電極墊相向的部分，藉鍍金形成柱狀凸起電極，且從半導體裝配基板的上端方向籍平板按壓該凸起電極，使其與半導體裝置之電極墊形成接觸面的多數個凸起電極的表面一致而呈同一平面將之平坦化的技術。Further, Patent Document 4 discloses a lead surface having a structure in which a silver plating layer is provided on the lower layer, a nickel plating layer is provided on the upper layer, and a gold plating layer is provided on the upper layer, and the semiconductor device mounted on the flip chip bonding method is disclosed. a portion of the opposite surface of the electrode pad is formed by gold plating to form a columnar bump electrode, and the bump electrode is pressed from the upper end of the semiconductor package substrate to form a surface of a plurality of bump electrodes which form a contact surface with the electrode pad of the semiconductor device. A technique that flattens and flattens the same plane.

又，專利文獻5中，揭示一種技術，係以藉整合統一焊料凸起電極的高度來達到降低裝配不良、降低電性連接電阻且同時提高連接強度之目的，其係以接觸對焊料凸起電極進行電性特性檢查之後，將焊料凸起電極的至少頂部進行研磨處理的技術。Further, in Patent Document 5, a technique is disclosed in which the purpose of reducing the assembly failure, reducing the electrical connection resistance, and simultaneously improving the connection strength by integrating the height of the unified solder bump electrode is to contact the solder bump electrode. After performing the electrical property inspection, at least the top of the solder bump electrode is subjected to a rubbing treatment.

又，專利文獻6中，揭示一種以有效整合統一凸起高度為目的之技術，係在讓攝像機構對凸起的頂部聚焦，同時以切削機構此時的位置為原點，並以該原點為基準驅動切削機構以進行切削凸起之技術。Further, Patent Document 6 discloses a technique for effectively integrating the uniform projection height by focusing the imaging mechanism on the top of the projection while taking the position of the cutting mechanism as the origin, and using the origin A technique of driving a cutting mechanism for cutting a projection for a reference.

又，除了這些專利文獻1至專利文獻6所記載的技術以外，其他還有在凸起電極與連接端子之間，於凸起電極形成凹凸以求提高導電性粒子的捕捉性之嘗試(例如參考專利文獻7到專利文獻10等)。In addition to the techniques described in Patent Literatures 1 to 6, there are other attempts to form irregularities between the bump electrodes and the connection terminals to improve the trapping properties of the conductive particles (for example, refer to Patent Document 7 to Patent Document 10, etc.).

例如，在專利文獻7中，揭示一種液晶顯示裝置，係由連接液晶晶胞之電極與柔性基板之電極而成者，其中該柔性基板之電極具有業已粗面化之表面。For example, Patent Document 7 discloses a liquid crystal display device which is formed by connecting an electrode of a liquid crystal cell and an electrode of a flexible substrate, wherein the electrode of the flexible substrate has a surface which has been roughened.

又，專利文獻8中，揭示一種技術，係在備有具磨料(abrasive)之研磨片的平面高台上，以倒裝設置半導體裝置(IC基板)以使凸起抵接於研磨片，一面將半導體裝置按壓於平面高台，一面在垂直於按壓方向的平面內以超音波振動平面高台，藉此在凸起的前端面形成凹凸面。Further, Patent Document 8 discloses a technique in which a semiconductor device (IC substrate) is flip-chip mounted on a flat platform provided with an abrasive polishing sheet so that the projection abuts against the polishing sheet. The semiconductor device is pressed against the plane-high table, and is elevated in a plane perpendicular to the pressing direction by an ultrasonic vibration plane, whereby an uneven surface is formed on the front end surface of the projection.

又，專利文獻9中，揭示一種半導體裝置的裝配方法，其包含：在半導體裝置的電極上形成金凸起之步驟；在電路基板上貼附異向性導電膜之步驟；由比金凸起硬的材料構成且形成有比異向性導電膜之導電粒子之粒徑更小的凹凸的按壓用基板，將該按壓用基板按壓於半導體裝置的金凸起之前端面，藉此在金凸起之前端面形成凹凸部之步驟；以及在金凸起與電路基板的電極進行位置對準後，將半導體裝置按壓於已貼附有異向性導電膜之電路基板並加熱之步驟。Further, Patent Document 9 discloses a method of assembling a semiconductor device, comprising: a step of forming a gold bump on an electrode of a semiconductor device; a step of attaching an anisotropic conductive film on the circuit substrate; and being harder than a gold bump The material for forming a pressing substrate having irregularities smaller than the particle diameter of the conductive particles of the anisotropic conductive film, and pressing the pressing substrate against the front end surface of the gold bump of the semiconductor device, thereby before the gold bump The step of forming the uneven portion on the end surface; and after the gold bump is aligned with the electrode of the circuit board, the semiconductor device is pressed against the circuit substrate to which the anisotropic conductive film is attached and heated.

甚且，專利文獻10中，揭示一種技術，係在形成凸起電極之際，在配線電極上預先設置多數個由鈍化保護(passivation)膜構成的錐狀或梯形狀之凸部，在該狀態下堆積凸起底層金屬層，再於其上藉電鍍生長形成金電極而作成凸起電極的技術。藉此，對應於配線電極上設置的凹凸部，而在凸起電極的電極表面上形成凹凸部。Further, Patent Document 10 discloses a technique in which a plurality of tapered or trapezoidal convex portions composed of a passivation film are provided in advance on a wiring electrode when a bump electrode is formed, in this state. A technique of depositing a raised underlying metal layer and then forming a gold electrode by electroplating to form a bump electrode. Thereby, the uneven portion is formed on the electrode surface of the bump electrode in accordance with the uneven portion provided on the wiring electrode.

專利文獻1：日本特開平1-278034號公報Patent Document 1: Japanese Patent Laid-Open No. 1-278034

專利文獻2：日本特開平1-295433號公報Patent Document 2: Japanese Patent Laid-Open No. 1-295433

專利文獻3：日本特開平4-33395號公報Patent Document 3: Japanese Patent Laid-Open No. 4-33395

專利文獻4：日本特開平5-291262號公報Patent Document 4: Japanese Patent Laid-Open No. Hei 5-291262

專利文獻5：日本特開2000-114313號公報Patent Document 5: Japanese Laid-Open Patent Publication No. 2000-114313

專利文獻6：日本特開2006-324397號公報Patent Document 6: Japanese Laid-Open Patent Publication No. 2006-324397

專利文獻7：日本實開昭63-174328號公報Patent Document 7: Japanese Unexamined Publication No. SHO63-174328

專利文獻8：日本特開平6-283537號公報Patent Document 8: Japanese Patent Laid-Open No. Hei 6-283537

專利文獻9：日本特開平11-16946號公報Patent Document 9: Japanese Patent Laid-Open No. 11-16946

專利文獻10：日本特開2004-14778號公報Patent Document 10: Japanese Patent Laid-Open Publication No. 2004-14778

然而，前述用於倒裝晶片裝配的異向性導電膜中，導電性粒子的粒徑通常在5μm~10μm的範圍，而為了對應近年的微距(fine pitch)要求，故尋求減少導電性粒子的比例、或者縮小導電性粒子的粒子徑。例如，若導電性粒子的比例多、或導電性粒子的粒徑大時，在微距的倒裝晶片裝配上，導電性粒子會阻塞在凸起電極間，造成發生電性短路(short)的問題。However, in the above anisotropic conductive film for flip chip mounting, the particle diameter of the conductive particles is usually in the range of 5 μm to 10 μm, and in order to meet the requirements of fine pitch in recent years, it is sought to reduce the conductive particles. The ratio or the particle diameter of the conductive particles is reduced. For example, when the ratio of the conductive particles is large or the particle diameter of the conductive particles is large, in the flip chip mounting of the macro, the conductive particles are clogged between the bump electrodes, causing an electrical short circuit. problem.

這種情況下，由於減少導電性粒子的比例會直接牽連倒導電性粒子的捕捉性，因此縮小導電性粒子的粒子徑是較為妥當的。若縮小導電性粒子的粒子徑，則凸起電極間之間隙的導電性粒子會呈現在絕緣性樹脂(接著劑)中分散的狀態，可迴避凸起電極間因導電性粒子彼此接觸造成的短路問題。In this case, since reducing the ratio of the conductive particles directly affects the trapping property of the inverted conductive particles, it is appropriate to reduce the particle diameter of the conductive particles. When the particle diameter of the conductive particles is reduced, the conductive particles in the gap between the bump electrodes are dispersed in the insulating resin (adhesive), and the short circuit caused by the contact of the conductive particles between the bump electrodes can be avoided. problem.

然而，在縮小導電性粒子之粒子徑的情況下，發生了新的問題，即因凸起電極的高度散亂不整齊或裝配精良度等，導電性粒子無法均勻潰散，而容易發生導通電阻不穩定的現象。各凸起電極的表面高度有±2μm左右的散亂(習知的凸起電極表面粗糙度Ra為0.3μm左右)，若例如導電性粒子的平均粒子徑為4μm以下時，就難以均勻按壓潰散。However, in the case where the particle diameter of the conductive particles is reduced, a new problem arises in that the conductive particles are not uniformly collapsed due to the disordered height of the bump electrodes or the assembly precision, and the on-resistance is liable to occur. Stable phenomenon. The surface height of each of the bump electrodes is about ±2 μm (the conventional bump electrode surface roughness Ra is about 0.3 μm), and when the average particle diameter of the conductive particles is 4 μm or less, it is difficult to uniformly press and collapse. .

考量這種導電性粒子的小徑化時，如前述專利文獻1至專利文獻6所記載之使凸起電極的高度均勻劃一的技術並不足以應付。該等專利文獻1至專利文獻6所記載的技術中，雖可縮小凸起電極間的高度散亂，卻無法消除凸起電極頂部(前端平面部)的表面粗糙所引起的高度散亂，使得凸起電極頂部存在有因表面粗糙所造成的散亂。因此，一旦導電性粒子的粒子徑變小時，凸起電極上的導電性粒子無法均勻潰散的問題仍未解決。When the diameter of the conductive particles is reduced, the technique of uniformly aligning the heights of the bump electrodes as described in Patent Documents 1 to 6 is not sufficient. In the techniques described in Patent Documents 1 to 6, the height disorder between the bump electrodes can be reduced, but the height disorder caused by the surface roughness of the top of the bump electrode (front end plane portion) cannot be eliminated. There is scattering at the top of the bump electrode due to surface roughness. Therefore, once the particle diameter of the conductive particles becomes small, the problem that the conductive particles on the bump electrodes cannot be uniformly collapsed remains unsolved.

另一方面，如前述專利文獻7至專利文獻10所記載的技術，於凸起電極形成凹凸以提高導電性粒子捕捉性的技術，其方向是加大凸起電極表面粗糙度，這種情況下，由於已捕捉的導電性粒子進入凹凸內而無法均勻潰散，因此難以對應導電性粒子的小徑化。On the other hand, as described in the above-described patent documents 7 to 10, the technique of forming irregularities on the bump electrodes to improve the trapping property of the conductive particles is to increase the surface roughness of the bump electrodes. Since the trapped conductive particles enter the unevenness and cannot be uniformly collapsed, it is difficult to reduce the diameter of the conductive particles.

又，裝配半導體元件等時，通常基於調整凸起電極的硬度使其均勻化之目的，會進行退火(annealing)處理。然而，凸起電極雖可藉切削頂部等處理來降低表面粗糙度，但卻有因進行退火處理而導致表面粗糙度大幅增加的問題。Further, when a semiconductor element or the like is mounted, an annealing process is usually performed for the purpose of uniformizing the hardness of the bump electrode. However, although the bump electrode can be treated by cutting the top or the like to reduce the surface roughness, there is a problem that the surface roughness is greatly increased by the annealing treatment.

本發明係有關一種電性連接體及其製造方法，係即使異向性導電膜中所含之導電性粒子其粒子徑很小，仍可均勻潰散，且無論有無進行退火處理，皆可獲得良好的導通特性者。The present invention relates to an electrical connector and a method of manufacturing the same, which is characterized in that even if the conductive particles contained in the anisotropic conductive film have a small particle diameter, they can be uniformly collapsed, and can be obtained with or without annealing treatment. The conduction characteristics of the person.

本發明人為了達成前述目的，經長期反覆專精研討，結果發現，在凸起電極表面形成凹凸之情況下，雖可能提升導電性粒子的捕捉性，然而因凹凸使得壓力無法充分傳到位於凸起電極周圍之部分的導電性粒子，凸起電極上的導電性粒子無法均勻潰散，相反的，藉由使凸起電極表面格外平滑，在導電性粒子的粒徑很小的情況下，也可因潰散而使有效作用的導電性粒子之比例提升，捕捉性也幾乎沒有問題。In order to achieve the above object, the present inventors have studied and studied after a long period of time, and found that, in the case where irregularities are formed on the surface of the bump electrode, the trapping property of the conductive particles may be improved, but the pressure may not be sufficiently transmitted to the convex portion due to the unevenness. The conductive particles on the portion around the electrode do not uniformly collapse the conductive particles on the bump electrode. Conversely, when the surface of the bump electrode is exceptionally smooth, the particle size of the conductive particles may be small. The proportion of the conductive particles that are effective due to the collapse is increased, and the trapping property is almost no problem.

本發明係依據前述發現而完成者，亦即，根據本發明之一方面，提出一種電性連接體，係第一電子零件與第二電子零件隔著異向性導電膜而電性連接者，其係在任一側之電子零件上形成有凸起電極，該凸起電極之頂部係作成在退火處理後之表面粗糙度Ra為0.05μm以下之平坦面。The present invention has been completed in accordance with the foregoing findings, that is, in accordance with one aspect of the present invention, an electrical connector is provided, wherein the first electronic component and the second electronic component are electrically connected via an anisotropic conductive film, A bump electrode is formed on the electronic component on either side, and the top of the bump electrode is formed into a flat surface having a surface roughness Ra of 0.05 μm or less after the annealing treatment.

又，根據本發明之另一方面，提出一種電性連接體的製造方法，包含：在第一電子零件與第二電子零件之任一側，藉電鍍形成頂部表面粗糙度Ra作成0.05μm以下之平坦面的凸起電極之步驟；使異向性導電膜介在於該第一電子零件與該第二電子零件之間的步驟；以及藉按壓將與該凸起電極相向的異向性導電膜之導電性粒子受壓潰散，使該第一電子零件與該第二電子零件電性連接之步驟。Moreover, according to another aspect of the present invention, a method of manufacturing an electrical connector includes: forming a top surface roughness Ra by plating on either side of a first electronic component and a second electronic component to be 0.05 μm or less a step of flattening the raised electrode; a step of interposing the anisotropic conductive film between the first electronic component and the second electronic component; and pressing the anisotropic conductive film to face the bump electrode The step of electrically connecting the conductive particles to the first electronic component and the second electronic component.

當使用分散有小粒徑之導電性粒子的異向性導電膜之情況時，若凸起電極的表面粗糙度偏大，表面形成有凹凸時，異向性導電膜夾入第一電子零件與第二電子零件之間，在與前述凸起電極相向的電極之間按壓前述異向性導電膜之際，壓力將無法傳到跑入凸起電極例如表面凹部內的導電性粒子，無法將之充分按壓潰散。一旦導電性粒子沒有充分潰散，電性連接面積等不足，將難以確保導通可靠性。When an anisotropic conductive film in which conductive particles having a small particle diameter are dispersed is used, if the surface roughness of the bump electrode is excessively large and irregularities are formed on the surface, the anisotropic conductive film is sandwiched between the first electronic component and When the anisotropic conductive film is pressed between the electrodes facing the bump electrodes between the second electronic components, the pressure cannot be transmitted to the conductive particles that run into the bump electrodes, for example, the surface recesses, and cannot be used. Fully press the collapse. When the conductive particles are not sufficiently broken, the electrical connection area and the like are insufficient, and it is difficult to ensure the conduction reliability.

相對於此，本發明之一實施例中，係令凸起電極的表面粗糙度Ra在0.05μm以下，呈現極為平滑之狀態。尤其本發明中，即使在退火處理後表面粗糙度Ra仍在0.05μm以下，無論有無進行退火處理，凸起電極頂部皆可維持在極其平滑的狀態。因此，即使導電性粒子其粒徑很小，仍可均勻施加壓力，實現均勻的粒子變形。On the other hand, in one embodiment of the present invention, the surface roughness Ra of the bump electrode is set to be 0.05 μm or less, and the state is extremely smooth. In particular, in the present invention, even if the surface roughness Ra is 0.05 μm or less after the annealing treatment, the top of the bump electrode can be maintained in an extremely smooth state with or without annealing treatment. Therefore, even if the conductive particles have a small particle diameter, pressure can be uniformly applied to achieve uniform particle deformation.

根據本發明，即使在異向性導電膜中所含的導電性粒子之粒子徑很小的情況下，仍可將之均勻潰散，可獲得良好的導通特性。因此，依據本發明，可實現導通可靠性優異的電性連接體。According to the present invention, even when the particle diameter of the conductive particles contained in the anisotropic conductive film is small, it can be uniformly collapsed, and good conduction characteristics can be obtained. Therefore, according to the present invention, an electrical connector excellent in conduction reliability can be realized.

為讓本發明之上述內容能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:

第1圖是顯示電性連接體之一個例子。電性連接體乃是例如將半導體元件等電子零件電性地或機械性地連接固定於配線基板等電子零件者。在此，是舉第一電子零件為半導體元件(IC晶片)，第二電子零件為配線基板之情況為例子進行說明。Fig. 1 is an example showing an electrical connector. The electrical connector is, for example, an electronic component such as a semiconductor element that is electrically or mechanically connected and fixed to an electronic component such as a wiring board. Here, a case where the first electronic component is a semiconductor element (IC wafer) and the second electronic component is a wiring substrate will be described as an example.

第1圖中，屬第一電子零件的半導體元件1上形成有作為連接端子的凸起電極2(以下稱「凸起(bump)」)。另一方面，屬第二電子零件的配線基板3上，電極4乃形成在與凸起2相向的位置。半導體元件1與配線基板3之間，異向性導電膜5介於其間，而在凸起2與電極4相向的部分，該異向性導電膜5中所含的導電性粒子6受壓潰散，以達到電性導通。In the first embodiment, a bump electrode 2 (hereinafter referred to as "bump") as a connection terminal is formed on the semiconductor element 1 belonging to the first electronic component. On the other hand, on the wiring substrate 3 which is the second electronic component, the electrode 4 is formed at a position facing the bump 2. Between the semiconductor element 1 and the wiring substrate 3, the anisotropic conductive film 5 is interposed therebetween, and in the portion where the bump 2 and the electrode 4 face, the conductive particles 6 contained in the anisotropic conductive film 5 are crushed and broken. To achieve electrical conduction.

凸起2是藉由例如Au、Cu或焊料(錫鉛合金)等導電性金屬所形成，其高度在5μm至50μm左右。凸起2可藉由電鍍等形成，例如僅表面進行鍍金。凸起2係如後所述尋求表面平滑性，以該觀點視之，以鍍金為佳。The bump 2 is formed of a conductive metal such as Au, Cu or solder (tin-lead alloy), and has a height of about 5 μm to 50 μm. The bump 2 can be formed by plating or the like, for example, only the surface is plated with gold. The bump 2 is intended to have surface smoothness as described later, and in view of this, gold plating is preferred.

在這種結構的電性連接體中，形成於半導體元件1的凸起2之表面粗糙度極為重要。當凸起2的表面粗糙度偏大時，即如第2圖模式性所示，局部的導電性粒子6會進入凸起2的連接面凹部2a內，即使加壓也不會受壓因而呈未潰散狀態，容易造成導通電阻不穩定的現象。相對的，凸起2的連接面若很平坦，則被捕捉到凸起2與電極4之間的所有導電性粒子6皆均勻受壓潰散，可穩定地確保導通可靠性。In the electrical connector of such a structure, the surface roughness of the bumps 2 formed on the semiconductor element 1 is extremely important. When the surface roughness of the protrusion 2 is excessively large, that is, as schematically shown in Fig. 2, the local conductive particles 6 enter the concave portion 2a of the joint surface of the projection 2, and are not pressed even if pressurized. If it is not broken, it is easy to cause the on-resistance to be unstable. On the other hand, if the connection surface of the bump 2 is flat, all the conductive particles 6 caught between the bump 2 and the electrode 4 are uniformly crushed and broken, and the conduction reliability can be stably ensured.

根據該觀點，本發明中，係使凸起2的表面粗糙度以中心線平均粗糙度Ra為0.05μm以下。電性連接體中，藉由使該平均粗糙度Ra在0.05μm以下，即使在例如導電性粒子6之平均粒徑在4μm以下這種情況，仍可實現均勻的粒子變形。又，凸起2的平均粗糙度Ra最好考量導電性粒子6的平均粒子徑來設定，尤其最佳為0.02μm以下。From this point of view, in the present invention, the surface roughness of the projections 2 is set to have a center line average roughness Ra of 0.05 μm or less. In the electrical connector, by setting the average roughness Ra to 0.05 μm or less, even when the average particle diameter of the conductive particles 6 is 4 μm or less, uniform particle deformation can be achieved. Further, the average roughness Ra of the bumps 2 is preferably set in consideration of the average particle diameter of the conductive particles 6, and particularly preferably 0.02 μm or less.

凸起2的平均粗糙度Ra可藉由例如Tencor社製造的表面輪廓量測儀(SURFACE PROFILER)等接觸式測定器來測定。The average roughness Ra of the projections 2 can be measured by a contact type measuring device such as a surface profile measuring instrument (SURFACE PROFILER) manufactured by Tencor.

在此，電性連接體中，後續步驟中進行退火處理的情況時，即使可暫時將退火處理前的表面粗糙度Ra形成在0.05μm以下，然而在退火處理後，通常表面粗糙度Ra會大幅增加。對此，依據本發明的電性連接體，在凸起2形成之際，藉由控制電鍍的結晶狀態，可在歷經退火處理前後，其表面粗糙度Ra仍保持在0.05μm以下，更佳者可保持在0.02μm以下。Here, in the case where the annealing treatment is performed in the subsequent step in the electrical connecting body, even if the surface roughness Ra before the annealing treatment can be temporarily formed to be 0.05 μm or less, the surface roughness Ra is usually large after the annealing treatment. increase. On the other hand, according to the electrical connector of the present invention, when the bump 2 is formed, by controlling the crystal state of the plating, the surface roughness Ra can be kept below 0.05 μm before and after the annealing treatment, and more preferably. It can be kept below 0.02μm.

又，除了表面粗糙度Ra以外，凸起2最好也可就其硬度進行適當設定。凸起2的硬度，可因應凸起2中使用的導電性材料種類、或例如形成電鍍之際的形成條件等來加以設計，而為了實現導電性粒子6的均勻粒子變形，最好是韋克斯硬度Hv為40~150。在電性連接體中，藉由將凸起2的韋克斯硬度Hv之值設定在該範圍內，在將導電性粒子6按壓潰散之際，加壓力可適正地傳到導電性粒子6，而作到均勻按壓潰散。Further, in addition to the surface roughness Ra, it is preferable that the projections 2 are appropriately set in terms of their hardness. The hardness of the bumps 2 can be designed in accordance with the type of the conductive material used in the bumps 2 or, for example, the formation conditions at the time of plating, and in order to achieve uniform particle deformation of the conductive particles 6, it is preferable that Wake The hardness Hv is 40~150. In the electrical connector, by setting the value of the Wex hardness Hv of the bump 2 within this range, when the conductive particles 6 are pressed and broken, the pressing force can be appropriately transmitted to the conductive particles 6, And it is evenly pressed and broken.

另一方面，在電性連接體中，用以達成凸起2與電極4之間的電性連接及機械性固定的異向性導電膜5，係在絕緣性樹脂中分散有導電性粒子6之物。絕緣性樹脂可使用例如聚胺酯樹脂、聚酯樹脂、氯丁二烯等熱塑性之熱熔樹脂，或環氧樹脂等熱硬化性樹脂等。又，環氧樹脂可例舉如BPA型環氧樹脂、BPF型環氧樹脂、酚醛環氧樹脂、或橡膠或聚胺酯等各種改良環氧樹脂等，該等可單獨使用或混合兩種以上來使用。On the other hand, in the electrical connecting body, the anisotropic conductive film 5 for achieving electrical connection and mechanical fixation between the bump 2 and the electrode 4 is dispersed with conductive particles 6 in an insulating resin. Things. As the insulating resin, for example, a thermoplastic hot melt resin such as a polyurethane resin, a polyester resin or chloroprene, or a thermosetting resin such as an epoxy resin can be used. Further, the epoxy resin may, for example, be a BPA-type epoxy resin, a BPF-type epoxy resin, a novolac epoxy resin, or a modified epoxy resin such as a rubber or a polyurethane, and these may be used alone or in combination of two or more. .

又，亦可於異向性導電膜5中添加潛伏性硬化劑，進行加熱將硬化劑活性化。藉由在異向性導電膜5中添加潛伏性硬化劑，可賦予觸發反應性，在連接之際可藉加熱操作確實且迅速地使其硬化。這時，潛伏性硬化劑可使用咪唑系潛伏性硬化劑等，可舉出例如經表面處理而微膠囊化的商品名諾巴丘亞HX3741(HX3741)(旭化成社製)、商品名諾巴丘亞HX3921HP(HX3921HP)(旭化成社製)、商品名亞美丘亞PN-23(PN-23)(味之素社製)、商品名ACR哈德那H-3615(ACRH-3615)(ACR社製)等。Further, a latent curing agent may be added to the anisotropic conductive film 5, and heating may be performed to activate the curing agent. By adding a latent curing agent to the anisotropic conductive film 5, the triggering reactivity can be imparted, and when it is connected, it can be hardened reliably and rapidly by a heating operation. In this case, an imidazole-based latent curing agent or the like can be used as the latent curing agent, and for example, a product name Nobchuchia HX3741 which is microencapsulated by surface treatment can be mentioned. HX3741) (made by Asahi Kasei Corporation), trade name Nobachuya HX3921HP ( HX3921HP) (made by Asahi Kasei Corporation), trade name Yamei Chuya PN-23 ( PN-23) (Ajinomoto Co., Ltd.), trade name ACR Hadna H-3615 (ACR H-3615) (made by ACR), etc.

異向性導電膜5中所含的絕緣性樹脂一旦黏度偏高，無法充分將絕緣性樹脂從應使其導通的電極間排除，恐有導通可靠性降低之虞。而且，當異向性導電膜5中所含的絕緣性樹脂黏度變高時，為了將應連接的電極間之絕緣性樹脂充分排除，必須提高熱硬化時的加壓力，其朝導電性粒子6的凸起2或電極4的附近變強，而恐有裂痕等產生的疑慮。因此，絕緣性樹脂在異向性導電膜5的熱壓著溫度中之熔融黏度以在108 mPa‧s以下為佳，更以107 mPa‧s以下為佳。When the insulating resin contained in the anisotropic conductive film 5 has a high viscosity, the insulating resin cannot be sufficiently removed from between the electrodes to be electrically connected, and the conduction reliability may be lowered. Further, when the viscosity of the insulating resin contained in the anisotropic conductive film 5 is increased, in order to sufficiently exclude the insulating resin between the electrodes to be connected, it is necessary to increase the pressing force at the time of thermosetting, which is directed toward the conductive particles 6 The vicinity of the bump 2 or the electrode 4 becomes strong, and there is fear of cracks and the like. Therefore, the melt viscosity of the insulating resin in the heat-pressing temperature of the anisotropic conductive film 5 is preferably 10 8 mPa·s or less, more preferably 10 7 mPa·s or less.

另一方面，絕緣性樹脂在熱壓著時的熔融黏度一旦過低，導電性粒子6容易從應使其導通的電極間逃脫，在捕捉性這點上恐怕會產生問題。因此，絕緣性樹脂在異向性導電膜5的熱壓著溫度中之熔融黏度以在10mPa‧s以上為佳。On the other hand, when the melt viscosity of the insulating resin at the time of heat pressing is too low, the conductive particles 6 easily escape from between the electrodes to be electrically connected, and there is a fear that a problem may occur in the catching property. Therefore, the melt viscosity of the insulating resin in the heat-pressing temperature of the anisotropic conductive film 5 is preferably 10 mPa·s or more.

構成異向性導電膜5的導電性粒子6，可使用該種異向性導電膜中所使用之習知導電性粒子的任何一種。例如，可使用鎳、鐵、銅、鋁、錫、鉛、鉻、鈷、銀、金等各種金屬、或金屬合金的粒子、金屬氧化物、碳、石墨、玻璃或陶瓷、塑膠等粒子表面被覆金屬者、或於該等的粒子表面更被覆絕緣薄膜者等。Any of the conventional conductive particles used in the anisotropic conductive film can be used as the conductive particles 6 constituting the anisotropic conductive film 5. For example, various metals such as nickel, iron, copper, aluminum, tin, lead, chromium, cobalt, silver, gold, or particles of metal alloys, metal oxides, carbon, graphite, glass, ceramics, plastics, and the like may be coated. The metal or the surface of the particles is further covered with an insulating film or the like.

唯，有關本發明的電性連接體中，由於必須讓導電性粒子6在電極間受壓潰散，因此是以在樹脂粒子表面業已被覆金屬者為宜。這時，樹脂粒子以使用20%壓縮變形時的壓縮硬度在100~1000kgf/mm2 (1kgf/mm2 =9.80665MPa)之物為佳。樹脂粒子的20%壓縮變形時的K值若大於1000kgf/mm2，由於樹脂粒子未適度潰散，故無法吸收電極表面之高度的散亂不一，又，加壓之際需要高壓力，且同時可能因為導電性粒子6的反彈力變大而引起界面剝離等瑕疵。In the electrical connector of the present invention, since it is necessary to cause the conductive particles 6 to be crushed between the electrodes, it is preferable that the surface of the resin particles is coated with a metal. In this case, the resin particles preferably have a compression hardness of 20 to 1000 kgf/mm 2 (1 kgf/mm 2 = 9.80665 MPa) when 20% compression deformation is used. When the K value at the 20% compression deformation of the resin particles is more than 1000 kgf/mm 2 , since the resin particles are not properly collapsed, the height of the electrode surface cannot be absorbed, and high pressure is required at the time of pressurization, and at the same time, The repulsive force of the conductive particles 6 is increased to cause a flaw such as interfacial peeling.

要滿足這種要求的樹脂粒子，可舉出例如環氧樹脂、苯酚樹脂、丙烯酸樹脂、苯乙烯丙烯腈樹脂(AS)、苯胍胺樹脂(benzoguanamine resin)、二乙烯苯系樹脂、苯乙烯系樹脂等粒子。Examples of the resin particles satisfying such requirements include an epoxy resin, a phenol resin, an acrylic resin, a styrene acrylonitrile resin (AS), a benzoguanamine resin, a divinylbenzene resin, and a styrene system. Particles such as resin.

導電性粒子6的平均粒徑為任意，而使用平均粒徑4μm以下之導電性粒子6的情況時本發明效果很大。因此，導電性粒子6的平均粒徑適宜在1μm~4μm。又，隨著凸起電極的頂部之平坦化，導電性粒子之粒子徑的散亂可能會依據導電性粒子的硬度而受到影響。本發明之情況，導電性粒子的平均粒子徑在1±μm的範圍內最好包含了全粒子的90%以上。The average particle diameter of the conductive particles 6 is arbitrary, and when the conductive particles 6 having an average particle diameter of 4 μm or less are used, the effect of the present invention is large. Therefore, the average particle diameter of the conductive particles 6 is preferably from 1 μm to 4 μm. Further, as the top of the bump electrode is flattened, the scattering of the particle diameter of the conductive particles may be affected by the hardness of the conductive particles. In the case of the present invention, the average particle diameter of the conductive particles preferably contains 90% or more of the total particles in the range of 1 ± μm.

在具有如上結構的電性連接體中，異向性導電膜5中所含的導電性粒子6之粒子徑即使只有例如4μm以下屬於很小的情況，仍可將之均勻潰散，可獲得良好的導通特性。因此，可實現導通可靠性優異的電性連接體。In the electrical connector having the above structure, the particle diameter of the conductive particles 6 contained in the anisotropic conductive film 5 can be uniformly broken even if it is only small, for example, 4 μm or less, and good particle diameter can be obtained. Turn-on characteristics. Therefore, an electrical connector excellent in conduction reliability can be realized.

接著，說明上述電性連接體的製造方法。欲製作上述結構的電性連接體時，首先必須在半導體元件1的電極上形成凸起2。該凸起2係藉電鍍等方法形成，而為了使退火處理前後的表面粗糙度Ra在0.05μm，故以進行鍍金為佳，又，必須藉由選定電鍍條件來使所形成的凸起2之表面呈現平滑。Next, a method of manufacturing the above electrical connector will be described. In order to fabricate the electrical connector of the above structure, it is first necessary to form the bump 2 on the electrode of the semiconductor element 1. The bumps 2 are formed by plating or the like, and in order to make the surface roughness Ra before and after the annealing treatment to be 0.05 μm, it is preferable to perform gold plating, and it is necessary to form the bumps 2 by selecting plating conditions. The surface is smooth.

在此，為了於鍍金當中，控制結晶狀態，使所形成的凸起2表面呈現平滑，故使用以下的鍍金液。Here, in order to control the crystal state in the gold plating, the surface of the formed bump 2 is smoothed, so the following gold plating liquid is used.

鍍金液係以下列a)~d)等作為基本組成所構成。The gold plating liquid is composed of the following a) to d) and the like as a basic composition.

a)金化合物a) gold compound

b)導電鹽、緩衝劑b) Conductive salt, buffer

c)結晶生長劑c) Crystal growth agent

d)有機亮光劑d) organic brightener

金化合物有例如亞硫酸金鹽或氰化金鹽等。又，作為導電鹽、緩衝劑的有亞硫酸鹽、磷酸鹽、檸檬酸鹽、草酸鹽、硫酸鹽、硼酸鹽、氯酸鹽、胺鹽、螯合劑等。又，作為結晶生長劑的有Tl、Pb、As、Bi、Co、Ni、Fe、Sb等。甚且，作為有機亮光劑的可舉具有NH基的高分子，即乙氧基化聚乙烯亞胺(PEIE)、聚烷基亞胺(PAI)、聚乙烯亞胺(PEI)等。由這些液組成所得之鍍金，其析出物緻密且具有光澤，非常適合用於本發明中所形成的凸起2之表面平滑化。The gold compound is, for example, a gold salt of sulfite or a gold cyanide salt. Further, examples of the conductive salt and the buffer include sulfites, phosphates, citrates, oxalates, sulfates, borates, chlorates, amine salts, and chelating agents. Further, as the crystal growth agent, there are Tl, Pb, As, Bi, Co, Ni, Fe, Sb and the like. Further, examples of the organic brightening agent include a polymer having an NH group, that is, ethoxylated polyethyleneimine (PEIE), polyalkylimine (PAI), and polyethyleneimine (PEI). The gold plating obtained by the composition of these liquids has a dense precipitate and a luster, and is very suitable for surface smoothing of the projections 2 formed in the present invention.

在凸起2形成後，進行半導體元件1之凸起2與配線基板3之電極4間的連接，在時，係例如，在配線基板3的表面貼附異向性導電膜5，進行位置對準及暫時連接後，以既定之溫度與壓力進行熱壓著，藉此將導電性粒子6按壓潰散，使半導體元件1之凸起2與配線基板3之電極4電性連接，並在此狀態下使構成異向性導電膜5的絕緣性樹脂硬化。熱壓著時的溫度及壓力會依據所使用的異向性導電膜5之種類等而有所不同，不過較佳為例如溫度180℃~220℃，壓力30MPa~120MPa。After the bump 2 is formed, the bump 2 of the semiconductor element 1 and the electrode 4 of the wiring board 3 are connected. For example, the anisotropic conductive film 5 is attached to the surface of the wiring board 3 to perform positional alignment. After the temporary connection and the temporary connection, the conductive particles 6 are pressed and collapsed by a predetermined temperature and pressure, and the bumps 2 of the semiconductor element 1 are electrically connected to the electrodes 4 of the wiring substrate 3, and in this state. The insulating resin constituting the anisotropic conductive film 5 is cured. The temperature and pressure at the time of hot pressing vary depending on the type of the anisotropic conductive film 5 to be used, etc., but it is preferably, for example, a temperature of 180 ° C to 220 ° C and a pressure of 30 MPa to 120 MPa.

依據經過以上步驟，異向性導電膜5中所含的導電性粒子6之粒子徑即使很小，仍可將之均勻潰散，可在所製造的電性連接體中獲得良好的導通特性。According to the above steps, even if the particle diameter of the conductive particles 6 contained in the anisotropic conductive film 5 is small, it can be uniformly collapsed, and good conduction characteristics can be obtained in the manufactured electrical connector.

[實施例][Examples]

接著，就適用本發明之電性連接體之具體實施情況，根據實驗結果說明。Next, the specific implementation of the electrical connector of the present invention is applied, and the results are explained based on the experimental results.

第一實施例First embodiment

為了評估藉凸起的表面粗糙度Ra之相異所造成的導電性粒子之捕捉性及潰散狀態，隔著異向性導電膜將附凸起IC裝配於玻璃。異向性導電膜係於黏著劑成分中混合導電性粒子使其成為約300萬個/mm3 ，再將之薄膜化而形成。各成分的內容如下。In order to evaluate the trapping property and the collapse state of the conductive particles caused by the difference in surface roughness Ra of the bumps, the bump ICs are mounted on the glass via the anisotropic conductive film. The anisotropic conductive film is formed by mixing conductive particles with an adhesive component to be about 3,000,000/mm 3 and thinning the film. The contents of each component are as follows.

環氧樹脂：日本環氧樹脂株式會社(Japan Epoxy Resins Co.,Ltd)製，商品名EP828，30重量份Epoxy resin: manufactured by Japan Epoxy Resins Co., Ltd., trade name EP828, 30 parts by weight

苯氧樹脂(phenoxy resin)InChem社製，商品名PKHH，40重量份Phenoxy resin, manufactured by InChem, trade name PKHH, 40 parts by weight

環氧硬化劑：旭化成社製，商品名HX3941HP，30重量份Epoxy hardener: manufactured by Asahi Kasei Co., Ltd., trade name HX3941HP, 30 parts by weight

導電性粒子：鍍Ni/Au樹脂粒子Conductive particles: Ni/Au resin particles

又，使用平均粒徑4μm之導電性粒子與平均粒徑2μm之導電性粒子作為導電性粒子，製作兩種異向性導電膜(異向性導電膜A及異向性導電膜B)。Further, two kinds of anisotropic conductive films (an anisotropic conductive film A and an anisotropic conductive film B) were produced by using conductive particles having an average particle diameter of 4 μm and conductive particles having an average particle diameter of 2 μm as conductive particles.

附凸起IC之凸起係藉鍍金形成。該鍍金係使用日本電鍍技術株式會社(Electroplating Engineers of Japan,Ltd.)製造、商品名米庫龍法部Au310(Au310)作為鍍金液，在電鍍溫度50℃、電流密度0.4A/dm2 之條件下進行。結果所得之凸起的連接面，其表面粗糙度Ra為0.0105μm。裝配時的壓著條件設為到達溫度200℃、壓力40MPa、時間5秒。The bumps with the raised ICs are formed by gold plating. This gold plating is manufactured by Electroplating Engineers of Japan, Ltd., under the trade name Mikulong Law Department Au310 ( Au310) was carried out as a gold plating solution under the conditions of a plating temperature of 50 ° C and a current density of 0.4 A/dm 2 . As a result, the resulting bonded joint surface had a surface roughness Ra of 0.0105 μm. The pressing conditions at the time of assembly were set to a temperature of 200 ° C, a pressure of 40 MPa, and a time of 5 seconds.

第二實施例Second embodiment

變更實施例1的鍍金液及電鍍條件製作附凸起IC。鍍金係使用日本電鍍技術株式會社(Electroplating Engineers of Japan,Ltd.)製造、商品名紐特羅涅克斯240(240)作為鍍金液，在電鍍溫度65℃、電流密度0.5A/dm2之條件下進行。該結果所得之凸起的連接面，其表面粗糙度Ra為0.004μm。其他係在與實施例1相同的條件下，隔著異向性導電膜將附凸起IC裝配於玻璃。The gold plating liquid of Example 1 and the plating conditions were changed to produce a bump IC. The gold plating system is manufactured by Electroplating Engineers of Japan, Ltd. under the trade name Newtrones 240 ( 240) The gold plating solution was carried out under the conditions of a plating temperature of 65 ° C and a current density of 0.5 A/dm 2 . The resulting joint face obtained by this result had a surface roughness Ra of 0.004 μm. Otherly, under the same conditions as in Example 1, the bump IC was attached to the glass via the anisotropic conductive film.

(比較例1)(Comparative Example 1)

變更實施例1及實施例2的鍍金液及電鍍條件製作附凸起IC。鍍金係使用日本電鍍技術株式會社(Electroplating Engineers of Japan,Ltd.)製造、商品名米庫龍法部Au100(Au100)作為鍍金液，在電鍍溫度60℃、電流密度0.5A/dm2 之條件下進行。該結果所得之凸起的連接面，其表面粗糙度Ra為0.298μm。其他係在與實施例1相同的條件下，隔著異向性導電膜將附凸起IC裝配於玻璃。The gold plating liquid of Example 1 and Example 2 and the plating conditions were changed to produce a bump IC. The gold plating system is manufactured by Electroplating Engineers of Japan, Ltd., and the product name is Mikulong Law Department Au100 ( Au100) was carried out as a gold plating solution under the conditions of a plating temperature of 60 ° C and a current density of 0.5 A/dm 2 . The resulting joint face obtained by this result had a surface roughness Ra of 0.298 μm. Otherly, under the same conditions as in Example 1, the bump IC was attached to the glass via the anisotropic conductive film.

(比較例2)(Comparative Example 2)

變更實施例1及實施例2以及比較例1的鍍金液及電鍍條件製作附凸起IC。鍍金係使用日本電鍍技術株式會社(Electroplating Engineers of Japan,Ltd.)製造、商品名米庫龍法部Au660(Au660)作為鍍金液，在電鍍溫度60℃、電流密度0.8A/dm2 之條件下進行。該結果所得之凸起的連接面，其表面粗糙度Ra為0.130μm。其他係在與實施例1相同的條件下，隔著異向性導電膜將附凸起IC裝配於玻璃。The bump IC was produced by changing the gold plating liquid and the plating conditions of Example 1 and Example 2 and Comparative Example 1. The gold plating system is manufactured by Electroplating Engineers of Japan, Ltd., and the product name is Mikulong Law Department Au660 ( Au660) was carried out as a gold plating solution under the conditions of a plating temperature of 60 ° C and a current density of 0.8 A/dm 2 . The resulting joint face obtained by this result had a surface roughness Ra of 0.130 μm. Otherly, under the same conditions as in Example 1, the bump IC was attached to the glass via the anisotropic conductive film.

評估：Evaluation:

針對作為各實施例及比較例所製作的異向性導電膜A、B，利用光學顯微鏡從玻璃之內面觀察凸起上所捕捉的導電性粒子，計算粒子捕捉數並求得總粒子捕捉數，再計算粒子的潰散狀態合格者求得有效粒子捕捉數(範圍2000μm2 )。其結果顯示於下表1及下表2。又，下表1係顯示異向性導電膜A的結果，下表2係顯示異向性導電膜B的結果。With respect to the anisotropic conductive films A and B produced in the respective examples and comparative examples, the conductive particles captured on the projections were observed from the inner surface of the glass by an optical microscope, and the number of captured particles was calculated to obtain the total number of captured particles. Then, if the particle collapse state is calculated, the effective particle capture number (range 2000 μm 2 ) is obtained. The results are shown in Table 1 below and Table 2 below. Further, Table 1 below shows the results of the anisotropic conductive film A, and Table 2 below shows the results of the anisotropic conductive film B.

從該等上表1及上表2可得知，藉由令凸起之表面粗糙度Ra在0.05μm以下，有助於電性連接的有效導電粒子數目大為增加。又，在總粒子捕捉數方面，其數值也在比較例的同等以上。As can be seen from the above Table 1 and Table 2, the number of effective conductive particles contributing to the electrical connection is greatly increased by making the surface roughness Ra of the bumps 0.05 μm or less. Moreover, in terms of the total particle capture number, the numerical value is equal to or higher than that of the comparative example.

又，第3圖中，顯示了實施例1(異向性導電膜A)中的凸起近旁之光學顯微鏡影像。第4圖中，顯示了比較例1(異向性導電膜B)中的凸起近旁之光學顯微鏡影像。比較該圖式即可得知，實施例1中，凸起的頂部呈現極為平滑的狀態，相對的，比較例1中，凸起的頂部乃粗糙模樣。Further, in Fig. 3, an optical microscope image of the vicinity of the projection in the first embodiment (the anisotropic conductive film A) is shown. In Fig. 4, an optical microscope image of the vicinity of the projection in Comparative Example 1 (anisotropic conductive film B) is shown. As can be seen from the comparison of the drawings, in the first embodiment, the top of the projection exhibited an extremely smooth state, and in contrast, in the comparative example 1, the top of the projection was rough.

又，第5圖中，顯示了實施例1(異向性導電膜A)中的凸起近旁之其他光學顯微鏡影像。第6圖中，顯示了比較例1(異向性導電膜B)中的凸起近旁之其他光學顯微鏡影像。無論哪個圖式(照片)，皆為凸起週邊部的光學顯微鏡影像。比較該圖式即可得知，實施例1中，在包含凸起週邊部之凸起全體中，導電性粒子皆均勻潰散。相對的，比較例1中，特別是在凸起週邊部，導電性粒子的潰散方式不足。Further, in Fig. 5, other optical microscope images in the vicinity of the projections in the first embodiment (the anisotropic conductive film A) are shown. In Fig. 6, other optical microscope images in the vicinity of the projections in Comparative Example 1 (anisotropic conductive film B) are shown. Regardless of which pattern (photograph), it is an optical microscope image of the convex portion. As can be seen from the comparison of the drawings, in the first embodiment, the conductive particles were uniformly collapsed in the entire projection including the peripheral portion of the projection. On the other hand, in Comparative Example 1, in particular, in the peripheral portion of the projection, the manner in which the conductive particles were broken was insufficient.

退火處理之影響的評估：Evaluation of the effects of annealing:

接著，為了評估退火處理對於凸起表面粗糙度Ra的影響，而對作為實施例1所製作的附凸起IC施以退火處理，測定退火處理前後的表面粗糙度Ra。其結果顯示於下表3。Next, in order to evaluate the influence of the annealing treatment on the surface roughness Ra of the bump, the bump IC prepared as Example 1 was annealed, and the surface roughness Ra before and after the annealing treatment was measured. The results are shown in Table 3 below.

由表3可清楚得知，對作為實施例1所製作的附凸起IC施以退火處理時，在退火處理後的表面粗糙度Ra變成0.0179μm，其與對例如藉由切削頂部使其平滑的凸起實施退火處理等習知手法不同，保持0.05μm以下之值。其理由如下，亦即，作為實施例1所製作的凸起，雖屬鍍金液之粒塊(結晶粒)堆積所形成，但為了使其頂部作製平滑，故使用已控制結晶狀態之鍍金液以使結晶粒變小。具體而言，在作為實施例1所製作的凸起中，當測定退火前處理的凸起截面之結晶粒模樣時，即如第7圖中左側之分布圖所示，有極細微的結晶粒集結，且如第7圖中右側所示，其平均粒徑為0.08μm。亦即，作為實施例1所製作的凸起，是由退火處理前的平均粒徑為0.1μm以下之結晶粒以極其細微地推基所形成者，依此，即使施以退火，其鍍金液的結晶粒也不會變大，可在歷經退火處理前後控制結晶粒的大小變化，使凸起的表面粗糙度Ra保持在0.05μm以下。As is clear from Table 3, when the bump IC fabricated as Example 1 was subjected to an annealing treatment, the surface roughness Ra after the annealing treatment was changed to 0.0179 μm, which was smoothed by, for example, cutting the top. The protrusions are subjected to an annealing treatment or the like in a conventional manner, and a value of 0.05 μm or less is maintained. The reason for this is that the projections produced in the first embodiment are formed by depositing granules (crystal grains) of the gold plating liquid, but in order to smooth the top portion, the gold plating liquid having the controlled crystal state is used. The crystal grains are made smaller. Specifically, in the projections produced as in the first embodiment, when the crystal grain shape of the convex section processed before annealing is measured, that is, as shown in the distribution diagram on the left side in FIG. 7, there are extremely fine crystal grains. Aggregate, and as shown on the right side of Fig. 7, its average particle diameter was 0.08 μm. In other words, the projections produced in the first embodiment are formed by extremely finely pushing the crystal grains having an average particle diameter of 0.1 μm or less before the annealing treatment, and thus, even if an annealing is applied, the gold plating solution is applied. The crystal grains do not become large, and the size of the crystal grains can be controlled before and after the annealing treatment, so that the surface roughness Ra of the protrusions is kept at 0.05 μm or less.

如此，本發明之上述實施例可顯示，可在歷經退火處理前後使凸起的表面粗糙度Ra在0.05μm，即使異向性導電膜中所含之導電性粒子其粒子徑很小，仍可均勻潰散，可在所製造的電性連接體中獲得良好的導通特性。Thus, the above embodiment of the present invention can show that the surface roughness Ra of the protrusion can be 0.05 μm before and after the annealing treatment, even if the conductive particles contained in the anisotropic conductive film have a small particle diameter, Uniform collapse provides good conduction characteristics in the fabricated electrical connectors.

根據本發明上述實施例，即使在異向性導電膜中所含的導電性粒子之粒子徑很小的情況下，仍可將之均勻潰散，可獲得良好的導通特性。因此，依據本發明，可實現導通可靠性優異的電性連接體。According to the above embodiment of the present invention, even when the particle diameter of the conductive particles contained in the anisotropic conductive film is small, it can be uniformly collapsed, and good conduction characteristics can be obtained. Therefore, according to the present invention, an electrical connector excellent in conduction reliability can be realized.

綜上所述，雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1．．．半導體元件1. . . Semiconductor component

2．．．凸起2. . . Bulge

2a．．．連接面凹部2a. . . Connection face recess

3．．．配線基板3. . . Wiring substrate

4．．．電極4. . . electrode

5．．．異向性導電膜5. . . Anisotropic conductive film

6．．．導電性粒子6. . . Conductive particles

第1圖繪示電性連接體之一構成例的概略截面圖。Fig. 1 is a schematic cross-sectional view showing an example of the configuration of an electrical connector.

第2圖係模式地繪示了當凸起的表面具有凹凸時其導電性粒子之潰散方式的概略截面圖。Fig. 2 is a schematic cross-sectional view schematically showing a manner in which the conductive particles are broken when the surface of the bump has irregularities.

第3圖繪示實施例1中的凸起近旁之光學顯微鏡影像。Fig. 3 is a view showing an optical microscope image of the vicinity of the projection in the first embodiment.

第4圖繪示比較例1中的凸起近旁之光學顯微鏡影像。Fig. 4 is a view showing an optical microscope image of the vicinity of the projection in Comparative Example 1.

第5圖繪示實施例1中的凸起近旁之其他光學顯微鏡影像FIG. 5 is a view showing another optical microscope image near the protrusion in Embodiment 1.

第6圖繪示比較例1中的凸起近旁之其他光學顯微鏡影像。Fig. 6 is a view showing another optical microscope image in the vicinity of the projection in Comparative Example 1.

第7圖繪示實施例1中的凸起截面之結晶粒模樣之圖。Fig. 7 is a view showing a pattern of crystal grains of a convex section in Example 1.

1．．．半導體元件1. . . Semiconductor component

2．．．凸起2. . . Bulge

3．．．配線基板3. . . Wiring substrate

4．．．電極4. . . electrode

5．．．異向性導電膜5. . . Anisotropic conductive film

6．．．導電性粒子6. . . Conductive particles

Claims (12)

一種電性連接體，係第一電子零件與第二電子零件隔著異向性導電膜而電性連接者，該電性連接體係在任一側之電子零件上形成有凸起電極，該凸起電極之頂部係作成在退火處理後的表面粗糙度Ra為0.05μm以下之平坦面。An electrical connector, wherein the first electronic component and the second electronic component are electrically connected via an anisotropic conductive film, and the electrical connection system forms a bump electrode on the electronic component on either side, the bump The top of the electrode was formed into a flat surface having a surface roughness Ra of 0.05 μm or less after the annealing treatment. 如申請專利範圍第1項所述之電性連接體，其中該凸起電極之頂部係作成在退火處理後的表面粗糙度Ra為0.02μm以下之平坦面。The electrical connector according to claim 1, wherein the top of the bump electrode is formed as a flat surface having a surface roughness Ra of 0.02 μm or less after the annealing treatment. 如申請專利範圍第1項所述之電性連接體，其中該凸起電極之頂部係藉由鍍金所形成。The electrical connector of claim 1, wherein the top of the bump electrode is formed by gold plating. 如申請專利範圍第1~3項中任一項所述之電性連接體，其中該異性向導電膜中所含的導電性粒子之平均粒徑為4μm以下。The electrical connector according to any one of the first to third aspects of the invention, wherein the conductive particles contained in the conductive film are an average particle diameter of 4 μm or less. 如申請專利範圍第4項所述之電性連接體，其中該導電性粒子係以樹脂粒子為芯材，於其表面形成導電層。The electrical connector according to claim 4, wherein the conductive particles have a resin layer as a core material and a conductive layer is formed on the surface. 如申請專利範圍第4項所述之電性連接體，其中該樹脂粒子係20%壓縮變形時的壓縮硬度為100~1000kgf/mm2 。The electrical connector according to claim 4, wherein the resin particles have a compression hardness of 100 to 1000 kgf/mm 2 at 20% compression deformation. 一種電性連接體的製造方法，該方法包含：在第一電子零件與第二電子零件之任一側，藉電鍍形成頂部表面粗糙度Ra作成0.05μm以下之平坦面的凸起電極之步驟；使異向性導電膜介在於該第一電子零件與該第二電子零件之間的步驟；以及藉按壓將與該凸起電極相向的異向性導電膜之導電性粒子受壓潰散，使該第一電子零件與該第二電子零件電性連接之步驟。A method for manufacturing an electrical connector, comprising: forming, on either side of the first electronic component and the second electronic component, a top surface roughness Ra to form a raised electrode having a flat surface of 0.05 μm or less; a step of interposing an anisotropic conductive film between the first electronic component and the second electronic component; and pressing and pressing the conductive particles of the anisotropic conductive film facing the bump electrode The step of electrically connecting the first electronic component to the second electronic component. 如申請專利範圍第7項所述之電性連接體的製造方法，其中該凸起電極之頂部係作成在該表面粗糙度Ra為0.02μm以下之平坦面。The method for producing an electrical connector according to claim 7, wherein the top of the bump electrode is formed as a flat surface having a surface roughness Ra of 0.02 μm or less. 如申請專利範圍第7項所述之電性連接體的製造方法，其中該凸起電極之頂部係藉由鍍金所形成。The method of manufacturing the electrical connector of claim 7, wherein the top of the bump electrode is formed by gold plating. 如申請專利範圍第7~9項中任一項所述之電性連接體的製造方法，其中該凸起電極之頂部係作成在退火處理後的該表面粗糙度Ra為0.02μm以下之平坦面。The method for producing an electrical connector according to any one of claims 7 to 9, wherein the top of the bump electrode is formed as a flat surface having a surface roughness Ra of 0.02 μm or less after the annealing treatment. . 如申請專利範圍第7~9項中任一項所述之電性連接體的製造方法，其中在形成該凸起電極之際所使用的電鍍液之結晶粒，係退火處理前的平均粒徑為0.1μm以下。The method for producing an electrical connector according to any one of claims 7 to 9, wherein the crystal grain of the plating solution used in forming the bump electrode is an average particle diameter before annealing treatment It is 0.1 μm or less. 如申請專利範圍第10項所述之電性連接體的製造方法，其中在形成該凸起電極之際所使用的電鍍液之結晶粒，係退火處理前的平均粒徑為0.1μm以下。The method for producing an electrical connector according to claim 10, wherein the crystal grain of the plating solution used for forming the bump electrode has an average particle diameter before annealing treatment of 0.1 μm or less.
TW097141683A 2007-10-29 2008-10-29 Electrical connector and method of manufacturing the same TWI443762B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007279941A JP5622137B2 (en) 2007-10-29 2007-10-29 Electrical connection body and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW200935531A TW200935531A (en) 2009-08-16
TWI443762B true TWI443762B (en) 2014-07-01

Family

ID=40590973

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097141683A TWI443762B (en) 2007-10-29 2008-10-29 Electrical connector and method of manufacturing the same

Country Status (4)

Country Link
JP (1) JP5622137B2 (en)
KR (1) KR101505214B1 (en)
TW (1) TWI443762B (en)
WO (1) WO2009057582A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012056661A1 (en) 2010-10-25 2012-05-03 パナソニック株式会社 Electronic components assembly
TWI456674B (en) * 2012-01-03 2014-10-11 Chipbond Technology Corp Semiconductor package and method thereof
JP6209313B2 (en) 2012-02-20 2017-10-04 デクセリアルズ株式会社 Anisotropic conductive film, connection structure, method for manufacturing connection structure, and connection method
KR101513642B1 (en) * 2013-08-21 2015-04-20 엘지전자 주식회사 A device of a semiconductor
JP2015179831A (en) * 2014-02-27 2015-10-08 デクセリアルズ株式会社 Connection body, manufacturing method of the same, and inspection method of the same
TWI809284B (en) * 2015-01-13 2023-07-21 日商迪睿合股份有限公司 Anisotropic conductive film, connection structure and method for manufacturing connection structure
CN111670488B (en) * 2018-02-01 2021-08-17 新唐科技日本株式会社 Semiconductor device with a plurality of semiconductor chips

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56108892A (en) * 1980-01-31 1981-08-28 Electroplating Eng Of Japan Co Plating solution with pure gold
JPH0797587B2 (en) * 1987-03-12 1995-10-18 株式会社東芝 Method for manufacturing semiconductor device
JPH065609A (en) * 1992-06-17 1994-01-14 Tanaka Kikinzoku Kogyo Kk Bump forming method
WO2000045431A1 (en) * 1999-01-27 2000-08-03 Citizen Watch Co., Ltd. Method of packaging semiconductor device using anisotropic conductive adhesive
JP2000269269A (en) * 1999-03-15 2000-09-29 Toshiba Corp Semiconductor mounting substrate, semiconductor device and manufacture thereof
JP2001007137A (en) * 1999-06-24 2001-01-12 Nec Corp Manufacture of semiconductor device
JP3828122B2 (en) * 2004-05-25 2006-10-04 日本アビオニクス株式会社 Electrical component connection method
JP2005347452A (en) * 2004-06-02 2005-12-15 Renesas Technology Corp Manufacturing method of semiconductor device
JP4035138B2 (en) * 2004-07-20 2008-01-16 松下電工株式会社 Flip chip mounting method
TW200638497A (en) * 2005-04-19 2006-11-01 Elan Microelectronics Corp Bumping process and bump structure
JP2006303250A (en) * 2005-04-21 2006-11-02 Ebara Corp Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
KR101505214B1 (en) 2015-03-23
TW200935531A (en) 2009-08-16
JP5622137B2 (en) 2014-11-12
JP2009111043A (en) 2009-05-21
WO2009057582A1 (en) 2009-05-07
KR20100077129A (en) 2010-07-07

Similar Documents

Publication Publication Date Title
TWI443762B (en) Electrical connector and method of manufacturing the same
US5545589A (en) Method of forming a bump having a rugged side, a semiconductor device having the bump, and a method of mounting a semiconductor unit and a semiconductor device
KR101886909B1 (en) Anisotropic conductive connection material, connection structure, manufacturing method and connection method for connection structure
KR102081570B1 (en) Anisotropic conductive connection structure
JP2004051755A (en) Elastic electrical conductive resin and elastic electrical conductive joint structure
JP2010199087A (en) Anisotropic conductive film and manufacturing method therefor, and junction body and manufacturing method therefor
US6426021B2 (en) Anisotropically electroconductive adhesive material and connecting method
KR101842855B1 (en) Manufacturing method of mounting device, connecting method and anisotropic conductive film
JP4191567B2 (en) Connection structure using conductive adhesive and method for manufacturing the same
TW201337959A (en) Bonding method using anisotropic conductive material, and anisotropic conductive bonded structure
TW201829195A (en) Film containing filler
JP2010272545A (en) Manufacturing method of mounting body, mounting body, and anisotropic conductive film
CN113056844A (en) Anisotropic conductive film, connection structure, and method for manufacturing connection structure
JPH114064A (en) Anisotropic conductive resin and mounting structure for electronic component using the same
JP5113390B2 (en) Wiring connection method
JP5245270B2 (en) Semiconductor device and manufacturing method thereof
JP5608504B2 (en) Connection method and connection structure
JP2018073684A (en) Manufacturing method of connection body, connection method, and connection device
CN115053640A (en) Method for producing connected body, and connected body
JP6562750B2 (en) Electronic component, connection body, manufacturing method of connection body, connection method of electronic component, cushioning material
CN105430901B (en) Electronic component and connection method thereof, connection body and manufacturing method thereof, and buffer material
TW201825563A (en) Film containing filler
JP2008179834A (en) Electrically-conductive elastic resin
TW202341578A (en) Anisotropic conductive film
JPH05291428A (en) Manufacture of board for mounting semiconductor device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees