JP2005347452A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control surface condition and cross-sectional shape of a bump electrode on the occasion of forming the bump electrode using a non-cyanogen system plating solution. <P>SOLUTION: The main surface of an n-type high concentration substrate 1 is plated while the surface is polished with a polishing member PLS or polishing device PLS2 under the condition that the main surface thereof is in contact with the non-cyanogen system plating solution PTL. Consequently, a metal film is formed as the bump electrode BMP. Accordingly, formation of unwanted waving in the shape of recess and roughness on the surface of the bump electrode BMP can be prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a process of forming a protruding electrode by a plating method.

For example, in a manufacturing process of a glass package diode formed by pressure-bonding an Ag (silver) bump and a lead, the unevenness and particle size of the pressure connection surface of the Ag bump are 1 μm or less, and the bump hardness is 100 Bickers hardness (Hv There is a technique for improving the connection strength between the Ag bump and the lead by setting the plating conditions at the time of forming the Ag bump or the additive to the plating solution so as to achieve the above (for example, see Patent Document 1).
JP 2002-43347 A

In the process of manufacturing a glass package diode, for example, a cyan plating solution containing AgCN (silver cyanide), KCN (potassium cyanide), and K ₂ CO ₃ (potassium carbonate) is used to form a bump electrode made of Ag. ing. Further, in order to smooth the surface of the bump electrode, NaSCN (sodium thiocyanate), NH ₄ SCN (ammonium thiocyanate), Sb (antimony), Se (selenium), Te (tellurium) are used as brighteners in the plating solution. , Bi (bismuth), benzene sulfonate or mercaptans.

  In order to improve the safety of the plating process, the present inventors are examining a technique that uses a non-cyanide plating solution instead of the cyan plating solution. Among them, the present inventors have found the following problems.

  That is, examples of the non-cyan plating solution used for forming the bump electrode made of Ag include a silver nitrate plating solution and a metasulfonic acid plating solution. However, when using these plating solutions, the present inventors cannot make the surface state of the formed bump electrode smooth as desired, or an undesirable step is formed in the cross-sectional shape of the bump electrode. I found out that it was going to fall. If such a step is formed, the contact area between the bump electrode and the jumet line to which the bump electrode is connected is reduced, so that the resistance value is increased at the connection portion between the bump electrode and the dumet line. Therefore, there is a problem that the voltage characteristics of the diode are different from the desired characteristics.

  An object of the present invention is to provide a technique capable of controlling the surface state and cross-sectional shape of a bump electrode when the bump electrode is formed using a non-cyan plating solution.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a protruding electrode formed by plating,
(A) forming a masking film on the main surface of the semiconductor wafer and forming a plurality of openings in the masking film;
(B) Growing a metal film from within the plurality of openings while rubbing the main surface of the semiconductor wafer with friction means while supplying a non-cyan plating solution to the main surface of the semiconductor wafer, A step of forming a plurality of protruding electrodes from
Is included.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, when forming a bump electrode using a non-cyan plating solution, the surface state and cross-sectional shape of the bump electrode can be controlled.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The semiconductor device of the first embodiment includes, for example, a diode. The manufacturing process of the semiconductor device according to the first embodiment will be described with reference to FIGS.

First, a wafer-like n-type high-concentration substrate (semiconductor wafer) 1 made of Si (silicon) doped with an n-type impurity (for example, Sb (antimony)) at a high concentration is prepared. For example, the concentration of the n-type impurity doped in the n-type high-concentration substrate 1 is, for example, about 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³ .

Subsequently, an n-type low concentration layer 2 is formed by epitaxially growing an n-type Si layer doped with an n-type impurity (for example, P (phosphorus)) on the main surface of the n-type high concentration substrate 1. The n-type low-concentration layer 2 has a resistivity of about 100 Ωcm or more, a thickness of, for example, about 15 μm, and a concentration of doped n-type impurities of 1 × 10 ¹⁶ atoms / cm ³ to 1 ×. An example is about 10 ¹⁹ pieces / cm ³ .

  Subsequently, a thermal oxidation process is performed on the n-type high concentration substrate 1 to form a silicon oxide film 3 having a thickness of about 0.4 μm to 1 μm on the surface of the n-type low concentration layer 2.

  Next, as shown in FIG. 2, a photoresist film (not shown) is formed on the silicon oxide film 3 on the surface of the n-type low concentration layer 2, and this photoresist film is patterned by a photolithography technique. An opening is formed. Subsequently, the silicon oxide film 3 is etched using the photoresist film as a mask, and an opening 6 for forming a p-type diffusion layer to be formed in the next step on the silicon oxide film 3 on the surface of the n-type low concentration layer 2. Are selectively formed.

Next, after removing the photoresist film, a doping material such as PBF (Poly Boron Film) is applied on the n-type low concentration layer 2 including the inside of the opening 6. Subsequently, by annealing the n-type high concentration substrate 1 in an atmosphere of about 900 ° C., the n-type low concentration layer 2 is doped with B (boron) as a p-type impurity, and the p-type diffusion layer 7 Form. Subsequently, in a N ₂ (nitrogen) atmosphere, the n-type high concentration substrate 1 is subjected to a heat treatment at about 1000 ° C., thereby forming a pn junction between the p-type diffusion layer 7 and the n-type low concentration layer 2. A diode element can be formed.

  Next, as shown in FIG. 3, an oxide film 9 is formed on the surface of the p-type diffusion layer 7 using a thermal oxidation method. Subsequently, a silicon oxide film and a PSG (Phospho Silicate Glass) film are sequentially deposited on the silicon oxide film 3 including the inside of the opening 6 to form a surface protective film 10 composed of the silicon oxide film and the PSG film. Subsequently, using the photoresist film (not shown) as a mask, the oxide film 9 and the surface protective film 10 are etched to form a contact hole 11 reaching the p-type diffusion layer 7.

  Subsequently, a metal film made of Au (gold) and Ag (silver) is deposited on the surface protective film 10 including the inside of the contact hole 11 by using, for example, a sputtering method. Subsequently, the surface electrode 12 is formed by lift-off or etching the metal film using a photoresist film (not shown) as a mask. Subsequently, as shown in FIG. 4, a bump electrode (projection electrode) BMP is formed by depositing, for example, an Ag film on the surface electrode 12 by plating.

  Here, FIG. 5 is an explanatory diagram of an example of a plating apparatus used in forming the bump electrode BMP in the first embodiment. In the plating apparatus shown in FIG. 5, a carbon dish CBD, a porous member POR, and a polishing member (polishing means) PLS are arranged from below in a stage STG formed of, for example, stainless steel. As the porous member POR, for example, one formed from conductive polyurethane can be used. The polishing member PLS can be made of, for example, a high-temperature dust collection filter cloth woven or a wholly aromatic polyamide heat-resistant fiber.

  On the polishing member PLS, a wafer-like n-type high-concentration substrate 1 on which an Ag film serving as a bump electrode BMP is deposited on the main surface (element formation surface) by plating is disposed. Is held by the pedestal PDS. The pedestal PDS is formed of an adsorption member ADS and a holder HLD, and the adsorption member ADS holds the n-type high concentration substrate 1 so that the back surface of the n-type high concentration substrate 1 is vacuum-sucked and the main surface is in contact with the polishing member PLS. ing.

  During the plating process on the n-type high concentration substrate 1, a non-cyan plating solution PTL is dropped into the stage STG, and a potential is supplied from the power source PS to the adsorption member ADS, the holder HLD, and the stage STG. Examples of the components of the plating solution PTL include silver nitrate of about 4.7%, heterocyclic compound of about 22%, potassium hydroxide of 11%, and water of 60% or less. In FIG. 5, a DC power source is illustrated as the power source PS, but a power source that emits a pulse wave, a power source that emits a square wave, a power source that emits a sine wave, or the like may be used. Air is supplied toward the outer periphery of the n-type high concentration substrate 1 from the discharge port BOH provided between the holder HLD and the n-type high concentration substrate 1. By supplying this air, the amount of the plating solution PTL flowing into the suction surface between the suction member ADS and the n-type high concentration substrate 1 can be reduced, so that suction when the suction member ADS vacuum-sucks the n-type high concentration substrate 1. It is possible to prevent a problem that the plating solution PTL is excessively sucked by the force. Under such circumstances, the stage STG rotates to cause the main surface of the n-type high concentration substrate 1 (the surface of the bump electrode BMP being formed) to be polished by the polishing member PLS during the plating process.

Further, instead of using the plating apparatus as shown in FIG. 5, a bath-type plating apparatus as shown in FIGS. 6 and 7 may be used. In this case, power may be supplied from the back side of the n-type high concentration substrate 1 in the same manner as the n-type high concentration substrate 1 used in the plating apparatus shown in FIG. A power supply metal film (for example, an Al (aluminum) film) UBM is formed (see FIG. 8), and a surface final protective film 13 made of a laminated film of a silicon nitride film and a silicon oxide film is formed on the metal film UBM. A current for forming bump electrodes may be supplied from the surface of the n-type high concentration substrate 1. FIG. 6 is a perspective view of the bathtub type plating apparatus, and FIG. 7 is a plan view of the bathtub type plating apparatus as viewed from above. 6 and 7, the holder HLD2 is disposed on the cathode side in the bathtub TB1 while holding the wafer-like n-type high concentration substrate 1, and a plate-like Ag electrode is provided on the anode side. An ECR is disposed, and a polishing instrument (polishing means) PLS2 for polishing the surface of the n-type high concentration substrate 1 held by the holder HLD2 is disposed between the holder HLD2 and the Ag electrode ECR. The components of the non-cyan plating solution held in the bath TB1 are the same as those of the non-cyan plating solution PTL shown in FIG. The polishing tool PLS2 has a polishing member attached to the tip of an arm that rubs the surface of the n-type high-concentration substrate 1. As the polishing member, for example, a conductive sponge whose surface is covered with a polyimide sheet is used. Use. The polishing tool PLS2 polishes the main surface (the surface of the bump electrode BMP being formed) of the n-type high concentration substrate 1 by an operation such as a circular motion or a reciprocating motion during the plating process. At this time, the polishing pressure applied to the n-type high concentration substrate 1 from the polishing tool PLS2 can be exemplified as about 1 × 10 ⁵ Pa to 2 × 10 ⁷ Pa. Further, when the polishing tool PLS2 polishes the main surface of the n-type high concentration substrate 1 by a reciprocating motion, it can be exemplified that the reciprocating motion is performed about 20 times per minute.

  Here, the waviness and roughness of the surface of the bump electrode BMP in the first embodiment will be described. In the first embodiment, the difference H1 between the highest position and the lowest position on the surface of the bump electrode BMP is referred to as the undulation of the surface of the bump electrode BMP (see FIG. 9). Further, in the first embodiment, in the cross section showing the diameter of the bump electrode BMP, the cross section is equally divided in the width direction, and among the plurality of equally divided areas W1, there is a difference in elevation in the central area W1. The surface with the largest surface roughness indicated by H2 is called the surface roughness of the bump electrode BMP (see FIG. 10).

  In the first embodiment, the bump electrode BMP is used as shown in FIG. 11 regardless of which of the plating apparatus described with reference to FIG. 5 and the plating apparatus described with reference to FIGS. When the surface of the Ag film becomes higher than the surface of the photoresist film that becomes the masking film during the plating process, the surface of the Ag film is polished by the polishing member PLS or the polishing tool PLS2 in the plating solution PTL. . According to experiments conducted by the present inventors, for example, when the depth of the opening formed in the photoresist film is about 2 μm, a height of 5 μm to 5 μm in the opening is formed using a non-cyanide plating solution. When the bump electrode BMP of about 10 μm is formed, if the main surface of the n-type high concentration substrate 1 is not polished as described above, the surface of the bump electrode BMP has a concave undulation of about 1 μm or more, It was found that a roughness of 0.03 μm or more was formed (see FIG. 12). At this time, the applied current was about 10 minutes at a direct current of 400 mA. If such waviness and roughness are formed, the contact area between the bump electrode BMP and the dumet line will be reduced when the bump electrode BMP is connected to the dumet line in a later step. Become. As the contact area is reduced, the resistance value increases at the connection portion between the bump electrode BMP and the dumet wire, and there is a concern that the voltage characteristics of the diode may be different from the desired characteristics.

  On the other hand, when the bump electrode BMP is formed while performing the polishing as described above, the surface of the bump electrode BMP is flat as compared with the case where the polishing is not performed, and the undulation of about 1 μm or less and about 0.03 μm or less. The roughness could be obtained (see FIG. 13). At this time, the applied current was a pulse application in the forward direction and the reverse direction, and after flowing a 430 mA DC current in the forward direction for about 50 ms, a flow of 30 mA DC current in the reverse direction for about 50 ms was repeated for about 10 minutes. Is. That is, in the case where the bump electrode BMP is formed by a plating method using a non-cyan plating solution, the bump electrode BMP is formed while polishing the main surface of the n-type high-concentration substrate 1. Waviness and roughness can be reduced. Thereby, when the bump electrode BMP is connected to the dumet line in a later step, it is possible to prevent the contact area between the bump electrode BMP and the dumet line from being reduced, and thus a diode having a desired voltage characteristic is manufactured. It becomes possible.

  Further, as shown in FIG. 13, during the plating process, it is possible to form a shape in which the central portion of the bump electrode BMP is convex by increasing the polishing pressure applied to the n-type high concentration substrate 1. .

  By the way, in the plating apparatus described with reference to FIG. 5, the main surface of the n-type high concentration substrate 1 is polished by rotating the stage STG. However, as shown in FIG. The substrate 1 may also be rotated. In addition, as shown in FIG. 16, a plurality of n-type high concentration substrates 1 may be disposed on the stage STG, and these n-type high concentration substrates 1 may be processed at once.

  Further, as shown in FIG. 17, the stage STG may have a structure that reciprocates instead of rotating. Further, as shown in FIG. 18, the n-type high concentration substrate 1 may be rotated or reciprocated on such a stage STG. The stage STG may be rotated as well as reciprocating (see FIG. 19). At this time, the operation directions of the stage STG and the n-type high concentration substrate 1 are aligned so that the main surface of the n-type high concentration substrate is not rubbed by the polishing member PLS.

  In addition, as shown in FIG. 20, a plurality of n-type high concentration substrates 1 may be arranged on the stage STG. At this time, either one or both of the n-type high concentration substrate 1 and the stage STG are rotated or reciprocated. As a result, it is possible to collectively perform plating on a plurality of n-type high concentration substrates 1.

  Further, as shown in FIG. 21, the n-type high concentration substrate 1 is sequentially loaded onto the stage STG from the loader, and, for example, the n-type high concentration substrate 1 is moved in the direction from the loader to the unloader while rotating. You may make it unload. After the plating process is completed and the n-type high concentration substrate 1 is unloaded from the stage STG, it is stored in a wafer cassette (not shown), and a predetermined number of n-type high concentration substrates 1 are stored in the wafer cassette. The wafer cassette is stored in water.

  Further, in the bath type plating apparatus described with reference to FIG. 6, the polishing tool PLS2 polishes the main surface of the wafer-like n-type high concentration substrate 1 held by the holder HLD2 during the plating process. As shown in FIG. 22, the main surface of the n-type high concentration substrate 1 may be polished using a cylindrical polishing tool (polishing means) PLS3 instead of the polishing tool PLS2. At this time, polishing is performed by rotating either one or both of the n-type high concentration substrate 1 and the polishing tool PLS3. The rotational motion may be rotational motion in one direction as shown in FIG. 22 or rotational motion in both directions as shown in FIG. Further, as shown in FIGS. 24 and 25, a polishing tool PLS may be incorporated in the cup of the jet plating apparatus, and the surface of the n-type high concentration substrate 1 may be polished by rotation / linear motion. FIG. 25 is an enlarged view of the cup portion in FIG.

  After the formation of the bump electrode BMP, in the case with a metal film UBM such as an Al film, the photoresist film (not shown) that has become a masking film during the plating process is removed. Subsequently, as shown in FIG. 26, only the metal film UBM around the bump electrode BMP is removed, for example, by wet etching using a potassium hydroxide solution.

  Next, the back surface of the n-type high-concentration substrate 1 is ground by grinding, and the n-type high-concentration substrate 1 is thinned according to the package form described later. Subsequently, the back surface of the n-type high concentration substrate 1 is etched by, for example, a wet etching method using a spin etching apparatus.

  Subsequently, after the n-type high concentration substrate 1 is cleaned, an Ag (silver) film is deposited on the back surface of the n-type high concentration substrate 1 by using, for example, a sputtering method. Subsequently, the n-type high concentration substrate 1 is divided by dicing to form a semiconductor chip 18 having a diode as a unit element.

  Next, as shown in FIG. 27, a relatively long dumet line for forming a dumet electrode is prepared. This dumet wire is formed of, for example, a cylindrical core portion made of an alloy mainly composed of Fe (iron) and Ni, and a coating layer mainly composed of Cu formed on the outer periphery of the core portion. ing. Subsequently, the jumet line is cut into a predetermined length using, for example, a diamond cutter, etc., to form the jumet electrodes 21 and 22. Since the dumet electrode (second electrode) 22 is used in a later process, the illustration in FIG. 27 is omitted.

  Next, the external lead 23 is connected (welded) to the center position of the end face of the dumet electrode 21 or its vicinity, and the external lead 24 is connected (crimped) to the center position of the end face of the dumet electrode 22 or its vicinity. For example, an arc welding method or a spot welding method can be applied to the connection between the external lead 23 and the dumet electrode 21 and the connection between the external lead 24 and the dumet electrode 22. In addition, after connecting (welding) the external lead 23 (external lead 24) to the cross section of the jumet wire for forming the jumet electrodes 21, 22, the dumet wire is cut and the external lead 23 (external lead 24) is connected (welded). ) Formed dumet electrode 21 (jumet electrode 22) can also be formed. Note that the external lead 24 and the dumet electrode 22 have substantially the same structure as the external lead 23 and the dumet electrode 21, and are not shown in FIG.

  Next, glass sealing is performed using the assembly jig 25. A plurality of circular holes 26 are provided in a lattice shape on the upper surface of the assembly jig 25. The hole 26 is formed on the upper surface of the assembly jig 25. The dumet electrode 21 to which the external lead 23 is connected as described above is inserted into each hole portion 26 of the assembly jig 25 with the jumet electrode 21 side facing up (the external lead 23 side facing down).

  Next, the glass tube 27 to be a glass sealing body is fitted with the jumet electrode 21.

  Next, as shown in FIG. 28, the semiconductor chip 15 is put into the glass tube 27. Thereby, the semiconductor chip 18 is disposed on the jumet electrode 21 in the hole of the glass tube 27. At this time, either the main surface (surface on the bump electrode BMP forming side) or the back surface (surface on the back electrode 17 forming side) of the semiconductor chip 18 may face upward.

  Next, as shown in FIG. 29, the jumet electrode 22 to which the external lead 24 is connected is placed in the hole 26 of the assembly jig 25 with the jumet electrode 22 side down (the external lead 24 side up). Insert (inject). Thereby, the jumet electrode 22 is fitted in the hole of the glass tube 27. The semiconductor chip 17 is sandwiched between dumet electrodes 21 and 22. Then, if necessary, a load is applied to the dumet electrode 22 using a pressurizing device (not shown), thereby pressing the dumet electrodes 21 and 22 against the semiconductor chip 17.

  Next, the assembly jig 25 in which the jumet electrodes 21 and 22, the chip 15 and the glass tube 27 are set is put into a glass sealing heating device (not shown) and heated at a predetermined temperature. Thereby, the glass tube 27 is melted and the glass tube 27 is fused to the outer peripheral surfaces of the jumet electrodes 21 and 22. After heating, it is cooled and the glass tube 27 is cured to form a glass sealed body. Thereby, each member is fixed and a diode package as shown in FIG. 30 is manufactured. Since the glass sealing body and the outer circumferences of the dumet electrodes 21 and 23 are bonded, the chip 15 positioned between the dumet electrode 21 and the dumet electrode 22 is hermetically sealed. The manufactured package is taken out from the assembly jig 25, a test for examining the polarity of the package is performed, the anode side and the cathode side of the package are discriminated, and marking is performed as necessary. In the process of mounting the package on the wiring board, the external leads 23 and 24 are connected to the wiring pattern of the wiring board via solder or the like.

(Embodiment 2)
The semiconductor device of the second embodiment is an LCD (Liquid Crystal Display) driver, for example. In the first embodiment, the case where the bump electrode BMP in the semiconductor chip 18 on which the diode element is formed is formed by the plating method has been described. However, in the second embodiment, the semiconductor chip on which the LCD driver is formed. A case where the bump electrode in FIG. 1 is formed by the same plating method as the plating method described in the first embodiment will be described.

  FIG. 31 shows an example of an overall plan view of the semiconductor chip CHP on which the LCD driver of the second embodiment is formed.

  The semiconductor chip CHP has, for example, a semiconductor substrate 31 formed in an elongated rectangular shape, and an LCD driver circuit for driving, for example, a liquid crystal display device is formed on the main surface thereof. This LCD driver circuit has a function of controlling the orientation of liquid crystal molecules by supplying a voltage to each pixel of the cell array of the LCD, and includes a gate drive circuit 33, a source drive circuit 34, a liquid crystal drive circuit 35, a graphic RAM ( Random Access Memory) 36 and a peripheral circuit 37. In the vicinity of the outer periphery of the semiconductor chip CHP, a plurality of pads PD are arranged at predetermined intervals along the outer periphery of the semiconductor chip CHP. The plurality of pads PD are arranged on an active region in which elements and wirings of the semiconductor chip CHP are arranged. Among the plurality of pads PD, there are a pad for an integrated circuit necessary for the configuration of the integrated circuit and a dummy pad that is not required for the configuration of the integrated circuit. The pads PD are staggered in the vicinity of one long side and two short sides of the semiconductor chip CHP. The plurality of pads arranged in a staggered pattern are mainly gate output signal pads and source output signal pads. A plurality of pads PD arranged in a zigzag at the center of the long side of the semiconductor chip CHP are pads for source output signals, and are arranged in a staggered manner near both corners of the long side of the semiconductor chip CHP and on both short sides of the semiconductor chip CHP. A plurality of pads PD are gate output signal pads. With such a staggered arrangement, it is possible to arrange a large number of gate output signal and source output signal pads while suppressing an increase in the size of the semiconductor chip CHP. That is, the chip size can be reduced and the number of pads (pins) can be increased. In addition, the plurality of pads PD arranged side by side in the vicinity of the other long side of the semiconductor chip CHP are not digitally arranged but are pads for digital input signals or analog input signals. Also, pads PD having relatively large planar dimensions are arranged in the vicinity of the four corners of the semiconductor chip CHP. This relatively large pad PD is a corner dummy pad. The plane dimension of the relatively small pad PD is, for example, about 35 μm × 50 μm. The plane size of the relatively large pad PD (corner dummy pad) is, for example, about 80 μm × 80 μm. The adjacent pitch of the pad PD is, for example, about 30 μm to 50 μm. The total number of pads PD is, for example, about 800.

  Bump electrodes for face-down bonding are formed on the pads PD of the semiconductor chip CHP by plating. For example, the bump electrodes are formed by using the various plating apparatuses described in the first embodiment with reference to FIGS. 5 to 25 (excluding FIGS. 9 to 14), and at the stage where the pads PD are formed, for each semiconductor substrate 31. It is formed in a lump.

  Next, a cross-sectional structure of the semiconductor chip CHP will be described with reference to FIGS. 32 and 33. FIG.

  The semiconductor substrate 31 is made of, for example, p-type single crystal Si, and an isolation region 32 is formed on the main surface of the device forming surface to define an active region La and a dummy active region Lb. The isolation | separation part 32 consists of a silicon oxide film formed, for example by the LOCOS (Local Oxidization of Silicon) method. However, the separation part 32 may be formed of a groove type (SGI: Shallow Groove Isolation or STI: Shallow Trench Isolation) separation part 32.

  For example, a pn junction diode D is formed in the active region La surrounded by the isolation part 32 of the substrate 1S under the pad PD1 shown in FIG. The pn junction diode D is, for example, a protection diode for preventing electrostatic breakdown, and is formed by a pn junction between the p-type well PWL of the semiconductor substrate 31 and the n-type semiconductor region 38 thereabove. On the main surface of the semiconductor substrate 31, an insulating film IS1 made of, for example, a silicon oxide film is formed. A first layer wiring M1 is formed thereon. The first layer wiring M1 has a configuration in which, for example, titanium, titanium nitride, aluminum (or aluminum alloy), and titanium nitride are sequentially deposited from the lower layer. This film of aluminum or aluminum alloy is the main wiring material and is formed to be the thickest. The first layer wiring M1 is connected to the n-type semiconductor region 38, that is, the pn junction diode D through a plurality of planar circular contact holes CNT formed in the insulating film IS1. First layer wiring M1 is covered with an insulating film IS2 made of, for example, a silicon oxide film. On the insulating film IS2, a second layer wiring M2 is formed. The material configuration of the second layer wiring M2 is the same as that of the first layer wiring M1. The second layer wiring M2 is electrically connected to the first layer wiring M1 through a plurality of planar circular through holes TH1 formed in the insulating film IS2. Second-layer wiring M2 is covered with an insulating film IS3 made of, for example, a silicon oxide film. A third layer wiring M3 is formed on the insulating film IS3. The third layer wiring M3 is electrically connected to the second layer wiring M2 through a plurality of planar circular through holes TH2 formed in the insulating film IS3. Further, most of the third layer wiring M3 is covered with a surface protecting insulating film IS4, but a part of the third layer wiring M3 is a planar rectangular opening formed in a part of the insulating film IS4. The portion 39 is exposed. The portion of the third layer wiring M3 exposed from the opening 39 is a pad PD1 (PD). The insulating film IS4 for surface protection is, for example, a single film of a silicon oxide film, a laminated film having a structure in which a silicon nitride film is stacked on a silicon oxide film, or a silicon nitride film and a polyimide film stacked on a silicon oxide film in order from the lower layer. It consists of a laminated film having a different structure. The pad PD1 (PD) is bonded to the bump electrode (projection electrode) 41 through the opening 39 through the base metal film 40. In addition to the function of improving the adhesion between the bump electrode 41 and the pad PD or the insulating film IS4, the base metal film 40 moves the metal element of the bump electrode 41 to the third layer wiring M3 side, and conversely the third layer. It is a film having a barrier function for suppressing or preventing the metal element of the wiring M3 from moving to the bump electrode 11 side. For example, a single film of a refractory metal film such as titanium or titanium tungsten, or a nickel film on the titanium film And a laminated film having a structure in which gold is stacked in order from the lower layer. The bump electrode 41 is made of, for example, an Au (gold) film, and is formed by, for example, a plating method.

  On the other hand, the dummy active region Lb is formed in the semiconductor substrate 31 below the dummy pad PD2 (PD) shown in FIG. 33 as described above, and no element is particularly formed in the dummy active region Lb. Absent. Of course, like other pads PD, diodes or other elements may be formed, or p-type wells, n-type wells, etc. may be provided. The second layer wiring M2 and the first layer wiring M1 below the dummy pad PD2 are electrically connected through a plurality of through holes TH1. Since the pad PD2 is a dummy, it is not necessary to electrically connect the second layer wiring M2 and the first layer wiring M1 below the pad PD2. A plurality of through holes TH1 are also arranged in the lower layer of the pad PD2 so as to be closer to the height of the top side of the bump electrode 41 bonded to the other pad PD.

  Next, an example of the manufacturing process of this semiconductor device will be described. First, the isolation part 32 is formed on the main surface of the semiconductor substrate 31 in the form of a semiconductor wafer by, for example, the LOCOS method, the active region La and the dummy active region Lb are formed, and then an element is formed in the active region La surrounded by the isolation part 32 Form. No element is formed in the dummy active region Lb under the dummy pad PD2. Subsequently, an insulating film IS1 is deposited on the main surface of the semiconductor substrate 31 by a CVD (Chemical Vapor Deposition) method or the like, and then a planar circular contact hole CNT is formed at a predetermined position of the insulating film IS1 by photolithography and dry etching. Form by technology. After that, for example, a titanium nitride film, a titanium film, an aluminum film, and a titanium nitride film are sequentially deposited on the insulating film IS1 from the lower layer by sputtering or the like, and then the laminated metal film is patterned by a photolithography technique and a dry etching technique. Thus, the first layer wiring M1 is formed. Next, an insulating film IS2 is similarly deposited on the insulating film IS1, a through hole TH1 is formed in the insulating film IS2, and then a second layer wiring M2 is formed on the insulating film IS2 in the same manner as the first layer wiring M1. Subsequently, an insulating film IS3 is similarly deposited on the insulating film IS2, a through hole TH2 is formed in the insulating film IS3, and then a third layer wiring M3 is formed on the insulating film IS3 in the same manner as the first layer wiring M1. . Thereafter, an insulating film IS4 for surface protection is deposited on the insulating film IS3, and then an opening 39 in which a part of the third layer wiring M3 is exposed is formed in the insulating film IS4 to form a pad PD. Next, a conductor film made of a laminated film having a structure in which a nickel film and a gold film are stacked in order from the lower layer on the insulating film IS4, for example, a single film of a refractory metal film such as titanium or titanium tungsten or the like on the titanium film. After being deposited by sputtering or the like, a photoresist pattern is formed so that the bump formation region is exposed and the others are covered thereon.

  Next, bump electrodes 41 made of, for example, gold are formed. As described above, the bump electrode 41 is formed by using the various plating apparatuses and non-cyanide plating solutions described in the first embodiment with reference to FIGS. 5 to 25 (excluding FIGS. 9 to 14). It can be formed by depositing an Au film using a photoresist film (masking film) 42 (see FIG. 34) provided with an opening by lithography as a mask.

  Next, the photoresist film 42 is removed, and the underlying conductor film is removed by etching to form the underlying metal film 40. Thereafter, the semiconductor substrate 31 is cut into each semiconductor chip CHP, and the semiconductor device of the second embodiment is manufactured.

  Also in the second embodiment, when the bump electrode 41 is formed by a plating method using a non-cyan plating solution, the surface of the bump electrode 41 is the same as the bump electrode BMP (see FIG. 4) in the first embodiment. It is possible to prevent the formation of concave waviness and roughness. On the other hand, when such waviness and roughness are formed on the surface of the bump electrode 41, the semiconductor chip CHP is mounted on the mounting substrate 45 using the anisotropic conductive sheet 44 having the conductive particles 43. At this time (see FIG. 35), there is a possibility that the area where the bump electrode 41 and the conductive particles 43 are in contact with each other is reduced between the electrode (second electrode) 46 provided on the mounting substrate and the bump electrode 41. is there. When the contact area becomes small, there is a concern that the resistance value increases at the electrical connection portion between the bump electrode 41 and the electrode 46. However, according to the second embodiment, it is possible to prevent the above-described undulation and roughness from occurring on the surface of the bump electrode 41, so that a large area where the bump electrode 41 and the conductive particles 43 are in contact is ensured. be able to. That is, the resistance value at the electrical connection portion between the bump electrode 41 and the electrode 46 can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, the bump electrode is formed from an Ag film formed by a plating method using a non-cyan plating solution. However, the bump electrode is formed by a plating method using a non-cyan plating solution. You may form from Au film | membrane, Cu (copper) film | membrane, Pb (lead) film | membrane, or a solder film | membrane.

  In the embodiment, the bump electrode is formed by a plating method using a non-cyan plating solution. However, the film formation by the plating method using the non-cyan plating solution described in the embodiment is performed. The technique can be used in a process of depositing a metal film in a technique of forming a wiring by forming a groove for forming a wiring in an insulating film deposited on a semiconductor substrate and embedding the metal film in the groove, for example. . In that case, it is possible to prevent so-called dishing (dents) from occurring on the surface of the wiring.

  The method for manufacturing a semiconductor device of the present invention can be applied to a manufacturing process of a semiconductor device having a bump electrode (projection electrode).

It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; It is explanatory drawing of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a perspective view of the bathtub type plating apparatus used during the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is the top view which looked at the bathtub type plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention from upper direction. It is principal part sectional drawing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is explanatory drawing shown about the surface wave | undulation of the bump electrode in the semiconductor device of Embodiment 1 of this invention. It is explanatory drawing shown about the roughness of the surface of the bump electrode in the semiconductor device of Embodiment 1 of this invention. It is principal part sectional drawing explaining the process of forming the bump electrode in the semiconductor device of Embodiment 1 of this invention. It is explanatory drawing of the cross section of the bump electrode formed without grinding | polishing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is explanatory drawing of the cross section of the bump electrode formed while grinding | polishing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is explanatory drawing of the cross section of the bump electrode formed while grinding | polishing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part perspective view of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is principal part sectional drawing of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is principal part sectional drawing of the plating apparatus used in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; It is principal part sectional drawing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; It is principal part sectional drawing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is a principal part top view of the semiconductor device of Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor device of Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor device of Embodiment 2 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of Embodiment 2 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of Embodiment 2 of this invention.

Explanation of symbols

1 n-type high concentration substrate (semiconductor wafer)
2 n-type low concentration layer 3 silicon oxide film 6 opening 7 p-type diffusion layer 9 oxide film 10 surface protective film 11 contact hole 12 surface electrode 13 surface final protective film 17 back electrode 18 semiconductor chip 21 jumet electrode 22 jumet electrode (first electrode) 2 electrodes)
23, 24 External lead 25 Assembly jig 26, 26A, 26B Hole 27 Glass tube 31 Semiconductor substrate (semiconductor wafer)
32 Separation unit 33 Gate drive circuit 34 Source drive circuit 35 Liquid crystal drive circuit 36 Graphic RAM
37 Peripheral circuit 38 N-type semiconductor region 39 Opening 40 Base metal film 41 Bump electrode (projection electrode)
42 Photoresist film (masking film)
43 Conductive Particles 44 Anisotropic Conductive Sheet 45 Mounting Board 46 Electrode (Second Electrode)
ADS adsorption member BMP Bump electrode (projection electrode)
BOH Discharge port CBD Carbon dish CHP Semiconductor chip CNT Contact hole D pn junction diode ECR Ag electrode HLD, HLD2 Holder IS1, IS2, IS3, IS4 Insulating film La Active region Lb Dummy region M1 First layer wiring M2 Second layer wiring M3 First Three-layer wiring PD, PD1, PD2 Pad PDS Pedestal PLS Polishing member (polishing means)
PLS2, PLS3 Polishing tools (polishing means)
POR Porous member PS Power supply PTL Plating solution PWL P-type well STG Stage TB1 Bathtub TH1, TH2 Through hole UBM Metal film

Claims (3)

A method for manufacturing a semiconductor device having a protruding electrode formed by plating,
(A) forming a masking film on the main surface of the semiconductor wafer and forming a plurality of openings in the masking film;
(B) Growing a metal film from within the plurality of openings while rubbing the main surface of the semiconductor wafer with friction means while supplying a non-cyan plating solution to the main surface of the semiconductor wafer, A step of forming a plurality of protruding electrodes from
A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device having a protruding electrode formed by plating,
(A) forming a masking film on the main surface of the semiconductor wafer and forming a plurality of openings in the masking film;
(B) Growing a metal film from within the plurality of openings while rubbing the main surface of the semiconductor wafer with friction means while supplying a non-cyan plating solution to the main surface of the semiconductor wafer, A step of forming a plurality of protruding electrodes from
(C) cutting the semiconductor wafer and dividing it into individual semiconductor chips, and then connecting the protruding electrode to the second electrode;
A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device having a protruding electrode formed by plating,
(A) forming a masking film on the main surface of the semiconductor wafer and forming a plurality of openings in the masking film;
(B) Growing a metal film from within the plurality of openings while rubbing the main surface of the semiconductor wafer with friction means while supplying a non-cyan plating solution to the main surface of the semiconductor wafer, A step of forming a plurality of protruding electrodes from
Including
The step (b)
(B1) The friction means is operated while supplying the plating solution to the main surface of the semiconductor wafer in a state where the arrangement position of the semiconductor wafer is fixed. Rubbing the surface,
(B2) By operating the semiconductor wafer while supplying the plating solution to the main surface of the semiconductor wafer in a state in which the arrangement position of the friction means is fixed, the friction means causes the main of the semiconductor wafer to move. Rubbing the surface,
(B3) rubbing the main surface of the semiconductor wafer with the friction means by operating both the semiconductor wafer and the friction means while supplying the plating solution to the main surface of the semiconductor wafer;
A method for manufacturing a semiconductor device, comprising:

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