JP2005243714A - Electrode bump, its manufacturing method and its connecting method - Google Patents

Electrode bump, its manufacturing method and its connecting method Download PDF

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JP2005243714A
JP2005243714A JP2004048252A JP2004048252A JP2005243714A JP 2005243714 A JP2005243714 A JP 2005243714A JP 2004048252 A JP2004048252 A JP 2004048252A JP 2004048252 A JP2004048252 A JP 2004048252A JP 2005243714 A JP2005243714 A JP 2005243714A
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electrode
bump
electrode bump
semiconductor chip
manufacturing
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JP4480417B2 (en
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Tanemasa Asano
種正 浅野
Naoya Watanabe
直也 渡辺
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Japan Science and Technology Agency
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode bump, its manufacturing method and a connecting method which allows many electrodes to be connected surely for electrical connection between semiconductor chips after laminating them, and ensures a high operation reliability of semiconductor elements, such as transistors located on and around connection points. <P>SOLUTION: The top end 1b of the electrode bump 1 is formed more yieldingly to stresses than its base 1a. Hence, the electrode bump 1, disposed on the electrode pad 2 of a semiconductor chip 10-12, is pressed against another semiconductor chip to buckle and deform the top end 1b, and the pressing stress is absorbed by buckling and deforming the top end 1b to resulting in no stress being applied directly to each semiconductor chip 10-12. This reliably and easily executes the electric connection and prevents the stress in the connecting operation to the semiconductor chips 10-12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体チップを他の半導体チップ又は回路基板も電気的に接続する電極バンプに関し、特に微細化又は積層化する半導体チップに対応した電極バンプ及びこの電極バンプの製造方法並び接続方法に関する。   The present invention relates to an electrode bump for electrically connecting a semiconductor chip to another semiconductor chip or a circuit board, and more particularly to an electrode bump corresponding to a semiconductor chip to be miniaturized or stacked, a manufacturing method of the electrode bump, and a connection method.

近年、情報機器の高機能化、小型化が将来たりとも進むと見込まれ、またディジタル情報家電の普及が台頭するなか、半導体装置の小型化、信号処理速度の向上、他機能化の実現を目的とした技術開発に対する要望が高まっている。それを実現する概念の一つに、システム・イン・パッケージ（省略、ＳｉＰ）がある。このＳｉＰは、一つのパッケージの中に複数の半導体チップを内蔵させて小型化を図る、或いはシステムとしての機能を持たせるものである。一つの半導体チップの中に、複数の機能を設計して作りこむ、いわゆるシステム・オン・チップも有力な手法的概念であるが、ＳｉＰの方が内蔵する半導体チップとその機能の多様性に富み、かつ低価格で製造できると見込まれている。   In recent years, it is expected that information devices will have higher functionality and smaller size in the future, and with the rise of digital information home appliances, the purpose is to reduce the size of semiconductor devices, improve signal processing speed, and realize other functions. There is a growing demand for technical development. One concept that realizes this is system-in-package (abbreviation, SiP). This SiP is intended to reduce the size by incorporating a plurality of semiconductor chips in one package, or to have a system function. The so-called system-on-chip, in which multiple functions are designed and created in a single semiconductor chip, is also a powerful methodic concept, but the semiconductor chip built into SiP and the diversity of its functions are richer. It is expected to be manufactured at a low price.

複数の半導体チップを一つのパッケージに内蔵させる形態の一つに、半導体チップを積層化する方法が考えられる。この半導体チップの積層化は、小型化のみならず、配線の長さを短くできるため、配線での信号伝播の遅延を最小化にできることから、高速の信号処理を要する半導体装置、高周波信号を扱う半導体装置或いはシステムの集積化技術として大きな期待が寄せられている。システムの高機能化に伴い、積層する半導体チップ間の電気的な接続を行う電極の数が多くなり、電極間の距離も小さくなる。   One method for incorporating a plurality of semiconductor chips in one package is to stack the semiconductor chips. This stacking of semiconductor chips not only reduces the size but also shortens the length of the wiring, so that the delay of signal propagation in the wiring can be minimized, so that semiconductor devices requiring high-speed signal processing and high-frequency signals are handled. There is great expectation as a technology for integrating semiconductor devices or systems. As the function of the system increases, the number of electrodes for electrical connection between stacked semiconductor chips increases, and the distance between the electrodes also decreases.

また、半導体チップ間の接続に用いられる電極バンプ及びこの製造方法並びこの接続方法の応用製品としては、半導体装置を利用する全ての電子機器に適用できるが、具体的には第１に高速に撮像と画像処理のできる撮像装置（いわゆるビジョンチップ等）とその応用製品であるロボット、第２に携帯情報端末（携帯電話を含む）、コンピュータ機器、第３に高周波（ＲＦ）ＩＤタグ、第４に通信用電子機器、第５に 自動車の自動走行用電子機器（例えば物体認識用レーダ等）、第６にディジタル情報家電製品のような製品に有効であり、その工業的価値は高いと見込まれる。   In addition, the electrode bumps used for the connection between the semiconductor chips, the manufacturing method thereof, and the application products of this connection method can be applied to all electronic devices using semiconductor devices. Specifically, first, imaging is performed at high speed. And image processing devices capable of image processing (so-called vision chips, etc.) and their application products, robots, secondly, personal digital assistants (including mobile phones), computer equipment, thirdly radio frequency (RF) ID tags, fourthly It is effective for electronic devices for communication, fifthly, electronic devices for automatic driving of automobiles (for example, radar for object recognition), and sixthly, products such as digital information home appliances, and its industrial value is expected to be high.

従来、この種の電極バンプ、その製造方法及びその接続方法は、特開平６−２２４２５８号公報（第１の従来技術）、特開平１１−２５１３５６号公報（第２の従来技術）、特開平１１−３３０６８２号公報（第３の従来技術）及び特開平１３−１９６４１４号公報（第４の従来技術）に開示されるものがあり、その他に特開平５−１３６２０１号、特開平６−１６３６３４号公報に示されるものがある。   Conventionally, this kind of electrode bump, its manufacturing method and its connection method are disclosed in Japanese Patent Application Laid-Open No. 6-224258 (first prior art), Japanese Patent Application Laid-Open No. 11-251356 (second prior art), No. -330682 (third prior art) and Japanese Unexamined Patent Publication No. 13-196414 (fourth prior art), and others are disclosed in Japanese Patent Laid-Open Nos. 5-136201 and 6-163634. There is what is shown in.

前記第１の従来技術に係る半導体装置の製造方法は、金属突起用基板上に形成された金属突起（電極バンプに相当）と半導体素子Ａｌ電極とを接触させた状態で押圧，加熱し、金属突起とＡｌ電極とを合金化して接合した後、金属突起をＡｌ電極に転写し、この後に金属突起と配線電極とを接触させた状態で、前工程よりも高押圧力，高温又は長時間の押圧，加熱により、金属突起と配線電極とを再度合金化させ、その後、金属突起と配線電極とを光硬化性絶縁樹脂で固着して接続し、これにより、配線電極との接続前の金属突起の大変形を防ぎながら、Ａｌ電極・金属突起間の接合強度を強固にするという構成である。   The method of manufacturing a semiconductor device according to the first prior art includes pressing and heating a metal protrusion (corresponding to an electrode bump) formed on a metal protrusion substrate and a semiconductor element Al electrode in contact with each other. After the protrusion and the Al electrode are alloyed and joined, the metal protrusion is transferred to the Al electrode, and then the metal protrusion and the wiring electrode are in contact with each other with a higher pressing force, higher temperature or longer time than the previous process. By pressing and heating, the metal protrusion and the wiring electrode are re-alloyed, and then the metal protrusion and the wiring electrode are fixedly connected with a photo-curing insulating resin, thereby connecting the metal protrusion before the connection with the wiring electrode. In this configuration, the bonding strength between the Al electrode and the metal protrusion is strengthened while preventing large deformation of the metal.

このように構成することにより半導体素子の電極上に金属突起を容易でかつ低コストで形成する転写方式をフリップチップ方式やＭＢＢ方式に適用する際にきわめて接続信頼性を高くできることとなる。   With such a configuration, connection reliability can be extremely increased when a transfer method for forming metal protrusions on the electrodes of a semiconductor element easily and at low cost is applied to the flip chip method and the MBB method.

前記第２の従来技術に係るワイヤバンプの形成方法は、ワイヤを溶解させその先端に球状体を形成すると共に、ベアチップの電極と前記球状体の少なくとも一方の表面をハロゲン化し、前記電極と前記球状体とをハロゲン化面を介して相互に接合させ個体接合をなした後は、前記球状体と前記ワイヤとを切断分離し、前記電極上に前記球状体を残留させる構成である。   In the wire bump forming method according to the second prior art, the wire is melted to form a spherical body at the tip thereof, and at least one surface of the bare chip electrode and the spherical body is halogenated, and the electrode and the spherical body are formed. Are bonded to each other via a halogenated surface, and after the solid bonding, the spherical body and the wire are cut and separated, and the spherical body remains on the electrode.

この構成に基づく第２の従来技術は、接続を行う際に超音波振動を用いる必要がなくなるので、隣合う部材との接触するのを防止でき、ベアチップの狭ピッチ化を促進させることができると共に、接続条件を緩和させることができる。   The second prior art based on this configuration eliminates the need to use ultrasonic vibration when making connections, so that contact with adjacent members can be prevented, and the narrow pitch of bare chips can be promoted. The connection conditions can be relaxed.

前記第３の従来技術に係る突起電極（電極バンプに相当）の形成方法及び形成装置並びに突起電極の形成部品は、接合対象となるＩＣと半田ボールとが、フッ化処理部においてＨＦガス供給部からのＨＦガスと、水蒸気発生部からの水蒸気との混合ガスにさらされ、前記ＩＣ及び半田ボールの表面がフッ化されたのち、接合処理部に配置され、その後、チャンバ内をＡｒガス雰囲気にし、接続用導通部と半田ボールとをシリンダによって加圧するとともに、ヒータによって両者の融点以下に加熱して接合する構成である。   A method and apparatus for forming a protruding electrode (corresponding to an electrode bump) and a component for forming a protruding electrode according to the third prior art include an IC to be bonded and a solder ball in an HF gas supply unit in a fluorination processing unit. After being exposed to a mixed gas of HF gas from the water vapor and water vapor from the water vapor generating part, the surfaces of the IC and the solder balls are fluorinated, and then placed in the bonding processing part. The connection conducting portion and the solder ball are pressurized by a cylinder and heated to a temperature equal to or lower than the melting point of the two by a heater and joined.

この構成に基づく従来技術は、突起電極の形成時においてフラックスを必要とせず、また突起電極の形成のために共通電極を設けるなどの制約がなくなることとなる。   The prior art based on this configuration does not require a flux when forming the protruding electrode, and there is no restriction such as providing a common electrode for forming the protruding electrode.

前記第４の従来技術に係る半導体装置は、半導体チップに形成された銅からなる外部接続端子と、基板に形成されてなる外部接続端子とが接続されてなり、前記外部接続端子部と前記接続端子との少なくともいずれか一方がハロゲン化処理されてなり、両者が固着接合して構成される。   In the semiconductor device according to the fourth prior art, an external connection terminal made of copper formed on a semiconductor chip and an external connection terminal formed on a substrate are connected, and the external connection terminal portion and the connection are connected. At least one of the terminals is halogenated, and both are fixedly joined.

この構成に基づく第４の従来技術は、ハロゲン処理により半導体チップの外部接続端子部又は基板の接続端子の表面に金属と結合しやすいハロゲンを存在させたことにより、導電性に優れた銅の配線に、金ワイヤやＴＡＢ（Tape Automated Bonding）のインナーリード等基板の接続端子を直接接続することが可能で、配線抵抗を小さくすることができ、応答性に優れると共に発熱量を小さくすることができる。
特開平６−２２４２５８号公報（第１の従来技術） 特開平１１−２５１３５６号公報（第２の従来技術） 特開平１１−３３０６８２号公報（第３の従来技術） 特開平１３−１９６４１４号公報（第４の従来技術） 特開平５−１３６２０１号 特開平６−１６３６３４号 The fourth prior art based on this configuration is a copper wiring having excellent conductivity by the presence of halogen that is easily bonded to metal on the surface of the external connection terminal portion of the semiconductor chip or the connection terminal of the substrate by halogen treatment. In addition, it is possible to directly connect a connection terminal of a substrate such as an inner lead of a gold wire or TAB (Tape Automated Bonding), it is possible to reduce the wiring resistance, it is excellent in responsiveness and the calorific value can be reduced. .
JP-A-6-224258 (first prior art) Japanese Patent Laid-Open No. 11-251356 (second prior art) Japanese Patent Laid-Open No. 11-330682 (Third Prior Art) Japanese Patent Laid-Open No. 13-196414 (fourth prior art) JP-A-5-136201 JP-A-6-163634

前記各従来の技術において、電極バンプを用いて半導体チップに対する電気的接続を実現する方法として、ハンダを球状にした電極バンプを用いる方法、金を半球状にした電極バンプ（スタッドバンプと呼ばれる）を用いて接続する方法等があり、プリント基板等の回路基板への半導体チップの直接接続、或いはパッケージ内に半導体チップを内蔵して接続する方法等が実用化されている。しかし、このような球状の電極バンプの大きさは現状、小さくても１００ミクロン程度であり、半導体チップを積層化する場合に要求される、１０ミクロン程度の電極バンプの大きさには対応できないという課題を有する。これは予め球状に形成したボールを半導体チップの上に配置して電極バンプを形成する方法においては、ハンダボールの微細化に限界があること、クリーム状のハンダをスクリーン印刷した後にリフローして球状にする場合には印刷における解像度の向上に多くの技術的困難が存在するという理由からである。   In each of the above conventional techniques, as a method for realizing electrical connection to a semiconductor chip using electrode bumps, a method using electrode bumps made of solder in a spherical shape, an electrode bump made of gold in a hemisphere (called a stud bump) There is a method of using and connecting them, and a method of connecting a semiconductor chip directly to a circuit board such as a printed board or a method of connecting a semiconductor chip in a package has been put into practical use. However, the size of such a spherical electrode bump is currently about 100 microns at the smallest, and cannot meet the size of about 10 microns required for stacking semiconductor chips. Has a problem. This is because, in the method of forming electrode bumps by arranging balls formed in advance on a semiconductor chip, there is a limit to the miniaturization of the solder balls, and after reflowing the cream-like solder after screen printing, This is because there are many technical difficulties in improving the resolution in printing.

このような理由のため、高密度の電気的接続を実現するためには、鍍金技術等の成膜技術によって電極バンプを形成する必要があるが、高密度の電極バンプを持つ半導体チップの接続を、メッキ法で電極バンプを形成して半導体チップの積層接続を行う場合には以下の課題を有する。   For these reasons, in order to realize high-density electrical connection, it is necessary to form electrode bumps by film-forming technology such as plating technology, but it is necessary to connect semiconductor chips having high-density electrode bumps. When the electrode bumps are formed by plating and semiconductor chips are stacked and connected, the following problems are encountered.

まず、第１に電極バンプの高さが不揃いとなるために、電極バンプ間の距離が小さくなる（即ち高密化する）と、高さの高い電極バンプのみが接続されやすくなり、多数の電極バンプに対して一様な接続が困難となるという課題を有する。これを接続するためには、電極バンプを変形させればよいが、鍍金等の成膜技術で通常形成される平板状の構造を持つ電極バンプでは、変形させるには大きな荷重を加える必要があり、接合装置の設計、製造に技術的障壁が発生するという課題を有する。   First, since the heights of the electrode bumps are not uniform, when the distance between the electrode bumps is reduced (that is, the density is increased), only the electrode bumps having a high height are easily connected, and a large number of electrode bumps are formed. However, there is a problem that uniform connection becomes difficult. In order to connect them, the electrode bumps may be deformed. However, it is necessary to apply a large load to deform the electrode bumps having a plate-like structure usually formed by a film forming technique such as plating. In addition, there is a problem that a technical barrier occurs in the design and manufacture of the bonding apparatus.

次に、第２に、仮に大きな荷重を加えて接合が可能になったとしても、高密度に電極バンプを配置する場合には、電極バンプ間の距離が小さくなるために半導体チップに大きな応力が発生していまい、半導体チップ内のトランジスタ等の特性が変化してしまい、回動動作に支障を与えるという課題を有する。   Second, even if a large load is applied and bonding becomes possible, when the electrode bumps are arranged at a high density, the distance between the electrode bumps becomes small, so that a large stress is applied to the semiconductor chip. It does not occur, and the characteristics of the transistors and the like in the semiconductor chip change, resulting in a problem that the rotation operation is hindered.

また、第３に半導体チップを積層する場合に、電極バンプによる電気的接点が半導体チップ動作中の温度上昇に伴う熱変形で破壊されるのを防ぐために、機械的補強のための樹脂を半導体チップ間に挿入する必要があるが、メッキ法で形成する電極バンプの高さが小さくなるために、積層接続した半導体チップ間の間隙は小さくなり接合後に半導体チップ間に樹脂（アンダーファイルとよがれる）を流し込みのが困難になるという課題を有する。   Third, when a semiconductor chip is stacked, a resin for mechanical reinforcement is added to the semiconductor chip in order to prevent the electrical contacts due to the electrode bumps from being destroyed by the thermal deformation accompanying the temperature rise during the operation of the semiconductor chip. Although it is necessary to insert them in between, the height of the electrode bumps formed by the plating method is reduced, so the gap between the stacked semiconductor chips is reduced and the resin between the semiconductor chips after bonding (called an under file) ) Is difficult to pour.

そのため、接合前に非導電性の樹脂を一方の半導体チップ面上に半導体チップ面全体に滴下或いは塗布しておき、その上に別の半導体チップを積層して接合する方法が有力な方法となる。この場合、電極バンプの電気的な接合は、電極バンプが非導電性樹脂を押しのけて金属間接合が図れることになる。メッキ法等の成膜法で形成した電極バンプでは、形状が平板状であることに加えて電極バンプ上面が平坦ではないことから、電極バンプと相手側金属膜との間に非導電性樹脂を噛み込むとう問題を生じ、これは接合不良や接合の信頼性の低下につながるという課題を有する。   For this reason, a method in which a non-conductive resin is dropped or applied on the entire semiconductor chip surface on one semiconductor chip surface before bonding, and another semiconductor chip is stacked and bonded on the semiconductor chip surface is a powerful method. . In this case, as for the electrical bonding of the electrode bumps, the electrode bumps can push the non-conductive resin to achieve metal-to-metal bonding. In electrode bumps formed by film-forming methods such as plating, the shape of the electrode bumps is flat and the upper surface of the electrode bumps is not flat, so a non-conductive resin is placed between the electrode bumps and the counterpart metal film. The problem of biting occurs, and this has the problem that it leads to poor bonding and reduced bonding reliability.

更に、第４に異方性導電膜（Anisotropic Conductive Film, ACF）を介在させて電気的接続を図る図る場合に、鍍金により形成した電極バンプのように平板状の電極バンプでは、微細化すると大きさの２乗に反比例して接続面積が小さくなるために、高密度に配置する微細に電極バンプでは接合不良や接合部の抵抗が大きくなるという課題を有する。   Furthermore, fourthly, when an electrical connection is to be made by interposing an anisotropic conductive film (ACF), a flat electrode bump such as an electrode bump formed by plating is large when it is miniaturized. Since the connection area decreases in inverse proportion to the square of the length, there is a problem in that the bonding failure and the resistance of the bonding portion increase in the fine electrode bumps arranged at high density.

本発明は、半導体チップを積層してチップ間の電気的な接続を行う際に、多数の電極を確実に接続でき、また接続点及びその周辺に位置するトランジスタ等の半導体素子の動作に対し高い信頼性を保証できる電極バンプ及びその製造方法並びに接続方法を提供することを目的とする。   The present invention can reliably connect a large number of electrodes when stacking semiconductor chips and electrically connecting the chips, and is high in operation of semiconductor elements such as transistors located at and around the connection point. An object of the present invention is to provide an electrode bump capable of guaranteeing reliability, a manufacturing method thereof, and a connection method.

本発明に係る電極バンプは、半導体チップの電極パッド上に配設され、他の半導体チップ又は回路基板の電極パッドに当接して接続する電極バンプにおいて先端部が基部より応力変形を大きく形成されるものである。   The electrode bump according to the present invention is disposed on the electrode pad of the semiconductor chip, and the tip portion of the electrode bump that is in contact with and connected to the electrode pad of another semiconductor chip or circuit board is formed to have greater stress deformation than the base. Is.

本発明に係る電極バンプは必要に応じて、基部から先端部に向かって先細状の錐形状にて形成されることをものである。   The electrode bump according to the present invention is formed in a tapered cone shape from the base portion to the tip portion as necessary.

本発明に係る電極バンプは必要に応じて、対応する凹形状の凹部を複雑連設される鋳型に金属バンプ材を充填して形成するものである。   The electrode bump according to the present invention is formed by filling a metal bump material into a mold in which corresponding concave-shaped concave portions are arranged in a complex manner as necessary.

本発明に係る電極バンプの製造方法は、前記鋳型に金属バンプ材を堆積させ、当該堆積した金属バンプ材を前記各凹部相互間の境界部分が露出するまで切削するものである。   In the method for producing an electrode bump according to the present invention, a metal bump material is deposited on the mold, and the deposited metal bump material is cut until a boundary portion between the recesses is exposed.

本発明に係る電極バンプの製造方法は必要に応じて、前記鋳型の凹部に導電性のシード層を形成し、当該シード層に電解鍍金を施して各凹部に金属バンプ材を充填するものである。   In the electrode bump manufacturing method according to the present invention, a conductive seed layer is formed in the recess of the mold, if necessary, and electrolytic plating is applied to the seed layer to fill each recess with a metal bump material. .

本発明に係る電極バンプの製造方法は必要に応じて、前記鋳型の表面に導電性のシード層を形成し、当該シード層上の前記凹部以外の境界部分に非導電性のレジスト層を積層形成し、前記シード層が露出部分の各凹部に電解鍍金を施して各凹部に金属バンプ材を充填するものである。   In the electrode bump manufacturing method according to the present invention, if necessary, a conductive seed layer is formed on the surface of the mold, and a non-conductive resist layer is formed on the boundary portion other than the concave portion on the seed layer. Then, the seed layer is subjected to electrolytic plating in each concave portion of the exposed portion, and each concave portion is filled with a metal bump material.

本発明に係る電極バンプの製造方法は必要に応じて、鋳型がシリコンの結晶面間による化学的蝕刻性の違いにより凹部を形成されるものである。   In the electrode bump manufacturing method according to the present invention, the concave portion is formed by the difference in chemical etchability between the crystal planes of the silicon as required.

本発明に係る電極バンプの製造方法は必要に応じて、鋳型が、樹脂表面の部分加圧により凹部を形成されるものである。   In the method for producing an electrode bump according to the present invention, the mold is formed with a concave portion by partial pressurization of the resin surface as necessary.

本発明に係る電極バンプ接続方法は、電極バンプが、先端部を他の半導体チップ間又は回路基板の電極パッドに当接座屈して接続するものである。   In the electrode bump connecting method according to the present invention, the electrode bumps are connected by buckling the tip portion between other semiconductor chips or electrode pads of the circuit board.

本発明に係る電極バンプの接続方法は必要に応じて、半導体チップと他の半導体チップ又は回路基板との間に非導電性樹脂を介在させた状態で前記先端部を押圧して座屈させるものである。   In the electrode bump connection method according to the present invention, if necessary, the tip portion is pressed and buckled with a non-conductive resin interposed between the semiconductor chip and another semiconductor chip or circuit board. It is.

本発明に係る電極バンプの接続方法は必要に応じて、半導体チップと他の半導体チップ又は回路基板との間に異方性導電膜を介在させた状態で前記先端部を押圧して座屈させるものである。   In the electrode bump connection method according to the present invention, if necessary, the tip portion is pressed and buckled with an anisotropic conductive film interposed between a semiconductor chip and another semiconductor chip or a circuit board. Is.

本発明の電極バンプの接続方法は必要に応じて、電極バンプにハロゲン元素を付着させ、当該ハロゲン元素が付着した電極バンプを座屈して接続するものである。   In the electrode bump connection method of the present invention, a halogen element is attached to the electrode bump as necessary, and the electrode bump to which the halogen element is attached is buckled and connected.

本発明に係る電極バンプは、先端部が基部より応力変化を大きく形成されることから、半導体チップの電極パッドに配設された電極バンプを他の半導体チップ又は回路基板に押圧して先端部を座屈変形させ、押圧応力を先端部の座屈変形で吸収して各半導体チップ又は回路基板へ直接印加されることがなくなり、電気的接続を確実且つ容易に実行できると共に、半導体チップ及び回路基板への接続動作時のストレスを防止できる。   In the electrode bump according to the present invention, the tip portion is formed to have a larger stress change than the base portion. Therefore, the electrode bump disposed on the electrode pad of the semiconductor chip is pressed against another semiconductor chip or the circuit board, and the tip portion is pressed. The buckling deformation is applied and the pressing stress is absorbed by the buckling deformation of the tip portion and is not directly applied to each semiconductor chip or circuit board, so that electrical connection can be reliably and easily performed, and the semiconductor chip and circuit board It is possible to prevent stress during the connection operation.

また、本発明に係る電極バンプは、基部から先端部に向かって先細状の錐形状にて形成されることから、先細状の先端部が押圧力により容易に変形して座屈できることとなり、対向する他の半導体チップ及び回路基板への接合に伴う特性変動を最小限に止めることができる。特に、他の半導体チップ又は回路基板に対する電極バンプの高さが不揃いで形成されて複数配列された場合であっても、全ての電極バンプを確実且つ容易に接続することができる。   In addition, since the electrode bump according to the present invention is formed in a tapered cone shape from the base portion toward the tip portion, the tapered tip portion can be easily deformed and buckled by the pressing force, and facing It is possible to minimize the characteristic variation associated with bonding to other semiconductor chips and circuit boards. In particular, even when a plurality of electrode bumps are formed with irregular heights with respect to other semiconductor chips or circuit boards and are arranged in a plurality, it is possible to reliably and easily connect all the electrode bumps.

また、本発明に係る電極バンプの製造方法は、基部から先端部に向かって先細となる凹形状の凹部が複数連設される鋳型に金属バンプ材を充填させることにより電極バンプを形成することから、同一形状の電極バンプを均一且つ正確に形成できる。このように電極バンプを均一且つ正確な寸法精度で製作することにより、各半導体チップを押圧して電極バンプを座屈変形させる場合に、最小限の押圧力で多数の電極バンプを確実に変形させて接続することができる。   In addition, the electrode bump manufacturing method according to the present invention forms an electrode bump by filling a metal bump material into a mold in which a plurality of concave recesses tapering from the base toward the tip. The electrode bumps having the same shape can be formed uniformly and accurately. By manufacturing electrode bumps with uniform and accurate dimensional accuracy in this way, when each semiconductor chip is pressed and the electrode bumps are buckled and deformed, a large number of electrode bumps can be reliably deformed with minimum pressing force. Can be connected.

また、本発明に係る電極バンプの製造方法は、金属バンプ材を鋳型表面にに堆積させて、この堆積した金属バンプ材を各凹部相互間の境界部分が露出するまで切削するようにしているので、電極バンプの底面を均一な平滑面とすることができることとなり、電極バンプの高さを高精度に一致させることができる。   In the electrode bump manufacturing method according to the present invention, the metal bump material is deposited on the mold surface, and the deposited metal bump material is cut until the boundary portion between the recesses is exposed. The bottom surface of the electrode bump can be made uniform and smooth, and the height of the electrode bump can be matched with high accuracy.

また、本発明に係る電極バンプの製造方法は、鋳型の各凹部に導電性のシード層を形成してこのシード層の電解鍍金を施して各凹部に金属バンプ材を充填するようにしているので、より微細に電極バンプを形成できると共に、正確な高さに形成できる。   In the method of manufacturing the electrode bump according to the present invention, a conductive seed layer is formed in each concave portion of the mold, and electrolytic plating of the seed layer is performed to fill each concave portion with a metal bump material. The electrode bumps can be formed more finely and can be formed at an accurate height.

また、本発明に係る電極バンプの製造方法は、鋳型の表面全面に導電性のシード層上の凹部以外の境界部分に非導電性のレジスト層を積層形成し、前記露出しているシード層に対して電解鍍金を施すことにより各凹部に金属バンプ材を充填して電極バンプを形成するようにしているので、より微細に電極バンプを形成できると共に、正確な高さに形成できる。   In the electrode bump manufacturing method according to the present invention, a non-conductive resist layer is laminated on the entire surface of the mold at a boundary portion other than the recess on the conductive seed layer, and the exposed seed layer is formed. On the other hand, by applying electrolytic plating, each bump is filled with a metal bump material to form electrode bumps, so that the electrode bumps can be formed more precisely and at an accurate height.

また、本発明に係る電極バンプの接続方法は、シリコン結晶面による化学的蝕刻性により各凹部を有する鋳型を形成するようにしているので、均一且つ正確な鋳型が形成できる。   Further, in the electrode bump connecting method according to the present invention, the mold having each recess is formed by the chemical etching property by the silicon crystal plane, so that a uniform and accurate mold can be formed.

また、本発明に係る電極バンプの接続方法は、樹脂を部分加圧して鋳型とすることにより、簡易に均一な鋳型が形成できる。   In the electrode bump connection method according to the present invention, a uniform mold can be easily formed by partially pressurizing resin to form a mold.

また、本発明に係る電極バンプの接続方法は、電極バンプの電極バンプが、先端部を他の半導体チップ間又は回路基板の電極パッドに当接座屈して接続していることにより、半導体チップの電極パッドに配設された電極バンプを他の半導体チップ又は回路基板に押圧して先端部を座屈変形させ、押圧応力を先端部の座屈変形で吸収して各半導体チップ又は回路基板へ直接印加されることがなくなり、電気的接続を確実且つ容易に実行できると共に、半導体チップ及び回路基板への接続動作時のストレスを防止できる
また、本発明に係る電極バンプの接続方法は、半導体チップと他の半導体チップ又は回路基板との間に非導電性樹脂を介在させた状態で前記先端部を押圧して座屈させるようにしているので、接合界面に存在する非導電樹脂を押しのけながら接合が進行することとなり、強い接合強度で低い接触抵抗を確保できると共に、高い信頼性をもつ結合が実現できる。 Further, the electrode bump connection method according to the present invention is such that the electrode bump of the electrode bump is connected by buckling the tip portion between other semiconductor chips or the electrode pads of the circuit board. The electrode bumps disposed on the electrode pads are pressed against another semiconductor chip or circuit board to buckle and deform the tip, and the pressure stress is absorbed by the buckling deformation of the tip and directly applied to each semiconductor chip or circuit board. The electrical connection can be reliably and easily performed, and stress during the connection operation to the semiconductor chip and the circuit board can be prevented. Also, the electrode bump connection method according to the present invention includes a semiconductor chip and a semiconductor chip. Since the tip portion is pressed and buckled with a non-conductive resin interposed between another semiconductor chip or a circuit board, the non-conductive resin present at the bonding interface is pressed. In spite of this, the joining proceeds, so that a low contact resistance can be secured with a strong joining strength, and a highly reliable joint can be realized.

また、本発明に係る電極バンプの接続方法は、半導体チップと他の半導体チップ又は回路基板との間に異方性導電膜を介在させた状態で前記先端部を押圧して座屈させるようにしているので、電極バンプが微細化した場合にも、従来の鍍金形バンプの典型的な形状である円柱或いは四角柱状の電極バンプに比べて、実効的な接合面積を増やすことができることとなり、異方性導電膜中野金属粒子のばらつきに伴う接合性、接触抵抗のばらつきを低減でき、信頼性の高い接合性を実現できる。   The electrode bump connection method according to the present invention is such that the tip portion is pressed and buckled while an anisotropic conductive film is interposed between the semiconductor chip and another semiconductor chip or circuit board. Therefore, even when the electrode bumps are miniaturized, the effective bonding area can be increased compared to the cylindrical or square columnar electrode bumps that are typical shapes of conventional plated bumps. It is possible to reduce the bonding property and the variation in contact resistance due to the dispersion of the metal particles in the isotropic conductive film, and to realize a highly reliable bonding property.

また、本発明に係る電極バンプの接続方法は、電極バンプにハロゲン元素を付着させ、当該ハロゲン元素が付着した電極バンプを座屈して接続するようにしているので、接続抵抗を小さくすることができることとなり、半導体チップ及び回路基板の発熱量を小さくでき且つ応答性を向上させる。   In addition, the electrode bump connection method according to the present invention attaches a halogen element to the electrode bump and buckles and connects the electrode bump to which the halogen element is attached, so that the connection resistance can be reduced. Thus, the heat generation amount of the semiconductor chip and the circuit board can be reduced and the responsiveness can be improved.

（本発明の第１の実施形態）
以下、本発明の第１の実施形態に係る電極バンプ接続方法を、この電極バンプ接続方法に用いられる電極バンプの製造方法と共に図１に基づいて説明する。この図１は本実施形態に係る電極バンプ接続方法を説明する動作態様図を示す。 (First embodiment of the present invention)
Hereinafter, an electrode bump connecting method according to a first embodiment of the present invention will be described with reference to FIG. 1 together with an electrode bump manufacturing method used in the electrode bump connecting method. FIG. 1 shows an operation mode diagram for explaining the electrode bump connection method according to the present embodiment.

同図において本実施形態に係る電極バンプ接続方法は、基部１ａから先端部１ｂに向かって先細状の四角錐にて形成される電極バンプ１が半導体チップ１０、〜、１２の電極パッド２上に載置され、この配設された複数の電極バンプ１に対向して前記半導体チップ１０、〜、１２及び他の半導体チップ１３の電極パッド３を配置し（同図（Ａ）を参照）、前記各電極バンプ１の先端部１ｂを所定押圧力で押圧して座屈させた状態で前記半導体チップ１０、〜、１３の各電極パッド２、３に当接させて接続する（同図（Ｂ）を参照）構成である。   In the figure, the electrode bump connection method according to the present embodiment is such that the electrode bump 1 formed by a tapered quadrangular pyramid from the base portion 1a to the tip portion 1b is formed on the electrode pads 2 of the semiconductor chips 10 to 12. The electrode pads 3 of the semiconductor chips 10 to 12 and the other semiconductor chips 13 are arranged so as to face the plurality of arranged electrode bumps 1 (see FIG. 1A), and In a state where the tip 1b of each electrode bump 1 is pressed and buckled with a predetermined pressing force, it is brought into contact with and connected to the electrode pads 2 and 3 of the semiconductor chips 10 to 13 (FIG. 2B). See FIG.

次に、前記構成に基づく本実施形態に係る電極バンプの接続方法に用いられる電極バンプを製造する電極バンプの製造方法について図２及び図３に基づいて説明する。この図２は本実施形態に係る電極バンプの接続方法に用いられる電極バンプを製造する電極バンプの製造方法の動作説明図を示す。   Next, an electrode bump manufacturing method for manufacturing an electrode bump used in the electrode bump connection method according to the present embodiment based on the above configuration will be described with reference to FIGS. FIG. 2 is an operation explanatory diagram of an electrode bump manufacturing method for manufacturing an electrode bump used in the electrode bump connection method according to this embodiment.

同図において本実施形態における電極バンプ製造方法は、同図（Ａ）に示すように鋳型１００の基台となる結晶面を有する単結晶シリコン１０１の表面に酸化膜１０２を形成し、この酸化膜１０２をフォトリソグラフィーで開口した後、アルカリ溶液で異方性エッチングすることで、逆四角錐状の凹部１０３を形成して製作する。この鋳型１００の製造方法としては、樹脂基板或いはシートを予め所望の形状に加工した別の鋳型を用いて加圧、加熱して形成する方法も用いることもできる。   In the figure, the electrode bump manufacturing method according to the present embodiment forms an oxide film 102 on the surface of a single crystal silicon 101 having a crystal plane as a base of a mold 100 as shown in FIG. An opening 102 is opened by photolithography, and then anisotropically etched with an alkaline solution to form an inverted square pyramid-shaped recess 103 to be manufactured. As a method of manufacturing the mold 100, a method of forming a resin substrate or sheet by pressurizing and heating using another mold obtained by processing a resin substrate or a sheet in a desired shape in advance can also be used.

次に同図（Ｂ）に示すように凹部１０３が形成された単結晶シリコン１０１の表面に導電性膜の酸化シリコン（ＳｉＯ2）層１０４を形成し、この酸化シリコン層１０４上に以後の電界メッキの際に電流を流すための薄い導電性金属（ＡｕＣｒ）膜からなるシード層１０５を形成する。さらに、同図（Ｃ）に示すように、前記シード層１０５上に金を電解鍍金して金鍍金層１０６を形成する。この電極バンプ用の金属バンプ材は金に限定されない。例えば、金以外に、銅、すず、すずと銀の合金、銀、ニッケル、アルミニウム等を用いることができる。 Next, as shown in FIG. 4B, a conductive silicon oxide (SiO 2 ) layer 104 is formed on the surface of the single crystal silicon 101 where the recess 103 is formed, and a subsequent electric field is formed on the silicon oxide layer 104. A seed layer 105 made of a thin conductive metal (AuCr) film is formed to allow a current to flow during plating. Further, as shown in FIG. 3C, gold plating layer 106 is formed by electrolytic plating of gold on the seed layer 105. The metal bump material for this electrode bump is not limited to gold. For example, in addition to gold, copper, tin, an alloy of tin and silver, silver, nickel, aluminum, or the like can be used.

また、同図（Ｄ）に示すように電解鍍金した金鍍金層１０６を鋳型１００の単結晶シリコン１０１表面が露出するまで研磨して平坦にして電極バンプ１を形成し、この電極バンプ１が電極パッド２に転写される際の接合性を良好なものとしている。   Further, as shown in FIG. 4D, the electroplated gold plating layer 106 is polished and flattened until the surface of the single crystal silicon 101 of the mold 100 is exposed, and the electrode bump 1 is formed. The bondability when transferred to the pad 2 is good.

さらに、同図（Ｅ）に示すように逆四角錐状の凹部１０３で形取られた金鍍金層１０６の四角錐状の電極バンプ１の接合面を頭出しするため、単結晶シリコン１０１をエッチングできるガスを含むプラズマを用いて単結晶シリコン１０１の表面をエッチングする。   Further, as shown in FIG. 5E, the single crystal silicon 101 is etched in order to cue the bonding surface of the electrode bump 1 of the quadrangular pyramid shape of the metal plating layer 106 formed by the concave portion 103 having the inverted quadrangular pyramid shape. The surface of the single crystal silicon 101 is etched using a plasma containing a gas that can be generated.

さらに、前記単結晶シリコン１０１の鋳型１００上に形成された電極バンプ１を半導体チップ１０、〜、１２の各電極パッド２に配設する動作は、まず同図（Ｆ）に示すように配設対象となる半導体チップ１０、〜、１２を単結晶シリコン１０１に対向配置し、図示矢印方向に加熱状態で押圧して複数の電極バンプ１を電極パッド２に移設転写する。この電極パッド２上への電極バンプ１の配設により、電極パッド２と電極バンプ１とが接着する。このように電極バンプ１が電極パッド２に接着された後は、同図（Ｇ）に示すように電極バンプ１から鋳型１００を離型する。   Further, the operation of disposing the electrode bumps 1 formed on the mold 100 of the single crystal silicon 101 on the electrode pads 2 of the semiconductor chips 10 to 12 is first disposed as shown in FIG. The target semiconductor chips 10 to 12 are disposed opposite to the single crystal silicon 101 and pressed in a heated state in the direction of the arrow in the drawing to transfer and transfer the plurality of electrode bumps 1 to the electrode pads 2. By arranging the electrode bump 1 on the electrode pad 2, the electrode pad 2 and the electrode bump 1 are bonded. After the electrode bump 1 is bonded to the electrode pad 2 as described above, the mold 100 is released from the electrode bump 1 as shown in FIG.

また、前記電極バンプ１の電極パッド２上への移設転写は、大きさ２．５ｍｍ角の半導体チップ１０、〜、 １２の表面に合わせて加圧し、同時に鋳型１００と半導体チップ１０、〜、１２を個別に加圧する実験をおこなった。この実験における押圧の圧力は５ｋｇｆ〜２５ｋｇｆの範囲で調査し、半導体チップ側温度は２００℃一定、鋳型側温度は１５０℃〜４００℃の範囲でパルス状に加熱して調査した。この実験の動作状態を図３に示し、１つの電極バンプ当たり２．５ｇの押圧力が印加されたこととなる。   In addition, the transfer transfer of the electrode bump 1 onto the electrode pad 2 is performed by applying pressure to the surface of the 2.5 mm square semiconductor chips 10 to 12, and simultaneously, the mold 100 and the semiconductor chips 10,. An experiment was conducted to pressurize each of them individually. In this experiment, the pressing pressure was investigated in the range of 5 kgf to 25 kgf, the semiconductor chip side temperature was constant at 200 ° C., and the mold side temperature was investigated in the form of pulses in the range of 150 ° C. to 400 ° C. The operation state of this experiment is shown in FIG. 3, and a pressing force of 2.5 g per one electrode bump is applied.

（本発明の第２の実施形態）
本発明の第２の実施形態に係る電極バンプ接続方法を、この電極バンプ接続方法に用いられる電極バンプの製造方法と共に図４に基づいて説明する。この図４は本実施形態に係る電極バンプ接続方法に用いられる電極バンプを製造する電極バンプの製造方法の動作説明図を示す。 (Second embodiment of the present invention)
An electrode bump connection method according to a second embodiment of the present invention will be described based on FIG. 4 together with an electrode bump manufacturing method used in this electrode bump connection method. FIG. 4 is an operation explanatory diagram of an electrode bump manufacturing method for manufacturing an electrode bump used in the electrode bump connection method according to the present embodiment.

同図において本実施形態に係る電極バンプ接続方法は、前記図１に示す第１の実施形態の電極バンプ製造方法と同様に構成され、この電極バンプを製造する電極バンプ製造方法を異にする。   In the figure, the electrode bump connection method according to this embodiment is configured in the same manner as the electrode bump manufacturing method of the first embodiment shown in FIG. 1, and the electrode bump manufacturing method for manufacturing this electrode bump is different.

まず、図４（Ａ）に示すように前記第１の実施形態と同様にフォトリソグラフィー技術及び異方性エッチング技術により逆四角錐状の凹部１０３を複数形成した鋳型１００の基台となる単結晶シリコン１０１を作成する。また、同図（Ｂ）で示すように前記第１の実施形態と同様に凹部１０３が形成された単結晶シリコン１０１の表面に酸化シリコン（ＳｉＯ2）層１０４及びシード層１０５を積層して形成する。 First, as shown in FIG. 4A, a single crystal serving as a base of a mold 100 in which a plurality of inverted quadrangular concave portions 103 are formed by photolithography and anisotropic etching as in the first embodiment. Silicon 101 is formed. Further, as shown in FIG. 5B, a silicon oxide (SiO 2 ) layer 104 and a seed layer 105 are stacked on the surface of the single crystal silicon 101 where the recess 103 is formed, as in the first embodiment. To do.

次に、同図（Ｃ）に示すように酸化シリコン層１０４及びシード層１０５が形成された単結晶シリコン１０１に対して、前記凹部１０３以外の領域にフォトレジストパターン１０７をフォトリソグラフィーにて形成し、電極バンプ１を形成する領域を決定する。また、同図（Ｄ）に示すように前記フォトレジストパターン１０７が形成されない凹部１０３の領域に電解鍍金により金鍍金層１０６を形成する。   Next, as shown in FIG. 2C, a photoresist pattern 107 is formed on the single crystal silicon 101 on which the silicon oxide layer 104 and the seed layer 105 are formed in a region other than the recess 103 by photolithography. The region where the electrode bump 1 is to be formed is determined. Further, as shown in FIG. 4D, a gold plating layer 106 is formed by electrolytic plating in the region of the recess 103 where the photoresist pattern 107 is not formed.

また、同図（Ｅ）に示すように、電解鍍金により金鍍金層１０６が形成された単結晶シリコン１０１のフォトレジストパターン１０７及びシード層１０５を除去することにより電極バンプ１が形成される。   Further, as shown in FIG. 5E, the electrode bump 1 is formed by removing the photoresist pattern 107 and the seed layer 105 of the single crystal silicon 101 on which the gold plating layer 106 is formed by electrolytic plating.

さらに、前記単結晶シリコン１０１の鋳型１００上に形成された電極バンプ１を半導体チップ１０、〜、１２の各電極パッド２に配設する動作は、まず同図（Ｆ）に示すように配設対象となる半導体チップ１０、〜、１２を単結晶シリコン１０１に対向配置し、図示矢印方向に加熱状態で押圧して複数の電極バンプ１を電極パッド２に移設転写する。この電極パッド２上への電極バンプ１の配設により電極パッド２と電極バンプ１が接着する。このように電極バンプ１が電極パッド２に接着された後は、同図（Ｇ）に示すように電極バンプ１から鋳型１００を離型する。   Further, the operation of disposing the electrode bumps 1 formed on the mold 100 of the single crystal silicon 101 on the electrode pads 2 of the semiconductor chips 10 to 12 is first disposed as shown in FIG. The target semiconductor chips 10 to 12 are disposed opposite to the single crystal silicon 101 and pressed in a heated state in the direction of the arrow in the drawing to transfer and transfer the plurality of electrode bumps 1 to the electrode pads 2. By arranging the electrode bump 1 on the electrode pad 2, the electrode pad 2 and the electrode bump 1 are bonded. After the electrode bump 1 is bonded to the electrode pad 2 as described above, the mold 100 is released from the electrode bump 1 as shown in FIG.

（本発明の第３の実施形態）
本発明の第３の実施形態に係る電極バンプ接続方法を、図５に基づいて説明する。この図５は本実施形態に係る電極バンプ接続方法に非導電性樹脂を介在させた場合の接続態様図を示す。 (Third embodiment of the present invention)
An electrode bump connection method according to the third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a connection diagram when a non-conductive resin is interposed in the electrode bump connection method according to this embodiment.

同図において、本実施形態に係る電極バンプ接続方法は、四角錐形状の電極バンプ１が電極パッド２上に載置された半導体チップ１０と、この半導体チップ１０に電気的に接続される他の半導体チップ１１との間に非導電性樹脂４を介在させ、前記半導体チップ１０の電極バンプ１の先端部１ｂを半導体チップ１１の電極パッド３に押圧して座屈させることにより接続する構成である。   In the figure, the electrode bump connection method according to the present embodiment includes a semiconductor chip 10 on which a quadrangular pyramid-shaped electrode bump 1 is placed on an electrode pad 2 and other semiconductor chips 10 that are electrically connected to the semiconductor chip 10. The non-conductive resin 4 is interposed between the semiconductor chip 11 and the tip 1b of the electrode bump 1 of the semiconductor chip 10 is pressed against the electrode pad 3 of the semiconductor chip 11 to be connected by buckling. .

このように、接続しようとする半導体チップ１０、１１の間に非導電性樹脂４を介在させて強い接合強度を確保させる場合においても、電極バンプ１の四角錐形状が非導電性樹脂４を押しのけながら対向する半導体チップ１１の電極パッド３に接触し、さらに電極バンプ１の先端部１ｂを座屈しつつ非導電性樹脂４を側方へ排除し、座屈面に非導電性樹脂４が噛み込まれて接合することがなくなり、強い接合強度と共に低い接触抵抗及び高い接合の信頼性を実現できることとなる。   As described above, even when the nonconductive resin 4 is interposed between the semiconductor chips 10 and 11 to be connected to ensure a strong bonding strength, the quadrangular pyramid shape of the electrode bump 1 displaces the nonconductive resin 4. While contacting the electrode pad 3 of the opposing semiconductor chip 11 and further buckling the tip 1b of the electrode bump 1, the nonconductive resin 4 is removed to the side, and the nonconductive resin 4 bites into the buckled surface. In rare cases, bonding will not occur, and low contact resistance and high bonding reliability will be realized along with strong bonding strength.

（本発明の第４の実施形態）
本発明の第４の実施形態に係る電極バンプ接続方法を、図６に基づいて説明する。この図６は本実施形態に係る電極バンプ接続方法に異方性導電膜を介在させた場合の接続態様図を示す。 (Fourth embodiment of the present invention)
An electrode bump connection method according to the fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a connection diagram in the case where an anisotropic conductive film is interposed in the electrode bump connection method according to this embodiment.

同図において、本実施形態に係る電極バンプ接続方法は、四角錐形状の電極バンプ１が電極パッド２上に載置された半導体チップ１０と、この半導体チップ１０に電気的に接続される他の半導体チップ１１との間に異方性導電膜５を介在させ、前記半導体チップ１０の電極バンプ１の先端部１ｂを半導体チップ１１の電極パッド３に押圧して座屈させることにより接続する構成である。   In the figure, the electrode bump connection method according to the present embodiment includes a semiconductor chip 10 on which a quadrangular pyramid-shaped electrode bump 1 is placed on an electrode pad 2 and other semiconductor chips 10 that are electrically connected to the semiconductor chip 10. An anisotropic conductive film 5 is interposed between the semiconductor chip 11 and the tip 1b of the electrode bump 1 of the semiconductor chip 10 is connected to the electrode pad 3 of the semiconductor chip 11 by being pressed and buckled. is there.

このように、接続しようとする半導体チップ１０、１１の間に異方性導電膜５を介在させて強い電気的接合状態を確保させる場合においても、電極バンプ１の四角錐形状が異方性導電膜５を噛み込みながら対向する半導体チップ１１の電極パッド３に接触し、さらに電極バンプ１の先端部１ｂを座屈しつつ異方性導電膜５の銀粒子（Ａｇ）５１を押しつぶして接合することとなり、電極バンプ１が高密度化して電極バンプ１相互間の間隔が接近した場合においても、電極バンプ１相互の干渉がなくなり、電気的接続の確実性を向上させると共に誤接続を確認できる。   In this way, even when the anisotropic conductive film 5 is interposed between the semiconductor chips 10 and 11 to be connected to ensure a strong electrical bonding state, the quadrangular pyramid shape of the electrode bump 1 is anisotropic conductive. The silver particles (Ag) 51 of the anisotropic conductive film 5 are crushed and bonded while contacting the electrode pads 3 of the opposing semiconductor chip 11 while biting the film 5 and further buckling the tip 1b of the electrode bump 1. Thus, even when the electrode bumps 1 are densified and the distance between the electrode bumps 1 approaches, the interference between the electrode bumps 1 is eliminated, and the reliability of the electrical connection is improved and the erroneous connection can be confirmed.

なお、前記電極バンプ１には、ハロゲン元素を付着させ、このはハロゲン元素が付着した電極バンプ１を座屈して半導体チップ１０と他の半導体チップ１１を接続することもできる。   It is to be noted that a halogen element is attached to the electrode bump 1, and the semiconductor chip 10 can be connected to another semiconductor chip 11 by buckling the electrode bump 1 to which the halogen element is attached.

また、鋳型１００の単結晶シリコン１０１上に形成されるシード層１０５としては、鋳型１００に対して適度な密着性をもち、且つ転写の際の離型のい容易性を有する金属が望ましい。   The seed layer 105 formed on the single crystal silicon 101 of the mold 100 is preferably a metal that has appropriate adhesion to the mold 100 and that can be easily released during transfer.

さらにまた、前記複数の電極バンプ１の先端部１bの座屈は、電極バンプ１の高さの少なくとも約５％以上変形させる構成とすることができる。この先端部１bの座屈の程度は、電極バンプ１の素材又は異方性導電膜の種類により、電気的接続状態が十分確保できる範囲で任意に調整することができる。   Furthermore, the buckling of the tip portions 1b of the plurality of electrode bumps 1 can be configured to deform at least about 5% or more of the height of the electrode bumps 1. The degree of buckling of the tip end portion 1b can be arbitrarily adjusted within a range in which an electrical connection state can be sufficiently secured depending on the material of the electrode bump 1 or the type of the anisotropic conductive film.

本発明の第１の実施形態に係る電極バンプ接続方法の動作説明図である。It is operation | movement explanatory drawing of the electrode bump connection method which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る電極バンプの接続方法に用いられる電極バンプを製造する電極バンプの製造方法の動作説明図である。It is operation | movement explanatory drawing of the manufacturing method of the electrode bump which manufactures the electrode bump used for the connection method of the electrode bump which concerns on the 1st Embodiment of this invention. 図２の動作説明における鋳型で形成された電極バンプ転写動作説明図である。FIG. 3 is an explanatory diagram of an electrode bump transfer operation formed with a mold in the operation description of FIG. 2. 本発明の第２の実施形態に係る電極バンプ接続方法に用いられる電極バンプを製造する電極バンプの製造方法の動作説明図Operation | movement explanatory drawing of the manufacturing method of the electrode bump which manufactures the electrode bump used for the electrode bump connection method concerning the 2nd Embodiment of this invention 本発明の第３の実施形態に係る電極バンプ接続方法に非導電性樹脂を介在させた場合の接続態様図である。It is a connection mode figure at the time of interposing nonelectroconductive resin in the electrode bump connection method which concerns on the 3rd Embodiment of this invention. 本発明の第４の実施形態に係る電極バンプ接続方法に異方性導電膜を介在させた場合の接続態様図である。It is a connection mode figure at the time of interposing an anisotropic conductive film in the electrode bump connection method concerning a 4th embodiment of the present invention.

符号の説明Explanation of symbols

１ 電極バンプ
１ａ 基部
１ｂ 先端部
２、３ 電極パッド
４ 非導電性樹脂
５ 異方性導電膜
１０、〜、１３ 半導体チップ
５１ 銀粒子（Ａｇ）
１００ 鋳型
１０１ 単結晶シリコン
１０２ 酸化膜
１０３ 凹部
１０４ 酸化シリコン（ＳｉＯ2）層
１０５ シード層
１０６ 金鍍金層
１０７ フォトレジストパターン DESCRIPTION OF SYMBOLS 1 Electrode bump 1a Base 1b Tip part 2, 3 Electrode pad 4 Non-conductive resin 5 Anisotropic conductive film 10, ..., 13 Semiconductor chip 51 Silver particle (Ag)
100 mold 101 single crystal silicon 102 oxide film 103 recess 104 of silicon oxide (SiO 2) layer 105 seed layer 106 gold plating layer 107 photoresist pattern

Claims (12)

半導体チップの電極パッド上に配設され、他の半導体チップ又は回路基板の電極パッドに当接して接続する電極バンプにおいて
先端部が基部より応力変形を大きく形成されることを
特徴とする電極バンプ。 An electrode bump which is disposed on an electrode pad of a semiconductor chip and is connected to an electrode pad of another semiconductor chip or a circuit board in contact with the tip portion, wherein the tip portion is formed to have greater stress deformation than the base portion. 前記請求項１に記載の電極バンプにおいて、
基部から先端部に向かって先細状の錐形状にて形成されることを
特徴とする電極バンプ。 In the electrode bump according to claim 1,
An electrode bump characterized by being formed in a tapered cone shape from the base to the tip. 前記請求項１または２に記載の電極バンプが、対応する凹形状の凹部を複雑連設される鋳型に金属バンプ材を充填して形成することを
特徴とする電極バンプの製造方法。 3. The method for producing an electrode bump according to claim 1 or 2, wherein the electrode bump is formed by filling a metal bump material into a mold in which corresponding concave-shaped concave portions are complicatedly arranged. 前記請求項３に記載の電極バンプの製造方法において、
前記鋳型に金属バンプ材を堆積させ、当該堆積した金属バンプ材を前記各凹部相互間の境界部分が露出するまで切削することを
特徴とする電極バンプの製造方法。 In the manufacturing method of the electrode bump according to claim 3,
A method for producing an electrode bump, comprising depositing a metal bump material on the mold and cutting the deposited metal bump material until a boundary portion between the recesses is exposed. 前記請求項３に記載の電極バンプの製造方法において、
前記鋳型の凹部に導電性のシード層を形成し、当該シード層に電解鍍金を施して各凹部に金属バンプ材を充填することを
特徴とする電極バンプの製造方法。 In the manufacturing method of the electrode bump according to claim 3,
A method for producing an electrode bump, comprising: forming a conductive seed layer in a concave portion of the mold, applying an electrolytic plating to the seed layer, and filling each concave portion with a metal bump material. 前記請求項３に記載の電極バンプの製造方法において、
前記鋳型の表面に導電性のシード層を形成し、当該シード層上の前記凹部以外の境界部分に非導電性のレジスト層を積層形成し、前記シード層が露出部分の各凹部に電解鍍金を施して各凹部に金属バンプ材を充填することを
特徴とする電極バンプの製造方法。 In the manufacturing method of the electrode bump according to claim 3,
A conductive seed layer is formed on the surface of the mold, a non-conductive resist layer is formed on a boundary portion other than the concave portion on the seed layer, and electrolytic plating is applied to each concave portion of the exposed portion of the seed layer. A method of manufacturing an electrode bump, comprising: applying a metal bump material to each recess. 前記請求項３ないし６のいづれかに記載の電極バンプの製造方法において、
前記鋳型がシリコンの結晶面間による化学的蝕刻性の違いにより凹部を形成されることを
特徴とする電極バンプの製造方法。 In the method for manufacturing an electrode bump according to any one of claims 3 to 6,
A method for producing an electrode bump, wherein the mold is formed with a recess due to a difference in chemical etchability between crystal planes of silicon. 前記請求項３ないし６のいずれかに記載の電極バンプの製造方法において、
前記鋳型が、樹脂平面の部分加圧により凹部を形成されることを
特徴とする電極バンプの製造方法。 In the method of manufacturing an electrode bump according to any one of claims 3 to 6,
A method for producing an electrode bump, wherein the mold has a recess formed by partial pressurization of a resin plane. 前記請求項１又は２に記載の電極バンプが、先端部を他の半導体チップ間又は回路基板の電極パッドに当接座屈して接続することを
特徴とする電極バンプ接続方法。 3. The electrode bump connection method according to claim 1, wherein the electrode bump is connected by buckling the tip portion between other semiconductor chips or electrode pads of a circuit board. 前記請求項９に記載の電極バンプの接続方法において、
前記半導体チップと他の半導体チップ又は回路基板との間に非導電性樹脂を介在させた状態で前記先端部を押圧して座屈させることを
特徴とする電極バンプの接続方法。 In the electrode bump connection method according to claim 9,
A method for connecting electrode bumps, wherein the tip portion is pressed and buckled while a non-conductive resin is interposed between the semiconductor chip and another semiconductor chip or circuit board. 前記請求項９に記載の電極バンプの接続方法において、
前記半導体チップと他の半導体チップ又は回路基板との間に異方性導電膜を介在させた状態で前記先端部を押圧して座屈させることを
特徴とする電極バンプの接続方法。 In the electrode bump connection method according to claim 9,
A method for connecting electrode bumps, wherein the tip portion is pressed and buckled while an anisotropic conductive film is interposed between the semiconductor chip and another semiconductor chip or circuit board. 前記請求項９ないし１１のいずれかに記載の電極バンプの接続方法において、
前記電極バンプにハロゲン元素を付着させ、当該ハロゲン元素が付着した電極バンプを座屈して接続することを
特徴とする電極バンプの接続方法。 In the electrode bump connection method according to any one of claims 9 to 11,
A method of connecting an electrode bump, comprising attaching a halogen element to the electrode bump and buckling the electrode bump to which the halogen element is attached.
JP2004048252A 2004-02-24 2004-02-24 Electrode bump, its manufacture, and its connection method Expired - Fee Related JP4480417B2 (en)

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JP2007123478A (en) * 2005-10-27 2007-05-17 Shindengen Electric Mfg Co Ltd Chip-carrier package
EP1978559A2 (en) 2007-04-06 2008-10-08 Hitachi, Ltd. Semiconductor device
JP2008277733A (en) * 2007-04-06 2008-11-13 Hitachi Ltd Semiconductor device
JP2009043891A (en) * 2007-08-08 2009-02-26 Yamaha Corp Method of manufacturing electronic component
US7791016B2 (en) 2007-10-29 2010-09-07 Hamamatsu Photonics K.K. Photodetector
JP2012109481A (en) * 2010-11-19 2012-06-07 Toray Ind Inc Method of manufacturing semiconductor device and semiconductor device
TWI566370B (en) * 2010-11-08 2017-01-11 三星電子股份有限公司 Semiconductor device and fabrication methods thereof
CN111799241A (en) * 2020-06-24 2020-10-20 霸州市云谷电子科技有限公司 Bonding structure, manufacturing method thereof and display panel
WO2024009498A1 (en) * 2022-07-08 2024-01-11 株式会社レゾナック Method for manufacturing semiconductor device, substrate, and semiconductor element

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123478A (en) * 2005-10-27 2007-05-17 Shindengen Electric Mfg Co Ltd Chip-carrier package
EP1978559A2 (en) 2007-04-06 2008-10-08 Hitachi, Ltd. Semiconductor device
JP2008277733A (en) * 2007-04-06 2008-11-13 Hitachi Ltd Semiconductor device
US8258625B2 (en) 2007-04-06 2012-09-04 Hitachi, Ltd. Semiconductor device
JP2009043891A (en) * 2007-08-08 2009-02-26 Yamaha Corp Method of manufacturing electronic component
US7791016B2 (en) 2007-10-29 2010-09-07 Hamamatsu Photonics K.K. Photodetector
TWI566370B (en) * 2010-11-08 2017-01-11 三星電子股份有限公司 Semiconductor device and fabrication methods thereof
JP2012109481A (en) * 2010-11-19 2012-06-07 Toray Ind Inc Method of manufacturing semiconductor device and semiconductor device
CN111799241A (en) * 2020-06-24 2020-10-20 霸州市云谷电子科技有限公司 Bonding structure, manufacturing method thereof and display panel
WO2024009498A1 (en) * 2022-07-08 2024-01-11 株式会社レゾナック Method for manufacturing semiconductor device, substrate, and semiconductor element

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