KR101423349B1 - 구리와 배리어층 간의 접착력을 개선하는 자기조립 단층 - Google Patents

구리와 배리어층 간의 접착력을 개선하는 자기조립 단층 Download PDF

Info

Publication number
KR101423349B1
KR101423349B1 KR1020097004315A KR20097004315A KR101423349B1 KR 101423349 B1 KR101423349 B1 KR 101423349B1 KR 1020097004315 A KR1020097004315 A KR 1020097004315A KR 20097004315 A KR20097004315 A KR 20097004315A KR 101423349 B1 KR101423349 B1 KR 101423349B1
Authority
KR
South Korea
Prior art keywords
layer
copper
barrier layer
metallic barrier
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020097004315A
Other languages
English (en)
Korean (ko)
Other versions
KR20090045302A (ko
Inventor
프라빈 날라
윌리엄 티
존 보이드
티루히라팔리 아루나기리
형석 알렉산더 윤
프리츠 씨 레데커
예즈디 도르디
Original Assignee
램 리써치 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/514,038 external-priority patent/US8241701B2/en
Application filed by 램 리써치 코포레이션 filed Critical 램 리써치 코포레이션
Publication of KR20090045302A publication Critical patent/KR20090045302A/ko
Application granted granted Critical
Publication of KR101423349B1 publication Critical patent/KR101423349B1/ko
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein

Landscapes

  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020097004315A 2006-08-30 2007-08-15 구리와 배리어층 간의 접착력을 개선하는 자기조립 단층 Expired - Fee Related KR101423349B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US11/514,038 US8241701B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a barrier surface for copper deposition
US11/514,038 2006-08-30
US11/639,012 2006-12-13
US11/639,012 US20090304914A1 (en) 2006-08-30 2006-12-13 Self assembled monolayer for improving adhesion between copper and barrier layer
PCT/US2007/018212 WO2008027205A2 (en) 2006-08-30 2007-08-15 Self assembled monolayer for improving adhesion between copper and barrier layer

Publications (2)

Publication Number Publication Date
KR20090045302A KR20090045302A (ko) 2009-05-07
KR101423349B1 true KR101423349B1 (ko) 2014-07-24

Family

ID=39136454

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020097004315A Expired - Fee Related KR101423349B1 (ko) 2006-08-30 2007-08-15 구리와 배리어층 간의 접착력을 개선하는 자기조립 단층

Country Status (7)

Country Link
US (1) US20090304914A1 (https=)
JP (1) JP5420409B2 (https=)
KR (1) KR101423349B1 (https=)
MY (1) MY162187A (https=)
SG (1) SG174105A1 (https=)
TW (2) TWI453822B (https=)
WO (1) WO2008027205A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016117851A1 (ko) * 2015-01-23 2016-07-28 코닝정밀소재 주식회사 금속 접합기판

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916232B2 (en) * 2006-08-30 2014-12-23 Lam Research Corporation Method for barrier interface preparation of copper interconnect
JP4755573B2 (ja) * 2006-11-30 2011-08-24 東京応化工業株式会社 処理装置および処理方法、ならびに表面処理治具
KR100841170B1 (ko) * 2007-04-26 2008-06-24 삼성전자주식회사 저저항 금속 배선 형성방법, 금속 배선 구조 및 이를이용하는 표시장치
JP4971078B2 (ja) * 2007-08-30 2012-07-11 東京応化工業株式会社 表面処理装置
KR101096031B1 (ko) 2009-03-31 2011-12-19 한양대학교 산학협력단 자기조립단분자막 형성방법과 이를 이용한 반도체 소자의 구리배선 및 그의 형성방법
US8415252B2 (en) * 2010-01-07 2013-04-09 International Business Machines Corporation Selective copper encapsulation layer deposition
US9252049B2 (en) 2013-03-06 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming interconnect structure that avoids via recess
US8962473B2 (en) 2013-03-15 2015-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming hybrid diffusion barrier layer and semiconductor device thereof
KR102264160B1 (ko) 2014-12-03 2021-06-11 삼성전자주식회사 비아 구조체 및 배선 구조체를 갖는 반도체 소자 제조 방법
US9799593B1 (en) * 2016-04-01 2017-10-24 Intel Corporation Semiconductor package substrate having an interfacial layer
US10358715B2 (en) * 2016-06-03 2019-07-23 Applied Materials, Inc. Integrated cluster tool for selective area deposition
KR101819825B1 (ko) * 2016-06-13 2018-01-18 아주대학교산학협력단 플렉시블 전극 제조방법
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US9875958B1 (en) 2016-11-09 2018-01-23 International Business Machines Corporation Trace/via hybrid structure and method of manufacture
US10163695B1 (en) * 2017-06-27 2018-12-25 Lam Research Corporation Self-forming barrier process
US10678135B2 (en) 2017-12-20 2020-06-09 International Business Machines Corporation Surface treatment of titanium containing hardmasks
JP2019192892A (ja) 2018-04-18 2019-10-31 東京エレクトロン株式会社 処理システムおよび処理方法
CN110952081B (zh) * 2018-09-27 2022-04-29 Imec 非营利协会 用于形成互连部的方法和溶液
KR20250116174A (ko) 2018-11-19 2025-07-31 램 리써치 코포레이션 텅스텐을 위한 몰리브덴 템플릿들
WO2020131897A1 (en) * 2018-12-17 2020-06-25 Averatek Corporation Three dimensional circuit formation
SG11202108217UA (en) 2019-01-28 2021-08-30 Lam Res Corp Deposition of metal films
US12334351B2 (en) 2019-09-03 2025-06-17 Lam Research Corporation Molybdenum deposition
WO2021076636A1 (en) 2019-10-15 2021-04-22 Lam Research Corporation Molybdenum fill
US11929327B2 (en) 2020-01-29 2024-03-12 Taiwan Semiconductor Manufacturing Co., Inc. Liner-free conductive structures with anchor points
DE102020119831B4 (de) 2020-01-29 2024-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Verfahren und Struktur
WO2022108762A1 (en) * 2020-11-19 2022-05-27 Lam Research Corporation Low resistivity contacts and interconnects
JP7686761B2 (ja) 2021-02-23 2025-06-02 ラム リサーチ コーポレーション ３ｄ－ｎａｎｄ用の酸化物表面上へのモリブデン膜の堆積
WO2022221210A1 (en) 2021-04-14 2022-10-20 Lam Research Corporation Deposition of molybdenum
CN115702474A (zh) 2021-05-14 2023-02-14 朗姆研究公司 高选择性掺杂硬掩模膜
CN121175781A (zh) * 2023-05-23 2025-12-19 朗姆研究公司 在沟槽特征中的抑制式原子层沉积
CN121310847B (zh) * 2025-12-11 2026-02-24 合肥晶合集成电路股份有限公司 半导体结构及其键合方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734559B1 (en) * 1999-09-17 2004-05-11 Advanced Micro Devices, Inc. Self-aligned semiconductor interconnect barrier and manufacturing method therefor
US20060108320A1 (en) * 2004-11-22 2006-05-25 Lazovsky David E Molecular self-assembly in substrate processing
KR100613388B1 (ko) * 2004-12-23 2006-08-17 동부일렉트로닉스 주식회사 다마신법을 이용한 구리 배선층을 갖는 반도체 소자 및 그형성 방법
KR100718804B1 (ko) * 2005-11-15 2007-05-16 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949671A (en) * 1985-10-24 1990-08-21 Texas Instruments Incorporated Processing apparatus and method
JP3911643B2 (ja) * 1995-07-05 2007-05-09 富士通株式会社 埋め込み導電層の形成方法
US6042623A (en) * 1998-01-12 2000-03-28 Tokyo Electron Limited Two-wafer loadlock wafer processing apparatus and loading and unloading method therefor
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
JP3974284B2 (ja) * 1999-03-18 2007-09-12 株式会社東芝 半導体装置の製造方法
US6423636B1 (en) * 1999-11-19 2002-07-23 Applied Materials, Inc. Process sequence for improved seed layer productivity and achieving 3mm edge exclusion for a copper metalization process on semiconductor wafer
US6890853B2 (en) * 2000-04-25 2005-05-10 Tokyo Electron Limited Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module
US20040040504A1 (en) * 2002-08-01 2004-03-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing apparatus
US20050274621A1 (en) * 2004-06-10 2005-12-15 Zhi-Wen Sun Method of barrier layer surface treatment to enable direct copper plating on barrier metal
US20060033678A1 (en) * 2004-01-26 2006-02-16 Applied Materials, Inc. Integrated electroless deposition system
US8916232B2 (en) * 2006-08-30 2014-12-23 Lam Research Corporation Method for barrier interface preparation of copper interconnect

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734559B1 (en) * 1999-09-17 2004-05-11 Advanced Micro Devices, Inc. Self-aligned semiconductor interconnect barrier and manufacturing method therefor
US20060108320A1 (en) * 2004-11-22 2006-05-25 Lazovsky David E Molecular self-assembly in substrate processing
KR100613388B1 (ko) * 2004-12-23 2006-08-17 동부일렉트로닉스 주식회사 다마신법을 이용한 구리 배선층을 갖는 반도체 소자 및 그형성 방법
KR100718804B1 (ko) * 2005-11-15 2007-05-16 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016117851A1 (ko) * 2015-01-23 2016-07-28 코닝정밀소재 주식회사 금속 접합기판

Also Published As

Publication number Publication date
TWI462178B (zh) 2014-11-21
JP2010503203A (ja) 2010-01-28
WO2008027205A3 (en) 2008-04-24
MY162187A (en) 2017-05-31
TW201246376A (en) 2012-11-16
SG174105A1 (en) 2011-09-29
TW200834726A (en) 2008-08-16
KR20090045302A (ko) 2009-05-07
US20090304914A1 (en) 2009-12-10
WO2008027205A2 (en) 2008-03-06
TWI453822B (zh) 2014-09-21
JP5420409B2 (ja) 2014-02-19

Similar Documents

Publication Publication Date Title
KR101423349B1 (ko) 구리와 배리어층 간의 접착력을 개선하는 자기조립 단층
JP5484053B2 (ja) 銅配線のバリア界面調整のための方法および装置
CN101548030A (zh) 用于增强铜和阻挡层之间粘结的自组装单层
JP5489717B2 (ja) 金属堆積のために基板表面を調整する方法および統合システム
US6905958B2 (en) Protecting metal conductors with sacrificial organic monolayers
US20110049716A1 (en) Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects
KR20200001556A (ko) 자기 터널 접합들을 위한 확산 층
KR20030068478A (ko) 반도체 디바이스 및 그 제조 방법
US20220115267A1 (en) In-situ cmp self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion
KR101506352B1 (ko) 금속 증착을 위해 기판 표면을 가공하는 프로세스 및 통합 시스템
US7867897B2 (en) Low leakage metal-containing cap process using oxidation
US10256185B2 (en) Nitridization for semiconductor structures
KR101487564B1 (ko) 구리 상호접속부의 배리어 계면 제작 방법 및 장치
JP2012074608A (ja) 配線形成方法
US6784093B1 (en) Copper surface passivation during semiconductor manufacturing
TW202333205A (zh) 半導體結構與其形成方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20170710

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20180719

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20180719

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000