KR101418036B1 - 도금 처리된 관통홀을 갖는 다층 인쇄 회로 기판의 제조방법 - Google Patents
도금 처리된 관통홀을 갖는 다층 인쇄 회로 기판의 제조방법 Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
- H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
보다 상세하게는 다수의 부도체층과 도체층이 교차 적층되어 이루어지고 층간 도체를 전기적으로 연결하기 위하여 관통홀 내벽에 전기 도금이 이루어진 다층 인쇄 회로 기판(Multi Layer PCB; MLB)의 제조방법에 있어서, 관통홀에 전도성 음이온 탄소의 코팅 효율이 증대되도록 관통홀의 부도체 표면을 양이온화 시키는 공정 이전에, 부도체 표면을 음이온화시키는 공정이 이루어지도록 함으로써, 관통홀의 부도체 표면의 양이온화가 더욱 쉽고 빠르게 이루어져, 관통홀 내부의 전도성 확보가 용이해져 종국적으로 전기 도금이 더욱 쉽고 빠르게 이루어지도록 한 다층 인쇄 회로 기판의 제조방법에 관한 것이다.
Description
도 2는 본 발명에 따른 다층 인쇄 회로 기판의 제조방법의 전기 도금 공정을 개략적으로 설명한 개념도.
도 3 내지 도 5은 본 발명에 따른 다층 인쇄 회로 기판의 제조방법을 설명하기 위한 실험 결과도들.
2 : 부도체 3 : 관통홀
4 : 음이온성 산화막층 5 : 전도성 음이온 탄소층
6 : 전기 도금층
Claims (10)
- A) 다수의 도체와 부도체가 교차 적층되며, 관통홀을 갖는 다층 인쇄 회로 기판을 준비하는 단계;
B) 상기 관통홀을 통해 노출된 상기 부도체 표면을 양이온화시키는 단계;
C) 상기 관통홀을 전도성 음이온 탄소로 코팅하는 단계;
D) 상기 관통홀을 통해 노출된 상기 도체 표면에 코팅된 전도성 음이온 탄소를 제거하기 위하여 마이크로 에칭 공정을 실시하는 단계; 및
E) 상기 관통홀을 전기 도금하여 상기 도체를 전기적으로 연결하는 단계;를 포함하여 이루어지되,
상기 B) 단계는 관통홀의 부도체 표면을 양이온화시키는 공정 이전에, 부도체 표면을 음이온화 시키는 공정을 포함하여 이루어지는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 1 항에 있어서,
상기 B) 단계의 음이온화 공정은 상기 기판을 나노 버블을 포함하는 용액에 투입하여 이루어지는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 2 항에 있어서,
상기 나노 버블을 포함하는 용액은 나노 발생기를 이용하여 용존 오존량을 증가시킨 용액인 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 3 항에 있어서,
상기 B) 단계의 용존 오존량을 증가시킨 용액은 5~10ppm의 오존 농도를 갖고, 오존의 양은 20g/㎥~30g/㎥로 이루어지는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 4 항에 있어서,
상기 B) 단계는 상기 기판을 용존 오존량이 증가된 용액에 수직 방식으로 침지시키며, 처리 시간은 10초~30초로 이루어지는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 1 항에 있어서,
상기 B) 단계의 양이온화 공정은 양이온성 계면활성제가 포함된 용액에 투입하여 이루어지는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 1 항에 있어서,
상기 C) 단계는 코팅된 음이온 탄소로부터 수분을 제거하기 위한 드라이 공정을 더 포함하여 이루어지는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 1 항에 있어서,
상기 A) 단계는 프리 에칭 공정을 포함하고,
상기 프리 에칭 공정에 사용되는 용액은 0.5~10중량%의 과산화수소와, 0.5~10중량%의 황산과, 0.5~10중량%의 저해제 및 85~95중량%의 물이 혼합되어 구성되는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 1 항에 있어서,
상기 C) 단계는 액상 탄소 분산 방식으로 이루어지며,
상기 액상 탄소 분산 방식의 탄소 분산 용액에 첨가되는 탄소 입자의 지름은0.05㎛~3.0㎛의 크기를 갖는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법. - 제 9 항에 있어서,
상기 C) 단계의 액상 탄소 분산 방식에 사용되는 용액은 물과, 전도성 탄소와 하나 이상의 계면활성제 및 액상 분산 중간체의 혼합물로 이루어지는 것을 특징으로 하는 다층 인쇄 회로 기판의 제조방법.
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KR20240015308A (ko) | 2022-07-27 | 2024-02-05 | 주식회사 피앤아이 | 인쇄회로기판의 스루홀 충진도금방법 |
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