KR101224948B1 - SRAM-type memory cell - Google Patents

Abstract

The present invention relates to an SRAM-type memory cell, wherein the SRAM-type memory cell comprises a semiconductor substrate on an insulator comprising a thin film 1 of semiconductor material separated from the base substrate 2 by an insulating (BOX) layer, And two array transistors arranged to form two back-coupled inverters together with two connection transistors T1 and T4, two conductive transistors T2 and T5, and the conductive transistors T2 and T5. Six transistors including charging transistors T3, T6, each of which are formed into the basal substrate 2 below the channel and for regulating the threshold voltage of the transistor; Rear control gates BG1 and BG2 that can be biased, a first rear gate line connecting the rear control gates of the connection transistors to a first potential, the conductive transistors and the charge transistors Having a second gate line connecting the back control gate of the room to the second potential, the first and second electrical potential are being adjusted according to the type of cell control operation.

Description

SRAM-type memory cell

The present invention relates to an SRAM-type memory cell formed on a semiconductor substrate on an insulator and comprising six transistors.

Static random access memory (SRAM) type memory cells are static RAM memories, that is, memories that do not require periodic refreshing.

Such memory cells consist of a collection of transistors.

A general concern in this field is how to reduce the size of the cells and how to reduce leakage currents.

If an SRAM cell is fabricated on a bulk substrate, the size reduction results in greater variability, which means that the dimensions of the transistors cannot be reduced very significantly, and are read to find the operating point. And write components must be separated from each other.

This entails an increase in the number of transistors (and therefore from six to eight or even ten transistors), followed by a disadvantage for the surface area.

Furthermore, on "bulk" type substrates, transistors have different dimensions depending on their function in the cell (transfer, charge, conduction).

The authors have suggested using an FD-SOI (abbreviation for "fully depleted SOI", including a rear control gate, describing a fully depleted structure fabricated on a silicon substrate over an insulator).

References to this view are described in Yamaoka et al. ("SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors", IEEE Journal of Solid-State Circuits, Vol. 41, No 11, Nov). 25, 2006) and Tsuchiya et al. ("Silicon on Thin BOX: A New Paradigm of the CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control", IEEE 2004). have.

Conventional SRAM cells typically include six transistors, i.e .:

Two access or transfer transistors: these are generally N channel field-effect transistors (NFETs).

Two charge transistors and two conductive transistors paired to form two back-coupled inverters: the charge transistors are, in theory, P-channel FET transistors (PFETs) and The conductive transistors are NFET transistors.

In the above publications, a rear control gate formed under the insulator is used to more precisely control the operating conditions of the transistors.

The rear control gate is a doped region formed under each transistor, and each group of underlying gates and transistors is an N + or P + type island insulated from others by a so-called " shallow trench isolation " Corresponding.

Thus, in an SRAM cell, the NFET transistors are grouped in pairs (each connected transistors and conductive transistors) in an island separated by a P region, while the PFET transistors are one and belong to the same island.

In practice, these two N regions are connected to one another in the periphery and to other regions of the same type for different columns. The same applies for the P region.

In the case of N-channel transistors, the region forming the rear control gate is P + type and is separated from the P type base substrate by an N conductive layer.

In the case of P channel transistors, the region forming the rear control gate is N + type.

A paper by Yamaoka et al. Discloses a rear control gate of P type and common to two charging transistors, and a rear control gate of N type conductive transistor and connection transistors.

In the paper by Tsuchiya et al., Each pair formed by the connecting transistors having the rear control gate connected to the ground and the charging transistor and the conductive transistor has a common rear control gate.

However, in these devices, the rear control gate includes a simple circuit well, which is defined by an isolation trench.

Furthermore, the choice of working in columns of wells does not contribute to the promotion of the modes of operation.

For example, a paper by Yamaoka describes N-connected transistors and N-conducting transistors having the same rear control gate, to ensure that their ratio remains constant regardless of the mode of operation and thus various functional modes. Limit margins for improvement.

Thus, research is focused on avoiding the shortcomings of existing devices and further reducing the dimensions of SRAM-type memory cells so that they can roughly conform to Moore's Law while improving the performance levels of such cells.

Accordingly, the problem to be solved by the present invention is to provide a memory cell that can enable the use of a minimum size transistor without reducing the stability of the memory cell.

According to the present invention, an SRAM-type memory cell is proposed, wherein the SRAM-type memory cell is:

A semiconductor substrate on the insulator comprising a thin film of semiconductor material separated from the base substrate by an insulating layer;

Six transistors comprising two connecting transistors, two conductive transistors, and two charging transistors arranged to form two back coupled inverters together with the two conductive transistors, each of said transistors A drain region and a source region arranged in the thin film, a channel extending between the source region and the drain region, and a front gate positioned on the channel,

Each of the transistors may be formed in the base substrate below the channel and may be biased to adjust the threshold voltage of the transistor, and to connect the rear control gates of the connection transistors to a first potential. And a first rear gate line and a second rear gate line connecting the conductive transistors and the charging transistors to a second potential, wherein the first and second potentials are adjusted according to a type of cell control operation. .

According to other characteristics of this cell:

The connection transistors and the conductive transistors are NFET transistors and the charging transistors are PFET transistors; The rear control gate of the connection transistors is N + conductive, and the rear control gate of the conductive transistors and charging transistors is N + conductive.

A rear control gate of the conductive transistors and the charging transistors is arranged in the well of the conductive opposite to the conductivity of the rear control gate, in the base substrate below the channel.

The memory cell is fully depleted.

Another technical idea of the present invention relates to a memory array comprising a plurality of memory cells as described above, wherein each channel of the transistors has a minimum physical width, but to the rear control gate of the transistor. It has an apparent width that can be adjusted through the application of a potential.

Another technical idea relates to the manufacturing method of the SRAM-type memory cell as described above, wherein the manufacturing method is:

Providing a semiconductor substrate over the insulator comprising the thin film of semiconductor material separated from the base substrate by an insulating layer,

Forming rear control gates in the base substrate via implantation.

Another technical idea of the present invention relates to the above-described control method of a memory cell, wherein the control method includes a so-called "high" positive voltage and a zero lower than the positive voltage for applying a bias to rear control gates of the transistors. A voltage or so-called "low" positive voltage is defined, and accordingly, depending on the type of cell control operation, a high or low voltage is dynamically applied to the rear control gate of the transistors.

According to other features of this control method:

The SRAM-type memory cell comprises a low voltage applied to the rear control gate of the connection transistors and to the rear control gate of the conductive and charging transistors during a standby operation.

The SRAM-type memory cell comprises a characteristic of applying a low voltage to the rear control gate of the connection transistors and a high voltage to the rear control gate of the conductive and charging transistors during a read operation.

The SRAM-type memory cell comprises a high voltage applied to the rear control gate of the connection transistors and a low voltage to the rear control gate of the conductive and charging transistors during a write operation.

According to embodiments of the present invention, the apparent size of a transistor can be dynamically adjusted through the use of an FD-SOI type substrate associated with a back gate for each transistor, thus ensuring stable read and write while minimizing current leakage. And standby mode may be performed. Furthermore, the FD-SOI substrate can be used to form non-doped channel transistors, thus eliminating the variability that can be obtained by the random distribution of the doping. This in turn enables the use of transistors of minimum size without reducing the stability of the memory cell.

Other features and advantages of the present invention will be derived from the accompanying drawings and the following detailed description, wherein:
1 is a circuit diagram of an SRAM cell according to the invention.
2 shows the topology of the SRAM cell.
3 is a view taken along the AA of the cell shown in FIG.
4 is a view taken along the BB of the cell shown in FIG.
5 shows a topology of an SRAM array comprising a plurality of cells according to the invention.
6 shows aspects of adjusting the threshold voltage of a transistor using a controlling rear control gate.

SRAM  Structure of the cell

1 shows a circuit diagram corresponding to an SRAM-type memory cell according to the present invention.

The memory cell includes six transistors T1 to T6.

Two of these transistors are connection transistors T1 and T4.

The transistors T1 and T4 are fabricated on a semiconductor on insulator substrate, each of which is controlled with a rear control gate BG1 and a front gate G that can be controlled to modify the operation of the transistor. Has

Preferably a rear gate line is used to jointly connect the rear control gates BG1 of the two connection transistors T1, T4 to one and the same potential, which makes it possible to provide easy and inexpensive control, but each It is also possible for the rear gates of to be individually connected to the potential.

The front gate G of each of the connection transistors T1 and T4 is connected to a word line WL.

Further, the drain electrodes of each of the connection transistors T1 and T4 are connected to the bit lines BL1 and BL2, respectively, and the bit line BL2 complements the bit line BL1.

The memory cell also includes two inverters, each of which includes charge transistors T3 and T6 and conductive transistors T2 and T5 connected in series between a power supply voltage VDD and ground GND. Each inverter includes an input consisting of front gates common with the series transistors and an output consisting of sources common with the series transistors.

These inverters are themselves back-coupled in a manner known in the art and the input of one inverter is connected to the output of the other and vice versa.

In addition, as with the connection transistors T1 and T4, it will be noted that the transistors T2, T3, T5 and T6 have a rear control gate BG2 in addition to the front gate G.

Preferably, a rear gate line is used to jointly connect the rear control gates BG2 of the transistors T2, T3, T5, T6 to one and the same potential, which makes it possible to provide easy and inexpensive control, However, it is also possible for each rear gate to be individually connected to the potential.

Preferably, the rear control gates BG1 and BG2 are not connected to the sources and the drains of the transistors T1-T6 and are independent. The voltages applied to the control rear gates BG1, BG2 are separated from the power supply voltage VDD and ground GND and are any one of a continuous range of values, for example VDD / 2 or VDD / 3. Can be.

The connection transistors T1 and T4 are used to control the connection to back-coupled inverters during read and write operations of the memory cell.

Thus, the source electrode of each connection transistor T1, T4 is connected with the output of one of the inverters and the input of the other inverter.

2 illustrates the topology of the corresponding memory cell.

3 is a view taken along the line A-A of the cell shown in FIG.

We will first focus on the connection transistor T1 (given descriptions are also valid for the second connection transistors T4).

The semiconductor substrate on the insulator comprises a thin film 1 of semiconductor material separated from the base substrate 2 by an insulating layer.

For example, the semiconductor substrate on the insulator is a silicon on insulator (SOI) substrate.

According to a preferred embodiment, the insulating layer is a buried oxide (hereinafter referred to as 'BOX') layer.

For example, the insulating layer may be silicon dioxide (SiO ₂ ).

Transistor T1 is an NFET transistor comprising a source region S, a drain region D, and a floating channel C extending between the source region and the drain region.

The drain D and source S regions are preferably in contact with the insulating BOX layer such that the transistor is fully depleted. The substrate is then determined as "FD SOI".

It is also possible for the transistor to be partially depleted, but because the thickness of the thin film of semiconductor material and the thickness of the insulating layer are larger, this technique is less advantageous and therefore the effect of the rear control gate is very weak (only a small percentage). (%)) Loses; Furthermore, in this case, the channel must be doped, which corresponds to a situation that can be compared with that of a bulk substrate in terms of variability.

The front gate G extends in a manner known per se on the surface of the substrate above the channel C and is separated from the channel C by the dielectric layer 3.

In the context of the present invention, the rear control gate BG1 of the transistor T1 is arranged in the base substrate 2 under the insulating BOX layer facing the channel C of the transistor.

As can also be seen in FIG. 3, transistor T2 is an NFET transistor (as with transistor T5), which extends between source region S, drain region D and between the source region and the drain region. Floating channel C.

The drain D and source S regions are preferably in contact with the insulating BOX layer such that the transistor is fully depleted.

The front gate G extends in a manner known per se on the surface of the substrate above the channel C and is separated from the channel C by the dielectric layer 3.

In the context of the present invention, the rear control gate BG2 of the transistor T2 is arranged in the base substrate 2 under the insulating BOX layer facing the channel C of the transistor.

Referring to FIG. 4, transistor T3 is a PFET transistor (as with transistor T6), which is a source region S, a drain region D, and a floating channel extending between the source region and the drain region. C).

The drain D and source S regions are preferably in contact with the insulating BOX layer such that the transistor is fully depleted.

Optionally, as described above, the transistors T2, T3, T5, T6 may also be partially depleted.

The front gate G extends in a manner known per se on the surface of the substrate above the channel C and is separated from the channel C by the dielectric layer 3.

In the context of the present invention, the rear control gate BG2 of the transistor T3 is arranged in the base substrate 2 below the insulating BOX layer facing the channel C of the transistor.

As a purely illustrative example, the thickness of the thin film 1 of the semiconductor substrate on the insulator is between 1.5 nm and 50 nm, and the thickness of the insulated BOX layer is between 1.5 and 50 nm.

If the rear control gate is such that it does not have any differential working function, the latter conductivity is the same type as that of the FET transistor (i.e., N-type conductivity for N-channel transistors, P-channel transistors). P type conductivity).

In order to minimize leakage currents in the standby mode, an ideal situation would be if the bottom of all of the transistors had an upper doped region of at least 10 ¹⁸ cm ³ and having an impurity concentration that is the opposite type of each of the transistors.

However, this requires the formation of three different rear control gates underneath the memory cell, which requires about 50% of the surface area of the cell since it requires reconnecting the rear control gates individually within each cell. It has a direct effect of increasing over.

Since the preferred goal is to minimize the dimensions of the transistors in order to minimize the surface area of the SRAM cell, the most appropriate trade-off has thus been defined.

Therefore, the connection transistors T1 and T4 are NFET transistors having a rear control gate BG1 of the N + type.

The conductive transistors T2 and T5 are NFET transistors having a rear control gate BG2 of N + type.

The charging transistors T3 and T6 are PFET transistors having a rear control gate BG2 of N + type.

As shown in Figs. 3 and 4, the rear control gates BG1 and BG2 are insulated from the base substrate 6 by a well indicated by reference numerals 4 and 5, and the wells 4 and 5 are respectively P-substrates. The substrate 2 has regions 4, 5, 6 with a bias opposite to that of.

Well 4 is N-type for N + rear control gate BG1; Well 5 is of the P- type for N + rear control gate BG2.

The voltages of the wells 4 and 5 are selected such that parasitic diodes generated by the electrical node between the rear control gate and the wells are always reversed, the diodes from and well behind the wells. The rear control gate is isolated from the control gate BG2.

In addition, as described above, the present invention relates to a memory array including a plurality of SRAM cells.

Such an array is shown in FIG. 5.

The array is composed of rows and columns.

By convention, the row is indicated in the direction of the word line (in the case of the present invention, which is also the direction of the rear control gate BG2 of the transistors T2, T3, T5, T6) in FIG. The column is in the direction of the bit line (consisting of metal), which is in the vertical direction (not shown in FIG. 5).

The array contains as many rows and columns as the application requires.

In the case of this invention, the memory cells have the special feature that they have rear control gates BG1 and BG2.

The rear control gate BG2 of the inverters is decoded in accordance with addressing (on the word line WL) on one side and by operation mode (read or write) on the other side.

The rear control gate BG1 modulates the connection transistors in the islands I (see FIG. 5).

The islands I are connected to each other by the well 4 at the bottom of the cell.

N + conductivity of the rear control gate BG1 is needed to prevent the formation of a diode and thus allow direct biasing under the transistor.

SRAM  Manufacturing method of the cell

SRAM cells are manufactured by conventional methods of aligning the masks with respect to each other.

For example, S.M. In Chapter 2 of the publication entitled "CMOS Digital Integrated Circuit Design: Analysis and Design" by Kang and Y. Leblebici (McGraw-Hill Publishing Co., New York, NY, 2003), a suitable method is described.

The levels located below the insulating BOX layer are all formed by implantation.

SRAM  Control the characteristics of transistors in the cell

In the context of the present invention, the rear control gates BG1 and BG2 are used dynamically: depending on the type of cell control operation (standby, read, write), the voltage applied to the rear control gates BG1 and BG2 is efficient. Stored as.

By biasing the rear control gate of each transistor with a positive voltage or with a negative voltage (typically by +/- 0.3 V), the characteristics of the transistor can be changed individually.

In particular, the threshold voltage of the transistor may be offset.

Unfortunately, changing the threshold voltage has the same meaning as changing the physical width of the channel.

Thus, in the context of the present invention, even though the physical width of the channel is defined once for all and for all transistors, for each transistor separately, the appearance of the channel of the transistor through the control of the rear control gate is apparent. It is possible to change the (valid) width of.

Since the voltage applied to the rear control gate can be changed, the present invention thus provides the advantage that the apparent width of the channel can be changed dynamically.

The variation of the threshold voltage of the transistor through the rear control gate can be expressed by the following equation.

는 트랜지스터의 문턱 전압을 나타내고,

는 후방 게이트에 인가된 전압이며,

는 (N 또는 P 타입의 후방 컨트롤 게이트가 사용되는지 여부에 따른 일함수에 의해 오프셋될 수 있는) 명목상의 문턱 전압이고,

는 트랜지스터의 기하특성(geometry)과 연계된 계수이다.here

Represents the threshold voltage of the transistor,

Is the voltage applied to the rear gate,

Is the nominal threshold voltage (which can be offset by the work function depending on whether a rear control gate of type N or P is used),

Is the coefficient associated with the geometry of the transistor.

는 다음 관계에 따라 모델링될 수 있다.In particular, the coefficient

Can be modeled according to the following relationship:

은 채널로부터 전방 게이트를 분리시키는 게이트 유전 층의 두께를 지정하고,

는 채널로부터 후방 컨트롤 게이트를 분리시키는 절연 층의 두께를 지정하며,

는 박막의 두께를 지정한다.here

Specifies the thickness of the gate dielectric layer separating the front gate from the channel,

Specifies the thickness of the insulation layer separating the rear control gate from the channel,

Specifies the thickness of the thin film.

Thus, it will be understood that the doping type of the rear control gate of the transistor may or may not offset the nominal threshold voltage and the biasing of the rear control gate makes it possible to adjust the threshold voltage.

)의 증가, 및 (문턱 전압의 증가에 의한) 트랜지스터의 비활성 상태에서의 누설 전류(

)의 감소로부터 이익을 얻는 것이 가능하다.Thus, the conduction current in the active state of the transistor (by decreasing the threshold voltage)

) And leakage current in the inactive state of the transistor (by increasing the threshold voltage)

It is possible to benefit from the reduction of.

Thereafter, the threshold voltages may be reduced by applying a positive voltage in the case of an N transistor and a voltage smaller than VDD in the case of a P transistor.

Furthermore, the present invention is not only limited to the use of zero or positive rear control gate voltages, but also extends to the use of zero or negative rear control gate voltages.

는 급격하게 감소한다.Coefficients above if silicon and box thicknesses are too large

Decreases sharply.

의 경우, 여기에 0.15 V의 일함수가 더해져, 0.5 V의 문턱 전압

이 얻어진다.For example, 0.35 V

In this case, the work function of 0.15 V is added to the threshold voltage of 0.5 V

Is obtained.

이 0.2 V까지 도달하도록 하는 것을 동작 모드가 요구하는 경우,

는 0.3이어야 한다(파워 공급 전압 VDD = 1 V).Threshold voltage to operate

If the mode of operation requires that this be reached to 0.2 V,

Must be 0.3 (power supply voltage VDD = 1 V).

If the thickness ratios do not allow this, the work function must be reduced (via process refinement) to achieve the required voltage of 0.2 V in the operating mode.

Of course it is necessary to compensate for the negative rear control gate voltage in other modes to find the required 0.5 V in these modes.

FIG. 6 is a SOI (or, generally, a semiconductor over insulating dielectric (SeOI) as a control by biasing a rear control gate arranged in the base substrate under the insulating layer facing the channel of the transistor). Shows control of the transistor fabricated on the substrate.

의 예를 나타낸다. In this figure, the center curve Cn is nominal (in the case of a transistor without a rear control gate).

An example is shown.

의 값들이 100 μA /μm 내지 2000 μA /μm 범위로 변화할 수 있고,

전류는 아마도 1 fA/μm 내지 30 nA/μm 범위로 변화한다는 것이 확실하다.The following values are examples only. According to technology

The values of can vary from 100 μA / μm to 2000 μA / μm,

It is certain that the current will probably vary in the range from 1 fA / μm to 30 nA / μm.

및

전류들은 각각 150 μA/μm 및 5 nA/μm에서 설정된다.

And

Currents are set at 150 μA / μm and 5 nA / μm, respectively.

는 0 V에서 제어되고 일함수를 가지는 후방 컨트롤 게이트의 효과 하에서의 명목상의 특성

을 나타낸다. 이 하부 커브는 문턱 전압의 상승을 도시한다.

및

전류들은 각각 100 μA/μm 및 200 pA/μm에서 설정된다.Lower curve

Is a nominal characteristic under the effect of a rear control gate controlled at 0 V and having a work function

Indicates. This lower curve shows the rise of the threshold voltage.

And

Currents are set at 100 μA / μm and 200 pA / μm, respectively.

는 명목상의 파워 공급 전압 VDD에서 제어되고 일함수를 가지지 않는 후방 컨트롤 게이트의 효과 하에서의 명목상의 특성

을 나타낸다. 이 상부 커브는 문턱 전압의 감소를 도시한다.

및

전류들은 각각 200 μA/μm 및 100 μA/μm에서 설정된다.Upper curve

Is the nominal characteristic under the effect of a rear control gate that is controlled at the nominal power supply voltage VDD and has no work function.

Indicates. This upper curve shows the reduction of the threshold voltage.

And

Currents are set at 200 μA / μm and 100 μA / μm, respectively.

및

을 조절하는 것에 의해. 하부

와 상부

사이의 공간들 모두가 커버될 수 있음이 이해될 것이다.Thus, by biasing the rear control gate with a positive or negative voltage, the threshold voltage of the transistor and its characteristic currents are thus

And

By adjusting it. bottom

And upper part

It will be appreciated that all of the spaces in between may be covered.

및

의 실질적인 변동에 반영된다.The present invention allows for a reduction / increase in the apparent width of the channel so that all increases as the power supply voltage decreases.

And

Is reflected in the substantial variation in

In this regard, it will be noted that a trend in the technical field of the present invention is to utilize electronic components at low power supply voltages for the next generation. Thus, the present invention is a preori for the next generation, with even more benefits.

A detailed description will now be given of how to control a memory cell in three operation modes: standby, write and read operation modes.

Waiting mode

As shown in the table below, in the standby mode, the connection transistors T1 and T4 are blocked, which causes the inverters of the bit lines BL1 and BL2 to be disconnected.

The power supply voltage VDD is applied to the well 5 including the base substrate 2 and the rear control gate BG2, while the zero voltage includes the well (including the rear control gate BG1). 4) is applied.

은 접속 트랜지스터들(T1, T4)의 후방 컨트롤 게이트(BG1)에 인가된다. Lower voltage than VDD

Is applied to the rear control gate BG1 of the connection transistors T1 and T4.

Therefore, the threshold voltages of the transistors T1 and T4 increase and are weighted when the BG voltage is low.

및 누설 전류

가 최소화된다는 것이다(아래 표에서 - 부호로 나타남).The result of this is the conductive current

And leakage current

Is minimized (indicated by the minus sign in the table below).

는 트랜지스터들(T2, T3, T5, T6)의 후방 컨트롤 게이트(BG2)에 인가된 전압을 나타낸다.

Denotes the voltage applied to the rear control gate BG2 of the transistors T2, T3, T5, and T6.

은 감소한다.In the standby mode, the voltage

Lt; / RTI >

Thus, for the NFET transistors T2 and T5, the leakage current is reduced.

For the PFET transistors T3 and T6, the leakage current can be large; However, in SRAM cells, PFET transistors are generally used that are low conductivity and have little leakage characteristics.

Thus, leakages in the memory cell resulting from the bit lines are minimized.

writing mode

In the write mode, a high power supply voltage is applied to the well 4 including the rear control gate BG1; The well 5 including the rear control gate BG2 is connected to the ground GND.

가 유지된다.Low voltage to the rear control gate of the transistors T2, T3, T5, T6 forming the inverters

Is maintained.

Thus, like the weak PFET transistors T3 and T6 because of their structure, the NFET transistors T2 and T5 remain weak.

The voltage of the well 4 is transferred to the rear control gate BG1 of the connection transistors T1 and T4.

)을 야기한다.This causes the threshold voltages of the above-described transistors to be reduced and therefore the transistors are " boosted " (higher currents).

Cause.

Thus, the above conditions applied to (powerful) connection transistors on one side and weak inverters on the other side make it possible to easily pass from the bit lines to the memory cell to perform a write operation.

read mode

In the read mode, a low power supply voltage is applied to the well 4 including the rear control gate BG1, which is transferred to BG1. The base substrate under the well 4 remains connected to GND. The well 5 including the rear control gate BG2 is grounded.

(예를 들어, 대략 VDD의 차수)가 인버터들을 형성하는 트랜지스터들(T2, T3, T5, T6)의 후방 컨트롤 게이트(BG2)에 인가된다.High positive voltage

(Eg, on the order of VDD) is applied to the rear control gate BG2 of the transistors T2, T3, T5, T6 forming the inverters.

PFET transistors T3 and T6 are weak because of their structure, while NFET transistors T2 and T5 become stronger and the apparent width of these channels is increased.

은 낮다.Voltage applied to the rear control gate for the connection transistors T1 and T4

Is low.

The conditions applied to (weak) connection transistors on one side and strong inverters on the other side, while providing sufficient read signal to be sensed by the peripheral amplifier, do not cause any disturbances by BL voltages. It is possible to prevent the contents of).

Advantages of the present invention are as follows.

The use of an FD-SOI type substrate associated with the back gate for each transistor makes it possible to adjust the apparent size of the transistor in order to obtain guaranteed read, easy write and standby modes while minimizing leakages.

Furthermore, the FD-SOI substrate can be used to form non-doped channel transistors, eliminating the variability that can be obtained by the random distribution of the doping. This enables the use of transistors of minimum size without reducing the stability of the memory cell.

The present invention applies the ratios for the modes of operation and thus improves the margins of the respective modes without yielding the correct operation of the other modes.

Also, the operation is done in rows (parallel to word line WL, all cells are activated according to this WL) and thus do not disturb other cells in the column.

All these conditions make it possible to further reduce the dimensions of the transistors and hence the cell.

The examples given so far are completely specific and do not limit the field of applications of the invention in any way.

Thus, the memory cell may also operate in a so-called "sub-threshold" mode, where the power supply voltage VDD is less than the threshold voltages.

This type of cell has certain benefits in very low power applications.

The SRAM cell according to the invention operates with lower power supply voltages VDD than conventional "sub-threshold" cells, making it possible to reduce the threshold voltages as much as possible, and the voltage VDD being lower.

As a result, leakage currents are reduced more efficiently than existing cells.

Claims (10)

A semiconductor substrate on an insulator comprising a thin film 1 of semiconductor material separated from the base substrate 2 by an insulating (BOX) layer;
Two charge transistors arranged to form two back-coupled inverters together with two connection transistors T1 and T4, two conductive transistors T2 and T5, and the conductive transistors T2 and T5. Six transistors T1-T6 comprising transistors T3, T6, wherein the two connection transistors T1, T4 control the connection to the back-coupled inverters, the transistor Each of the ones T1 to T6 may include a source region S and a drain region D arranged in the thin film 1, a channel C extending between the source region and the drain region, and the channel C. Includes, the transistors T1-T6 including a front gate G positioned on
Each of the transistors T1-T6 is formed into the base substrate 2 under the channel C, and can be biased to adjust the threshold voltage of the transistors T1-T6. BG2, a first rear gate line connecting the rear control gates BG1 of the connection transistors T1 and T4 to a first potential, the conductive transistors T2 and T5 and the charging transistors Having a second rear gate line connecting rear control gates BG2 of T3, T6 to a second potential,
And said first and second potentials are adjusted according to a type of cell control operation. The method of claim 1,
The connection transistors T1 and T4 and the conductive transistors T2 and T5 are N-type field effect transistor (NFET) transistors,
The charging transistors T3 and T6 are P-type field effect transistor (PFET) transistors,
The rear control gate BG1 of the connection transistors T1 and T4 is N + conductive.
And a rear control gate (BG2) of the conductive transistors (T2, T5) and charge transistors (T3, T6) are N + conductive. The method of claim 1,
The rear control gate BG2 of the conductive transistors T2 and T5 and the charging transistors T3 and T6 are in the base substrate 2 below the channel C, and the rear control gate BG2. SRAM-type memory cell, characterized in that arranged in the conductive well (5) as opposed to the conductivity of. The method of claim 1,
SRAM-type memory cell, characterized in that the transistors (T1-T6) are completely depleted. A memory array comprising a plurality of SRAM-type memory cells according to any one of claims 1 to 4, wherein
The channel of each of the transistors T1-T6 has a physical width, but can be adjusted via application of a potential to the rear control gates BG1, BG2 of the transistors T1-T6. A memory array having an effective width. A method of manufacturing an SRAM-type memory cell according to claim 1,
SRAM-type memory cells,
Providing a semiconductor substrate on said insulator comprising said thin film (1) of semiconductor material separated from said base substrate (2) by an insulating (BOX) layer; And
Forming implanted rear control gates (BG1, BG2) in the base substrate (2) by implantation. In the control method of a memory cell according to any one of claims 1 to 4,
A first positive voltage and a zero voltage or a second positive voltage lower than the first positive voltage are defined to apply a bias to the rear control gates BG1 and BG2, and according to the type of cell control operation, A first positive voltage or the second positive voltage or the zero voltage is dynamically applied to the rear control gates BG1 and BG2, The method of claim 7, wherein
The SRAM-type memory cell is connected to the rear control gate BG1 of the connection transistors T1 and T4 and to the conductive transistors T2 and T5 and the charging transistors T3 and T6 during a standby operation. And applying the first positive voltage to the rear control gate (BG2). The method of claim 7, wherein
The SRAM-type memory cell may have the second positive voltage, the conductive transistors T2 and T5 and the charging transistors at the rear control gate BG1 of the connection transistors T1 and T4 during a read operation. And applying the first positive voltage to the rear control gate (BG2) of T3 and T6. The method of claim 7, wherein
The SRAM-type memory cell may include the first positive voltage, the conductive transistors T2 and T5 and the charging transistors at the rear control gate BG1 of the connection transistors T1 and T4 during a write operation. And applying the second positive voltage to the rear control gate (BG2) of T3 and T6.

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