KR101143042B1 - Package substrate for mounting semiconductor element and method for manufacturing the package substrate - Google Patents

Package substrate for mounting semiconductor element and method for manufacturing the package substrate Download PDF

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Publication number
KR101143042B1
KR101143042B1 KR1020107024798A KR20107024798A KR101143042B1 KR 101143042 B1 KR101143042 B1 KR 101143042B1 KR 1020107024798 A KR1020107024798 A KR 1020107024798A KR 20107024798 A KR20107024798 A KR 20107024798A KR 101143042 B1 KR101143042 B1 KR 101143042B1
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South Korea
Prior art keywords
cavity
layer
connection
adhesive
plating
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KR1020107024798A
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Korean (ko)
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KR20100130640A (en
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타다시 타무라
마나부 스기바야시
쿠니지 스즈키
키요오 핫토리
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히다치 가세고교 가부시끼가이샤
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Publication of KR20100130640A publication Critical patent/KR20100130640A/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards

Abstract

본 발명은, PoP를 구성하는 경우에 있어서, 조합시키는 패키지의 자유도가 크고, 패턴설계상의 제약도 작고, 상부 패키지와 하부 패키지 사이의 접속을 고밀도로 행하는 것이 가능한 반도체소자 탑재용 패키지 기판과 그 제조방법을 제공하는 것을 목적으로 한다. 본 발명은, 캐비티재와 접착제를 구비하고, 이들을 관통하는 캐비티층과, 상기 접착제에 의해 상기 캐비티층에 적층된 베이스층과, 상기 개구에 의해 형성된 캐비티부와, 상기 관통공에 의해 형성된 바닥을 갖는 비아 를 갖는 반도체소자 탑재용 패키지 기판에 있어서, 상기 캐비티층에 내층회로가 설치되고, 이 내층회로와 접합하도록, 상기 바닥을 갖는 비아의 내벽에 금속피복이 도금에 의해 형성되고, 상기 바닥을 갖는 비아에 도전수지가 충전되는 반도체소자 탑재용 패키지 기판과 그 제조방법이다.According to the present invention, in the case of constituting a PoP, a package substrate for semiconductor element mounting and its manufacture, which have a large degree of freedom in the package to be combined, a small limit in pattern design, and a high density connection between the upper package and the lower package can be performed. It is an object to provide a method. The present invention includes a cavity material and an adhesive, a cavity layer penetrating them, a base layer laminated on the cavity layer by the adhesive, a cavity portion formed by the opening, and a bottom formed by the through hole. In a package substrate for mounting a semiconductor device having vias having an inner layer, an inner layer circuit is provided in the cavity layer, and a metal coating is formed on the inner wall of the via having the bottom by plating so as to bond with the inner layer circuit. A package substrate for mounting a semiconductor device in which a conductive resin is filled in a via having a via, and a manufacturing method thereof.

Description

반도체소자 탑재용 패키지 기판과 그 제조방법{PACKAGE SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE PACKAGE SUBSTRATE}PACKAGE SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE PACKAGE SUBSTRATE}

본 발명은, 고밀도화가 가능한 반도체소자 탑재용 패키지 기판과 그 제조방법에 관한 것이다.The present invention relates to a semiconductor substrate mounting package substrate capable of high density and a method of manufacturing the same.

전자부품의 소형화나 고밀도화에 따라, 시스템화된 반도체소자 탑재용 패키지 기판이 요구되고 있다. SiP(System in Package)로 대표되는 PoP(Package on Package)에서는, 하나의 반도체소자 탑재용 패키지 기판에 하나의 반도체소자를 실장하는 방법이 일반적이었다. 최근, 하나의 반도체소자 탑재용 패키지 기판에 반도체소자를 복수로 겹쳐 쌓은 패키지가 주류로 되고 있다. BACKGROUND With the miniaturization and high density of electronic components, systemized package boards for mounting semiconductor elements are required. In Package on Package (PoP) represented by SiP (System in Package), a method of mounting one semiconductor device on one semiconductor device mounting package substrate has been common. In recent years, packages in which a plurality of semiconductor devices are stacked on one package of semiconductor device mounting have become mainstream.

그러나, 반도체 패키지에서는, 반도체소자의 보호를 위해 포팅레진(potting resin) 등으로 코팅할 필요가 있다. 그 때문에, 하나의 반도체소자 탑재용 패키지 기판에 반도체소자를 복수로 겹쳐 쌓은 패키지에서는, 패키지의 전체 높이가 두껍게 되어 박형화(薄型化) 대응이 곤란했다. 또한, 이 전체 두께가 두껍게 된 패키지끼리를 겹쳐 쌓을 때는, 도 7에 나타낸 바와 같이, 접속단자A(14)보다 높게 솟아오른 봉지제(封止劑,3)가, 하부 패키지(35)와 상부 패키지(34)의 접속을 저해하기 때문에, 봉지제(3)의 높이보다 직경이 큰 땜납볼(38)(예를 들면, φ 0.6mm이상. 또한, 이하에서 φ는 직경을 나타낸다)을 이용하여, 상부 패키지(34)와 하부 패키지(35) 사이의 접속을 행할 필요성이 있다. 이렇게 하여 패키지끼리를 접속한 경우, 접속에 사용되는 땜납볼(38)의 직경(즉, 단자간 거리(44))의 반 이상의 높이로, 봉지제(3)가 솟아오른 상태가 되는 것이 일반적이었다. 땜납볼(38)의 직경이 크면, 이 땜납볼(38)을 사용하여 접속하는 접속단자A(14)의 직경과 피치도, 그것에 맞추어 확대하지 않을 수 없다. 이 때문에, 이들 패키지 사이의 접속에 사용되는 땜납볼(38)의 직경이 크게 되기 때문에, 접속단자A(14)의 크기와 피치를 미세화하는 것이 곤란했다.However, in the semiconductor package, it is necessary to coat with a potting resin or the like for the protection of the semiconductor device. Therefore, in a package in which a plurality of semiconductor devices are stacked on one package for mounting a semiconductor element, the overall height of the package becomes thick and it is difficult to cope with thinning. In addition, when stacking the packages which became thick in the whole thickness, as shown in FIG. 7, the sealing agent 3 which rose higher than the connection terminal A14, the lower package 35 and the upper part. Since the connection of the package 34 is impeded, a solder ball 38 having a diameter larger than the height of the encapsulant 3 (for example, φ 0.6 mm or more. In the following, φ represents a diameter). There is a need to make a connection between the upper package 34 and the lower package 35. In this way, when packages were connected, it was common that the sealing agent 3 rose to the height more than half of the diameter (namely, the distance 44 between terminals) of the solder ball 38 used for connection. . If the diameter of the solder ball 38 is large, the diameter and pitch of the connection terminal A 14 connected by using the solder ball 38 also must be enlarged accordingly. For this reason, since the diameter of the solder ball 38 used for the connection between these packages becomes large, it was difficult to refine | miniaturize the magnitude | size and pitch of the connection terminal A14.

그래서, PoP용의 반도체소자 탑재용 패키지 기판에서는, 위쪽이 되는 상부 패키지용 기판에 설치한 캐비티부(cavity section)에, 아래쪽이 되는 하부 패키지의 반도체소자의 일부가 수용되도록 한 것(인용문헌 1), 하부 패키지용의 기판에 캐비티부를 설치하여, 복수로 겹쳐 쌓은 반도체소자를 수용하는 것(인용문헌 2)이 알려져 있다.Therefore, in a package substrate for mounting a semiconductor device for PoP, a part of the semiconductor device of the lower package to be lowered is accommodated in a cavity section provided in the upper package substrate to be upper (Citation Document 1). ), It is known to accommodate a plurality of stacked semiconductor elements by providing a cavity on a substrate for a lower package (Citation Document 2).

특허문헌 1: 일본공개특허 2007-221118호 공보Patent Document 1: Japanese Patent Application Laid-Open No. 2007-221118 특허문헌 2: 일본공개특허 2008-016819호 공보Patent Document 2: Japanese Patent Application Laid-Open No. 2008-016819

그러나, 인용문헌 1에서는, 하부 패키지의 상방측(상부 패키지 측)은 봉지제가 볼록상태로 되어 있기 때문에, 조합시킬 수 있는 상부 패키지가 한정되고, 자유도가 작은 문제가 있다. 또한, 인용문헌 2에서는, 캐비티부를 설치하기 위해 절연층이 형성되고, 이 절연층을 통한 외부접속단자와의 층간접속을, 관통공에 금속층을 전기도금으로 충전하여 행하기 때문에, 전기도금을 위한 도금리드가 필요하게 되어, 고밀도화와 설계상의 제약이 있다.However, in the reference document 1, since the sealing agent is convex on the upper side (upper package side) of the lower package, the upper package which can be combined is limited, and there is a problem that the degree of freedom is small. In addition, in Reference Document 2, an insulating layer is formed to provide a cavity portion, and an interlayer connection with an external connection terminal via the insulating layer is performed by filling a through hole with a metal layer by electroplating. There is a need for plating leads, which leads to densification and design constraints.

이 문제를 해결하는 방법으로서, 도 6에 나타낸 바와 같이, 캐비티부(9)를 설치하기 위한 절연층(캐비티층(5))의 층간접속(31)을, 도전수지(17)를 이용하여 행하는 방법이 고려될 수 있다.As a method for solving this problem, as shown in FIG. 6, the interlayer connection 31 of the insulating layer (cavity layer 5) for providing the cavity portion 9 is performed using the conductive resin 17. The method can be considered.

그러나, 캐비티층(5)은 캐비티부(9)를 형성하기 때문에 개구율(開口率)이 크고, 한편, 베이스(base)층(6)은, 반도체소자(2)와 전기적인 접속용의 단자를 인출하기 때문에, 고밀도인 다층구조로 되기 위해, 양자는 개구율과 층 구성이 크게 다른 것이 일반적이다. 이 때문에, 캐비티층(5)과 베이스층(6)에서는 제조시와 사용시의 치수변화 거동이 달라, 층간접속(31)에 도전수지(17)를 사용한 경우는, 접속신뢰성을 확보하는 것이 어렵다는 문제점이 있다.However, since the cavity layer 5 forms the cavity portion 9, the aperture ratio is large, while the base layer 6 provides a terminal for electrical connection with the semiconductor element 2. In order to obtain a high-density multi-layer structure because of drawing out, it is common that both have a large difference in aperture ratio and layer structure. For this reason, the cavity layer 5 and the base layer 6 have different dimensional change behavior during manufacture and use, and it is difficult to secure connection reliability when the conductive resin 17 is used for the interlayer connection 31. There is this.

본 발명은, 상기 문제점을 감안하여 이루어진 것으로, PoP를 구성하는 경우에 있어서, 조합시키는 패키지의 자유도가 크고, 패키지 설계상의 제약도 작고, 상부 패키지와 하부 패키지 사이의 접속을 고밀도로 행하는 것이 가능하며, 게다가 신뢰성이 우수한 반도체소자 탑재용 패키지 기판과 그 제조방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in the case of constituting a PoP, the degree of freedom of the package to be combined and the package design is small, and the connection between the upper package and the lower package can be performed at a high density. In addition, an object of the present invention is to provide a package substrate for mounting a semiconductor device having excellent reliability and a method of manufacturing the same.

본 발명은, 이하의 것에 관한 것이다.The present invention relates to the following.

(1) 캐비티재와 접착제를 구비하고, 이들을 관통하는 개구 및 관통공을 갖는 캐비티층과, 상기 접착제에 의해 상기 캐비티층에 적층된 베이스층과, 상기 개구에 의해 형성된 캐비티부와, 상기 관통공에 의해 형성된 바닥을 갖는 비아(via)를 갖는 반도체소자 탑재용 패키지 기판에 있어서, 상기 캐비티층에 내층회로가 설치되고, 이 내층회로와 접합하도록, 상기 바닥을 갖는 비아의 내벽에 금속피복이 도금에 의해 형성되고, 상기 바닥을 갖는 비아에 도전수지가 충전되는 반도체소자 탑재용 패키지 기판.(1) a cavity layer having a cavity material and an adhesive and having openings and through holes therein; a base layer laminated to the cavity layer by the adhesive; a cavity portion formed by the opening; and the through hole In a package substrate for mounting a semiconductor device having a via having a bottom formed by a semiconductor substrate, an inner layer circuit is provided in the cavity layer, and a metal coating is plated on the inner wall of the via having the bottom so as to be bonded to the inner layer circuit. And a conductive resin filled in the via having a bottom thereof.

(2) 상기 (1)에 있어서, 바닥을 갖는 비아가, 캐비티재(cavity material)와 접착제를 관통하여, 베이스층상의 캐비티층 측에 설치되는 접속패드에 이르도록 설치되어, 상기 접속패드와, 상기 캐비티층상의 베이스층과 반대측에 설치되는 접속단자A를 접속하는 층간접속이 형성되는 반도체소자 탑재용 패키지 기판.(2) In the above (1), the via having a bottom penetrates the cavity material and the adhesive to reach the connection pad provided on the cavity layer side on the base layer. A package substrate for mounting a semiconductor element, wherein an interlayer connection is formed to connect a connection terminal A provided on the side opposite to the base layer on the cavity layer.

(3) 상기 (1) 또는 (2)에 있어서, 캐비티층에 설치되는 내층회로가 관통공의 주위에 설치되는 환상링(annular ring)이고, 이 환상링과 바닥을 갖는 비아의 내벽에 형성되는 금속피복이 내층접속을 형성하는 반도체소자 탑재용 패키지 기판.(3) In the above (1) or (2), the inner layer circuit provided in the cavity layer is an annular ring provided around the through hole, and is formed on the inner wall of the via having the annular ring and the bottom. A package substrate for mounting a semiconductor element, wherein a metal coating forms an inner layer connection.

(4) 상기 (1) 내지 (3) 중 어느 하나에 있어서, 캐비티층에 설치되는 내층회로가, 상기 캐비티재 상의 접착제 측에 설치되는 반도체소자 탑재용 패키지 기판.(4) The semiconductor device mounting package substrate according to any one of (1) to (3), wherein the inner layer circuit provided in the cavity layer is provided on the adhesive side on the cavity material.

(5) 상기 (1) 내지 (4) 중 어느 하나에 있어서, 캐비티층에 설치되는 접착제의 두께가, 내층회로에 대응하는 부분에서, 내층회로에 대응하지 않는 부분에 비하여 얇은 반도체소자 탑재용 패키지 기판.(5) The package for mounting a semiconductor element according to any one of (1) to (4), wherein the thickness of the adhesive provided in the cavity layer is thinner than the portion not corresponding to the inner layer circuit in the portion corresponding to the inner layer circuit. Board.

(6) 상기 (1) 내지 (5) 중 어느 하나에 있어서, 캐비티층과 베이스층을 적층하기 위한 접착제가 엘라스토머재인 반도체소자 탑재용 패키지 기판.(6) The package substrate for mounting a semiconductor element according to any one of (1) to (5), wherein the adhesive for laminating the cavity layer and the base layer is an elastomer material.

(7) 개구와 관통공과 내층회로를 갖는 캐비티재를 형성하는 공정과,(7) forming a cavity material having an opening, a through hole, and an inner layer circuit;

이 캐비티재에 접착제를 통해서 베이스층을 적층하고, 상기 개구에 의해 캐비티부를, 상기 관통공에 의해 바닥을 갖는 비아를 형성하는 공정과, 상기 바닥을 갖는 비아의 내벽에 금속피복을 형성하고, 이 금속피복과 상기 내층회로와의 내층접속을 형성하는 공정과, 상기 금속피복을 하지(下地)로 하여 상기 바닥을 갖는 비아에 도전수지를 충전하는 공정을 갖는 반도체소자 탑재용 패키지 기판의 제조방법.The base layer is laminated to this cavity material through an adhesive agent, and a cavity part is formed by the said opening by the said through-hole, and the metal coating is formed in the inner wall of the via via which the bottom part is formed, A method of manufacturing a package substrate for mounting a semiconductor device, comprising: forming an inner layer connection between a metal coating and the inner layer circuit; and filling a conductive via in the bottom via with the metal coating.

본 발명에 의하면, PoP를 구성하는 경우에 있어서, 조합시키는 패키지의 자유도가 크고, 패턴설계 상의 제약도 작고, 상부 패키지와 하부 패키지 사이의 접속을 고밀도로 행하는 것이 가능하며, 게다가 신뢰성이 우수한 반도체소자 탑재용 패키지 기판과 그 제조방법을 제공할 수 있다.According to the present invention, in the case of constituting a PoP, there is a large degree of freedom in the package to be combined, a small limit in pattern design, and the connection between the upper package and the lower package can be performed at a high density, and the semiconductor device is excellent in reliability. The mounting package substrate and its manufacturing method can be provided.

도 1은 본 발명의 실시예의 반도체소자 탑재용 패키지 기판 및 반도체 패키지의 단면도이다.
도 2는 본 발명의 실시예의 반도체소자 탑재용 패키지 기판 및 반도체 패키지의 일부를 확대한 단면도이다.
도 3은 본 발명의 실시예의 캐비티층의 제조공정을 나타내는 흐름도이다.
도 4는 본 발명의 실시예의 베이스층의 제조공정을 나타내는 흐름도이다.
도 5는 본 발명의 실시예의 캐비티부를 갖는 반도체 탑재용 패키지 기판의 제조공정을 나타내는 흐름도이다.
도 6은 본 발명의 반도체소자 탑재용 패키지 기판 및 반도체 패키지를 이용한 PoP의 개략의 단면도이다.
도 7은 종래의 반도체소자 탑재용 패키지 기판 및 반도체 패키지를 이용한 PoP의 개략의 단면도이다.1 is a cross-sectional view of a semiconductor device mounting package substrate and a semiconductor package according to an embodiment of the present invention.
2 is an enlarged cross-sectional view of a portion of a semiconductor device mounting package substrate and a semiconductor package according to an embodiment of the present invention.
3 is a flow chart showing a manufacturing process of the cavity layer of the embodiment of the present invention.
4 is a flowchart showing a manufacturing process of the base layer of the embodiment of the present invention.
Fig. 5 is a flowchart showing a manufacturing process of a semiconductor mounting package substrate having a cavity portion according to the embodiment of the present invention.
6 is a schematic cross-sectional view of a PoP using a semiconductor device mounting package substrate and a semiconductor package of the present invention.
7 is a schematic cross-sectional view of a conventional semiconductor device mounting package substrate and a PoP using a semiconductor package.

본 발명의 반도체소자 탑재용 패키지 기판(1)으로서는, 도 1, 도 2에 나타낸 바와 같이, 개구(25)를 갖는 캐비티층(5)과, 이 캐비티층(5)에 적층된 베이스층(6)과, 상기 개구(25)에 의해 형성된 캐비티부(9)를 갖는 반도체소자 탑재용 패키지 기판(1)으로서, 상기 캐비티층(5)을 관통하여, 상기 베이스층(6)의 접속패드(11)와 상기 캐비티층(5) 상의 접속단자A(14)를 접속하는 층간접속(31)이 설치되고, 이 층간접속(31)이 도전수지(17)에 의해 형성되는 반도체소자 탑재용 패키지 기판(1)을 들 수 있다.As the semiconductor device mounting package substrate 1 of this invention, as shown to FIG. 1, FIG. 2, the cavity layer 5 which has the opening 25 and the base layer 6 laminated | stacked on this cavity layer 5 are shown. ) And a package substrate 1 for mounting a semiconductor device having a cavity 9 formed by the opening 25, penetrating through the cavity layer 5 and connecting pads 11 of the base layer 6. ) And an interlayer connection 31 for connecting the connection terminal A 14 on the cavity layer 5, and the interlayer connection 31 is formed of a conductive resin 17. 1) may be mentioned.

또한, 본 발명의 반도체 패키지 기판(1)을 이용하여 제작한 반도체 패키지(36)로서는, 도 1, 도 2에 나타낸 바와 같이, 캐비티부(9)를 갖는 반도체소자 탑재용 패키지 기판(1)과, 상기 캐비티부(9) 안에 탑재된 반도체소자(2)와, 이 반도체소자(2)를 봉지하는 봉지제(封止劑)(3)와, 상기 반도체소자 탑재용 패키지 기판(1)의 한쪽면에 형성된 접속단자A(14)와, 다른쪽 면에 형성된 접속단자B(15)를 갖는 반도체 패키지(36)로서, 상기 캐비티부(9)가, 개구(25)를 갖는 캐비티층(5)과, 이 캐비티층(5)에 적층된 베이스층(6)에 의해 형성되고, 상기 캐비티층(5)에 상기 베이스층(6) 상의 접속패드(11)와 상기 캐비티층(5) 상의 접속단자A(14)를 접속하는 층간접속(31)이 설치되고, 이 층간접속(31)이 도전수지(17)에 의해 형성되는 반도체 패키지(36)를 들 수 있다.In addition, as the semiconductor package 36 manufactured using the semiconductor package substrate 1 of this invention, as shown in FIG. 1, FIG. 2, the semiconductor element mounting package substrate 1 which has the cavity part 9, A semiconductor element 2 mounted in the cavity portion 9, an encapsulant 3 for encapsulating the semiconductor element 2, and one side of the semiconductor element mounting package substrate 1; A semiconductor package 36 having a connecting terminal A 14 formed on a surface and a connecting terminal B 15 formed on the other surface, wherein the cavity portion 9 has a cavity layer 5 having an opening 25. And a base layer 6 laminated on the cavity layer 5, and a connection pad 11 on the base layer 6 and a connection terminal on the cavity layer 5 to the cavity layer 5. The semiconductor package 36 in which the interlayer connection 31 which connects A14 is provided, and this interlayer connection 31 is formed of the conductive resin 17 is mentioned.

이와 같이, 본 발명의 반도체소자 탑재용 패키지 기판(1) 및 반도체 패키지(36)에서는, 도전수지(17)에 의해, 캐비티층(5)의 층간접속(31)을 형성하기 때문에, 소위 필드비아도금에 의해 층간접속(31)을 형성하는 경우와 달리, 급전(給電)을 위한 도금리드를 설치할 필요가 없기 때문에, 설계의 자유도가 크고, 또한 그만큼 고밀도화를 도모할 수 있다. 또한, 필드비아도금에 비하여, 보다 종횡비가 큰 경우(예를 들면, 층간접속(31)을 위한 바닥을 갖는 비아(13)의 직경이 φ 0.2mm, 깊이 0.2mm ~ 0.55mm)라도, 접속패드(11)와 접속단자A(14)의 층간접속(31)을 형성할 수 있으므로, 캐비티층(5)의 두께를, 종래보다도 두껍게(예를 들면, 0.2mm ~ 0.55mm 정도) 할 수 있다. 그 결과, 캐비티부(9)를 높게 형성할 수 있어, 도 1에 나타낸 바와 같이, 복수의 반도체 패키지(36)를 겹쳐서 캐비티부(9) 안에 수납하는 것이 용이해 진다. 또한, 캐비티부(9)의 높이를, 봉지제(3)가 거의 돌출되지 않는 높이로 형성할 수 있기 때문에, 봉지제(3)를 몰딩하여 반도체 패키지(36)를 형성한 경우라도, 봉지제(3)의 표면이, 접속단자A(14)와 동등 이하, 즉 접속단자A(14)로부터 거의 돌출하지 않는 정도로 평탄하게 할 수 있다. 예를 들면, 도 6에 나타낸 바와 같이, 캐비티부(9) 안에 반도체소자(2)를 상하 2단으로 겹쳐 쌓아 탑재한 경우라도, 봉지제(3)의 표면이, 접속단자A(14)보다도 거의 돌출하지 않는 정도로 평탄하므로, 반도체 패키지 끼리의 접합을 위한 땜납볼 직경은, 봉지제(3)의 높이를 고려할 필요없이, 땜납볼로서, 직경이 φ0.3mm이하의 미소한 것을 이용해도 접합이 가능하게 된다. 그래서, φ0.3mm의 땜납볼을 이용한 경우라도, 하부 패키지(35)의 봉지제(3)의 최상부가, 접속단자A(14) 상의 땜납볼(φ0.3mm)의 1/3이하의 높이가 되는 상태에서, 상부 패키지(34)와 접합하는 것이 가능하다. 즉, 봉지제(3)의 최상부가, 접속단자A(14)보다도, 단자간 거리(44)의 1/3이하(0.1mm이하)의 높이만큼 돌출하도록 할 수 있다. 따라서, 본 발명의 반도체소자 탑재용 패키지 기판(1) 및 반도체 패키지(36)를, 하부 기판(33)과 하부 패키지(35)로서 사용하여 PoP를 구성하는 경우, 조합시키는 상대 반도체 패키지는 일반적인 것을 선택할 수 있어, 자유도가 크다. 또한, 접속을 위한 땜납볼의 직경은, 봉지제(3)의 돌출을 고려하여 크게 할 필요가 없기 때문에, 접속단자A(14)의 직경과 피치를 작게(예를 들면, 단자직경이 φ 0.25mm이하, 피치가 0.4mm이하) 하는 것이 가능하여, 고밀도인 접속이 가능하게 된다.As described above, in the semiconductor device mounting package substrate 1 and the semiconductor package 36 of the present invention, the interlayer connection 31 of the cavity layer 5 is formed by the conductive resin 17, so-called field vias. Unlike the case where the interlayer connection 31 is formed by plating, there is no need to provide a plating lead for power feeding, so that the degree of freedom in design and the density can be increased accordingly. In addition, even when the aspect ratio is larger than the field via plating (for example, the diameter of the via 13 having the bottom for the interlayer connection 31 is φ 0.2 mm, depth 0.2 mm to 0.55 mm), the connection pad Since the interlayer connection 31 of 11 and the connection terminal A 14 can be formed, the thickness of the cavity layer 5 can be made thicker (for example, about 0.2 mm to 0.55 mm) than before. As a result, the cavity part 9 can be formed high, and as shown in FIG. 1, it becomes easy to pile up the some semiconductor package 36 in the cavity part 9, and to receive it. In addition, since the height of the cavity part 9 can be formed so that the sealing agent 3 hardly protrudes, even when the sealing agent 3 is molded and the semiconductor package 36 is formed, the sealing agent The surface of (3) can be made flat so that it is equal to or less than the connection terminal A14, ie, hardly protrudes from the connection terminal A14. For example, as shown in FIG. 6, even when the semiconductor elements 2 are stacked and mounted in two stages up and down in the cavity portion 9, the surface of the encapsulant 3 is higher than that of the connection terminal A 14. Since the solder ball diameter for joining the semiconductor packages between the semiconductor packages is almost flat, the solder ball diameter does not have to consider the height of the encapsulant 3, and the solder ball diameter can be used as a solder ball having a diameter smaller than 0.3 mm. It becomes possible. Therefore, even when using a solder ball having a diameter of 0.3 mm, the top of the encapsulant 3 of the lower package 35 has a height equal to or smaller than 1/3 of the solder ball (φ 0.3 mm) on the connection terminal A 14. In this state, it is possible to bond with the upper package 34. That is, the uppermost part of the encapsulant 3 can protrude from the connection terminal A 14 by a height equal to or less than 1/3 (0.1 mm or less) of the distance 44 between terminals. Therefore, when the PoP is formed using the semiconductor device mounting package substrate 1 and the semiconductor package 36 as the lower substrate 33 and the lower package 35 of the present invention, the counterpart semiconductor package to be combined is a general one. We can choose, and degree of freedom is big. In addition, since the diameter of the solder ball for connection does not need to be made large in consideration of the protrusion of the encapsulant 3, the diameter and pitch of the connection terminal A 14 are reduced (for example, the terminal diameter is 0.25). mm or less, pitch is 0.4 mm or less), and high density connection is attained.

캐비티층(5)의 층간접속(31)은, 베이스층(6)의 캐비티층(5)측의 면에 설치된 접속패드(11)와, 이 접속패드(11)를 저면으로 하여 상기 캐비티층(5)에 형성된 바닥을 갖는 비아(13)와, 이 바닥을 갖는 비아(13) 안에 충전된 도전수지(17)와, 이 도전수지(17) 상에 설치된 접속단자A(14)에 의해 형성할 수 있다. 이렇게, 도전수지(17)를 충전하고, 그 위에 접속단자A(14)를 설치함으로써, 층간접속(31)의 바로 위에 접속단자A(14)를 형성할 수 있기 때문에, 접속단자A(14)를 고밀도로 배치할 수 있다. 이 캐비티층(5) 상의 접속단자A(14)는, 다른 반도체소자 탑재용 패키지 기판(1)과 반도체 패키지(36), 배선판(도시하지 않음)과의 접속에 사용하는 소위 외부접속단자로서 사용된다. 이 때문에, 도 6에 나타낸 바와 같이, 본 발명을 PoP 하부 기판(33)과 하부 패키지(35)로서 사용한 경우, 상부 기판(32)과 상부 패키지(34) 사이의 접속을 고밀도로 행하는 것이 가능하게 된다. 또한, 베이스층(6)의 캐비티층(5) 측의 면에 설치된 접속패드(11)는, 반도체소자(2)와의 접속을 행하는 와이어 본드 단자(12)와 접속단자C(27) 등의 소위 내부접속단자와, 베이스층(6)의 캐비티층(5) 측과는 반대측의 면에 설치된 접속단자B(15)에 접속된다. 접속단자B(15)는, 접속단자A(14)와 마찬가지로, 다른 반도체소자 탑재용 패키지 기판(1)과 반도체 패키지(36), 배선판(도시하지 않음)과의 접속에 사용하는 소위 외부접속단자로서 사용되고 있다.The interlayer connection 31 of the cavity layer 5 has a connection pad 11 provided on the side of the cavity layer 5 side of the base layer 6, and the connection pad 11 as a bottom surface thereof. A via 13 having a bottom formed in 5), a conductive resin 17 filled in the via 13 having a bottom, and a connection terminal A 14 provided on the conductive resin 17. Can be. In this way, by connecting the conductive resin 17 and providing the connection terminal A 14 thereon, the connection terminal A 14 can be formed directly on the interlayer connection 31, so that the connection terminal A 14 Can be arranged in a high density. The connection terminal A 14 on the cavity layer 5 is used as a so-called external connection terminal to be used for connection between another semiconductor element mounting package substrate 1, semiconductor package 36, and wiring board (not shown). do. For this reason, as shown in FIG. 6, when the present invention is used as the PoP lower substrate 33 and the lower package 35, the connection between the upper substrate 32 and the upper package 34 can be performed at a high density. do. Moreover, the connection pad 11 provided in the surface of the cavity layer 5 side of the base layer 6 is what is called the wire bond terminal 12 which connects with the semiconductor element 2, and the connection terminal C27, etc. The internal connection terminal is connected to the connection terminal B 15 provided on the side opposite to the cavity layer 5 side of the base layer 6. The connection terminal B 15, like the connection terminal A 14, is a so-called external connection terminal used for connection between the package substrate 1 for mounting another semiconductor element, the semiconductor package 36, and a wiring board (not shown). It is used as.

도 2에 나타낸 바와 같이, 캐비티층(5)의 층간접속(31)은, 캐비티층(5)의 바닥을 갖는 비아(13)의 내벽에 금속피복(18)을 형성하는 것이 바람직하다. 즉, 바닥을 갖는 비아(13) 안에 충전하는 도전수지(17)의 하지(下地)로서, 바닥을 갖는 비아(13)의 내벽에 금속피복(18)을 형성하는 것이 바람직하다. 바닥을 갖는 비아(13)의 내벽에 금속피복(18)을 형성하는 방법으로서는, 예를 들면, 전기구리도금이나 무전해구리도금에 의해 형성할 수 있다. 이것에 의해, 바닥을 갖는 비아(13)의 내벽이 매끄럽게 되어, 도전수지(17)가 바닥을 갖는 비어(13) 안으로 들어가기 쉽게 되기 때문에, 도전수지(17)가 충전되기 쉽게 된다. 또한, 도금에 의한 금속피복(18)과 도전수지(17)의 양자로 층간접속(31)을 형성하기 때문에, 층간접속의 신뢰성이 향상된다.As shown in FIG. 2, the interlayer connection 31 of the cavity layer 5 preferably forms a metal coating 18 on the inner wall of the via 13 having the bottom of the cavity layer 5. That is, it is preferable to form the metal coating 18 on the inner wall of the via 13 having a bottom as a base of the conductive resin 17 to fill in the via 13 having a bottom. As a method of forming the metal coating 18 on the inner wall of the via 13 which has a bottom, it can form by electrocopper plating or electroless copper plating, for example. As a result, the inner wall of the bottomed via 13 becomes smooth, and the conductive resin 17 easily enters the bottomed via 13, so that the conductive resin 17 is easily filled. In addition, since the interlayer connection 31 is formed by both the metal coating 18 and the conductive resin 17 by plating, the reliability of the interlayer connection is improved.

도 6에 나타낸 바와 같이, 베이스층(6)의 캐비티층(5)과 반대측의 면에 접속단자B(15)가 설치되고, 접속단자A(14)는 접속단자B(15)보다도 크기 및 피치가 작게 되도록 형성할 수 있다. 이것에 의해, 접속단자A(14)를, 다른 반도체소자 탑재용 패키지 기판(1)과 반도체 패키지(36)와 접속할 때, 고밀도의 접속이 가능하게 된다. 즉, PoP의 하부 기판(33)이나 하부 패키지(35)로서 사용하는 경우, 상부 기판(32)이나 상부 패키지(34)와의 고밀도 접속이 가능하게 된다.As shown in FIG. 6, the connection terminal B15 is provided in the surface on the opposite side to the cavity layer 5 of the base layer 6, and the connection terminal A14 is larger in size and pitch than the connection terminal B15. Can be formed to be small. As a result, when the connection terminal A 14 is connected to another semiconductor element mounting package substrate 1 and the semiconductor package 36, high-density connection is possible. That is, when used as the lower substrate 33 or the lower package 35 of the PoP, high density connection with the upper substrate 32 or the upper package 34 becomes possible.

봉지제(3)의 최상부는, 반도체소자 탑재용 패키지 기판(1)의 접속단자A(14)와 동등이하의 높이로 형성하는 것이 바람직하다. 여기서, 접속단자A(14)와 동등이하의 높이란, 접속단자A(14) 상에 설치되는 땜납볼(38)이 φ0.3mm의 경우(즉, 단자간 거리(44)가 0.3mm의 경우)를 상정(想定)하고 있고, 그 직경의 1/3이하의 높이까지를 말한다. 즉, 봉지제(3)의 최상부의 높이가, 접속단자A(14)에서 0.1mm의 높이까지인 것을 말한다. 이것에 의해, 본 발명의 반도체소자 탑재용 패키지 기판(1) 및 반도체 패키지(36)를, 하부 기판(33)이나 하부 패키지(35)로서 이용하여 PoP를 구성하는 경우, 접속단자A(14)의 면이 평탄하므로, 조합시키는 상부 기판(32)이나 상부 패키지(34)의 접속단자(37)면은, 평평한 일반적인 것을 선택할 수 있어, 자유도가 크다. 또한, 접속을 위한 땜납볼(38)의 직경은, 봉지제(3)의 튀어나옴을 고려하여 크게 할 필요가 없기 때문에, 고밀도인 접속이 가능하게 된다.The uppermost portion of the encapsulant 3 is preferably formed at a height equal to or less than the connection terminal A 14 of the package substrate 1 for mounting semiconductor elements. Here, the height equal to or less than the connection terminal A 14 means that the solder ball 38 provided on the connection terminal A 14 is φ 0.3 mm (that is, the distance 44 between the terminals is 0.3 mm). ) Is assumed, and the height is referred to as the height of 1/3 or less of the diameter. That is, it means that the height of the uppermost part of the sealing agent 3 is 0.1 mm in height from the connection terminal A14. As a result, when the PoP is formed by using the semiconductor device mounting package substrate 1 and the semiconductor package 36 as the lower substrate 33 or the lower package 35, the connection terminal A 14 Since the surface of the surface is flat, the surface of the connection terminal 37 of the upper substrate 32 or the upper package 34 to be combined can be selected from a flat general one, and the degree of freedom is large. In addition, since the diameter of the solder ball 38 for connection does not need to be made large in consideration of the protruding of the sealing agent 3, high density connection is attained.

캐비티부(9)는, 반도체소자 탑재용 패키지 기판(1)에 형성된 소정의 깊이의 패인곳이며, 반도체소자(2)를 탑재하기 위한 공간으로서 사용된다. 또한, 캐비티부(9)는, 개구(25)를 갖는 캐비티층(5)과 베이스층(6)에 의해 형성된다. 캐비티부(9)를 형성하는 방법으로서, 일예로서는, 도 3, 도 5에 나타낸 바와 같이, 접착제(8)를 붙인 캐비티층(5)에, 라우터(router)가공이나, 펀치가공 등으로 개구(25)를 형성한 후, 이 개구(25)를 베이스층(6)으로 막도록, 베이스층(6)을 적층하는 방법이 있다. 또한, 다른 예로서는, 캐비티층(5)과 베이스층(6)을 적층한 후에, 캐비티부(9)에 대응하는 부분의 캐비티층(5)을 제거하는 방법이 있다. 이 경우는, 캐비티층(5)으로서 감광성 재료를 사용할 수 있다.The cavity part 9 is a recess of the predetermined depth formed in the package element 1 for semiconductor element mounting, and is used as a space for mounting the semiconductor element 2. In addition, the cavity part 9 is formed of the cavity layer 5 and the base layer 6 which have the opening 25. As a method of forming the cavity portion 9, as an example, as shown in Figs. 3 and 5, the cavity layer 5 to which the adhesive agent 8 is attached is opened by router processing, punch processing, or the like. After forming 25, there is a method of laminating the base layer 6 so as to close the opening 25 with the base layer 6. As another example, after laminating the cavity layer 5 and the base layer 6, there is a method of removing the cavity layer 5 in the portion corresponding to the cavity portion 9. In this case, the photosensitive material can be used as the cavity layer 5.

캐비티층(5)은, 베이스층(6)과 적층되어 반도체소자(2)를 수납하는 캐비티부(9)를 형성하는 기판임과 아울러, 반도체소자(2)가 탑재되는 베이스층(6)의 접속패드(11)와, 다른 반도체소자 탑재용 패키지용 기판과 접속되는 접속단자A(14)와의 전기적 접속을 행하는 기판이다. 캐비티층(5)은, 절연층을 갖는 캐비티재(7)와, 그 표면에 형성되는 접속단자A(14) 및 내층회로(19)와, 캐비티재(7) 상에 설치되는 접착제(8)와, 캐비티부(9) 형성을 위한 개구(25)와, 층간접속(31)을 위한 관통공A(24)를 갖는다. 캐비티층(5)의 접착제(8)를 설치하는 측에 내층회로(19)를 설치함으로써, 베이스층(6)의 접속패드(11)와 금속피복(18)과의 접속개소에 가까운 위치에, 관통공A(24) 안의 금속피복(18)과의 내층접속(20)을 형성할 수 있고, 이 경우는, 열사이클시험에서의 수명이 개선되어, 신뢰성을 향상할 수 있다. 내층회로(19)는, 관통공A(24)의 주위를 완전히 둘러싸는 소위 환상링으로 하는 것이, 신뢰성이라는 점에서 더 바람직하다. 또한, 캐비티층(5)과 베이스층(6)을 접착제(8)을 끼워서 가열?가압하여 적층접착할 때에, 접착제(8)가 유동하여도, 관통공A(24)의 주위를 완전하게 둘러싼 댐(dam)으로서 작용하므로, 관통공A 안으로 유동한 접착제(8)가 들어가, 신뢰성이 저하하는 것을 억제할 수 있다. 또한, 예를 들면, 접착제(8)로서, 엘라스토머재를 사용하는 경우, 캐비티재(7)에 사용하는 글라스에폭시 등의 절연재에 비하여, 일반적으로 열팽창계수가 크다. 이 때문에, 바닥을 갖는 비아(13)의 내벽의 안에서 접착제(8)가 내벽으로 되는 부분에서는, 스루홀(through hole)도금인 금속피복(18)이, 바렐크랙(barrel crack)을 발생시키는 것이나, 바닥을 갖는 비아(13)의 저부에서는, 스루홀 도금 벗겨짐을 발생시키는 것이 염려된다. 그러나, 도 2의 확대도에서 알 수 있는 바와 같이, 내층회로(19)가 두께를 갖기 때문에, 내층회로(19)에 대응하는 부분의 접착제(8)는, 그 외의 부분에 비하여, 두께가 얇게 형성된다. 즉, 캐비티재(7) 상의 내층회로(19)와 베이스층(6)의 감광성수지(10) 사이에 끼워지는 부분의 접착제의 두께는, 이들에 끼워지지 않는 부분에 비하여 얇게 된다. 이렇게, 바닥을 갖는 비아(13)의 주위에는, 접착제(8)의 두께를 작게 할 수 있으므로, 접착제(8)의 열팽창계수가 큰 것에 의한 영향을 작게 할 수 있어, 신뢰성을 확보하는 것이 가능하게 된다. 이러한 작용을 생기게 하기 위해서는, 접착제의 두께가 10㎛ ~ 50㎛이고 내층회로의 두께가 9㎛ ~ 18㎛인 경우, 내층회로(19)에 대응하는 부분(내층회로(19)와 감광성수지층(10)에 끼워진 부분)의 접착제(8)의 두께는, 0.5㎛ ~ 7㎛인 것이 바람직하다. 따라서, 내층회로(19)가, 관통공A(24)의 주위를 완전히 둘러싸고 있는 소위 환상링으로 함으로써, 열팽창계수가 비교적 큰 엘라스토머재를 접착제(8)로서 사용하는 경우라도, 바닥을 갖는 비아(13)의 접착 신뢰성을 확보하는 것이 가능하게 된다. 내층회로(19)의 두께는, 9 ~ 18㎛인 것이 바람직하다. 이것에 의해, 도금으로 형성되는 금속피복(18)의 접속면적을 얻을 수 있으며, 또한, 관통공A(24)의 주위를 완전히 둘러싼 댐으로서의 효과도 크게 되므로, 접속 신뢰성이 향상된다. 도 3에 나타낸 바와 같이, 캐비티재(7)는, 반도체소자 탑재용 패키지 기판(1)의 제조에 사용되는 일반적인 동장적층판이나 빌드업재, 필름재를 이용할 수 있다. 또한, 이들의 동장적층판이나 빌드업재, 필름재를 조합시켜 다층화한 것도 사용할 수 있다. 캐비티재(7)의 두께는, 캐비티부(9)에 수납하는 반도체소자(2)를 겹쳐 쌓는 높이에 대응하여 선택된다. 접속단자A(14)와 내층회로(19)를 형성하는 패턴은, 서브트랙트법 등에 의해 제작할 수 있다. 개구(25)나 관통공A(24)은, 라우터 가공이나, 펀치가공 등으로 형성할 수 있다. The cavity layer 5 is a substrate which is stacked with the base layer 6 to form the cavity part 9 for accommodating the semiconductor element 2, and the base layer 6 on which the semiconductor element 2 is mounted. It is a board | substrate which makes electrical connection with the connection pad 11 and the connection terminal A14 connected with the other board | substrate for package mounting of semiconductor elements. The cavity layer 5 includes a cavity material 7 having an insulating layer, a connection terminal A 14 and an inner layer circuit 19 formed on the surface thereof, and an adhesive agent 8 provided on the cavity material 7. And an opening 25 for forming the cavity portion 9 and a through hole A 24 for the interlayer connection 31. By providing the inner layer circuit 19 on the side where the adhesive agent 8 of the cavity layer 5 is provided, the position close to the connection point between the connection pad 11 and the metal coating 18 of the base layer 6, The inner layer connection 20 with the metal coating 18 in the through hole A 24 can be formed. In this case, the lifetime in the thermal cycle test can be improved, and the reliability can be improved. The inner layer circuit 19 is more preferably a so-called annular ring that completely surrounds the periphery of the through hole A 24 in view of reliability. In addition, when the adhesive layer 8 is heated and pressurized by laminating the cavity layer 5 and the base layer 6 together with the adhesive 8, even if the adhesive 8 flows, the periphery of the through hole A 24 is completely enclosed. Since it acts as a dam, the adhesive agent 8 which flowed into the through hole A enters, and it can suppress that reliability falls. For example, when an elastomer material is used as the adhesive agent 8, the thermal expansion coefficient is generally large compared with the insulating material, such as glass epoxy used for the cavity material 7. As shown in FIG. For this reason, in the part where the adhesive agent 8 becomes an inner wall in the inner wall of the bottomed via 13, the metal coating 18 which is the through-hole plating generate | occur | produces a barrel crack, At the bottom of the via 13 having the bottom, it is concerned that through-hole plating peeling occurs. However, as can be seen from the enlarged view of FIG. 2, since the inner layer circuit 19 has a thickness, the adhesive 8 in the portion corresponding to the inner layer circuit 19 has a thinner thickness than the other portions. Is formed. In other words, the thickness of the adhesive at the portion sandwiched between the inner circuit 19 on the cavity material 7 and the photosensitive resin 10 of the base layer 6 is thinner than the portion not sandwiched therebetween. Thus, since the thickness of the adhesive agent 8 can be made small around the bottomed via 13, the influence by which the thermal expansion coefficient of the adhesive agent 8 is large can be made small, and it is possible to ensure reliability. do. In order to produce such an action, when the thickness of the adhesive is 10 μm to 50 μm and the thickness of the inner layer circuit is 9 μm to 18 μm, the portion corresponding to the inner layer circuit 19 (the inner layer circuit 19 and the photosensitive resin layer ( It is preferable that the thickness of the adhesive agent 8 of the part inserted in 10) is 0.5 micrometer-7 micrometers. Therefore, when the inner layer circuit 19 is a so-called annular ring that completely surrounds the periphery of the through hole A 24, the bottomed via (even when an elastomer material having a relatively large thermal expansion coefficient is used as the adhesive agent 8) It is possible to secure the adhesion reliability of 13). It is preferable that the thickness of the inner layer circuit 19 is 9-18 micrometers. Thereby, the connection area of the metal coating 18 formed by plating can be obtained, and also the effect as a dam which completely enclosed the periphery of the through-hole A24 becomes large, and connection reliability improves. As shown in FIG. 3, as the cavity material 7, a general copper clad laminate, a buildup material, and a film material used for manufacturing the semiconductor device mounting package substrate 1 can be used. Moreover, what laminated | multilayered by combining these copper clad laminated boards, a buildup material, and a film material can also be used. The thickness of the cavity material 7 is selected corresponding to the height of stacking the semiconductor elements 2 housed in the cavity part 9. The pattern for forming the connection terminal A 14 and the inner layer circuit 19 can be produced by a subtract method or the like. The opening 25 and the through hole A 24 can be formed by router processing, punch processing, or the like.

캐비티층(5)과 베이스층(6)의 적층에 사용되는 접착제(8)는, 반도체소자 탑재용 패키지 기판(1)의 제조에 사용되는 에폭시나 폴리이미드 계의 다층화 접착용의 접착제(8)를 이용할 수 있고, 프레스나 라미네이터 등에 의해 캐비티층(5)과 베이스층(6)에 임시부착할 수 있는 것이 바람직하다. 접착제(8)는, 캐비티층(5)과 베이스층(6)의 어느 쪽에 임시부착해도 좋고, 미리 임시부착하지 않고, 캐비티층(5)과 베이스층(6)을 적층하여 접착할 때에, 양자의 사이에 끼워 사용해도 좋다. 이러한 접착제(8)로서, 예를 들면, 강화섬유에 열경화성 수지를 함침(含浸)하고, 가열?건조하여, 반경화상으로 한 프리프레그(prepreg)나, 폴리에틸렌테레프탈레이트 필름상에 열경화성수지를 도포하고, 가열?건조하여 드라이 필름상으로 한 접착시트를 사용할 수 있다. 열경화수지로서는, 에폭시수지, 페놀수지, 폴리이미드수지, 비스말레이미드수지 등을 사용할 수 있고, 강화섬유로서는, 유리포, 유리 종이, 아미드포, 아미드 종이를 사용할 수 있다.The adhesive 8 used for laminating the cavity layer 5 and the base layer 6 is an adhesive 8 for multilayered adhesion of epoxy or polyimide used for the manufacture of the package substrate 1 for semiconductor element mounting. It is preferable that it can use, and can be temporarily attached to the cavity layer 5 and the base layer 6 by a press, a laminator, etc. The adhesive agent 8 may be temporarily attached to either of the cavity layer 5 and the base layer 6, and both of the adhesive layer 8 and the base layer 6 are laminated and bonded without temporarily adhering to each other. You may use between. As such an adhesive 8, for example, a reinforcing fiber is impregnated with a thermosetting resin, heated and dried, and a thermosetting resin is applied onto a prepreg or a polyethylene terephthalate film that has been semi-cured. The adhesive sheet which heated, dried, and made into the dry film can be used. As the thermosetting resin, epoxy resins, phenol resins, polyimide resins, bismaleimide resins, and the like can be used. As reinforcing fibers, glass cloth, glass paper, amide cloth, and amide paper can be used.

또한, 접착제(8)는, 엘라스토머재인 것이 바람직하다. 엘라스토머재로서 사용하는 접착제(8)로서는, 충분한 접착강도를 갖고, 또한 캐비티층(5)과 베이스층(6)의 치수변화의 거동의 차에 의해 발생하는 뒤틀림을 흡수할 수 있는 것이면 사용할 수 있다. 예를 들면, 에폭시수지 및 경화제 성분 100질량부에 대하여, 고무변성의 에폭시수지 20질량부 ~ 50질량부, 분자량이 1만 이상의 에폭시 골격의 고분자성분 10질량부 ~ 40질량부, 분자량 5만 이상의 고무성분 50질량부 ~ 150질량부, 경화촉진제 0.3질량부 ~ 2.5질량부로 이루어지는 접착제 조성물을, 기재필름에 도포하고, 반경화상태로 열처리하여 이루어지는 열경화성 접착시트를, 기재필름에서 벗겨내어, 진공 프레스 등으로 가열?가공하는 것으로 형성할 수 있다. 접착제(8)는, 캐비티층(5)이나 베이스층(6)에 라미네이터(laminator) 등으로 임시접착 가능한 것이, 작업성이라는 점에서 바람직하다. 가열?가압 후의 접착제(8)의 탄성율은, 50℃에서 100MPa ~ 500MPa의 것을 사용할 수 있고, 특히, 500MPa 정도가 바람직하다. 또한, 탄성율은, 가부시키가이샤 유비엠제, Rheogel E-4000형 점탄성 측정장치를 사용하여, DVE법에 의해, 인장모드, 주파수 10Hz, 승온속도 5℃/분인 조건에서 측정했다. 수지 플로우량(가열?가압 후의 단부(端部)에서의 수지흐름 양)은, 50㎛ ~ 1500㎛의 것을 사용할 수 있고, 성형성과 바닥을 갖는 비아 안으로의 배어 나오는 양의 밸런스 때문에 100㎛ ~ 500㎛가 바람직하고, 특히 300㎛정도의 것이 바람직하다. 또한, 수지플로우량은, 가열?가압 전의 시트상태의 접착제(8)를 직경 10mm의 원형으로 타발(打拔)한 것을 샘플로 하여, 이것을 PET(폴리에틸렌테레프탈레이트)필름에 끼워넣고, 프레스(100℃, 3MPa, 5분)를 행한 후, 샘플의 직경을 3개소 측정하여 평균하여, 프레스 전의 치수와의 차를 계산에 의해 구함으로써 측정했다. 고무변성의 에폭시수지로서는, CTBN(카르복시기 말단 부타디엔니트릴고무)변성품이고, 또한 변성률이 30% ~ 60%인 것을 들 수 있다. 고무성분으로서는, 분자량 5만 이상의 에폭시기 함유 아크릴니트릴 부타디엔고무를 들 수 있다. 반경화상태는, 기재필름에 도포한 후의 열처리에 의해, 10% ~ 60%의 경화율로 함으로써 얻을 수 있다. 이러한 엘라스토머로서의 작용을 갖는 접착제(8)를 사용함으로써, 엘라스토머재로서의 접착제(8)가, 캐비티층(5)과 베이스층(6)의 치수변화의 거동의 차에 의해 발생하는 뒤틀림을 흡수하므로, 반도체소자 탑재용 패키지 기판(1)의 휨을 억제할 수 있다. 특히, 캐비티층(5)과 베이스층(6)에 사용되는 재료와 층 구성이 다르거나, 캐비티부(9)용의 개구(25)를 갖기 때문에 개구율이 다른 경우는, 제조시와 사용시의 캐비티층(5)과 베이스층(6)의 치수변화의 거동이 다르기 때문에, 적층에 사용하는 접착제(8)로서 엘라스토머재를 사용하는 것이 유효하다. 이러한 접착제(8)로서는, 예를 들면, AS2600, AS3000, GF3500, GF3600(모두 히다치가세이고쿄가부시키가이샤제 제품명)을 들 수 있다. 접착제(8)의 두께로서는, 10㎛ ~ 50㎛를 사용할 수 있고, 20㎛ ~ 50㎛가 바람직하며, 특히, 25㎛ ~ 40㎛가 바람직하다. 이보다 얇은 경우는, 캐비티층(5)의 내층회로(19)의 두께에 의한 단차 등을 메울 수 없고, 또한 캐비티층(5)과 베이스층(6)의 치수변화의 거동의 차이 등에 의한 뒤틀림을 흡수하기 어렵게 된다. 이보다 두꺼운 경우는, 엘라스토머재인 접착제(8)의 움직임이 크게 되어, 접착 신뢰성이 저하할 가능성이 있다.Moreover, it is preferable that the adhesive agent 8 is an elastomer material. The adhesive 8 used as the elastomer material can be used as long as it has sufficient adhesive strength and can absorb the distortion caused by the difference in the behavior of the dimensional change between the cavity layer 5 and the base layer 6. . For example, 20 mass parts-50 mass parts of rubber-modified epoxy resins, 10 mass parts-40 mass parts of polymer components of an epoxy skeleton with a molecular weight of 10,000 or more, and molecular weight 50,000 or more with respect to 100 mass parts of epoxy resins and a hardening | curing agent component 50 mass parts-150 mass parts of rubber components, 0.3 mass part-2.5 mass parts of hardening accelerators are apply | coated to a base film, and the thermosetting adhesive sheet formed by heat-processing in a semi-hardened state is peeled off from a base film, and a vacuum press is carried out. It can form by heating and a process with etc. It is preferable that the adhesive agent 8 can be temporarily bonded to the cavity layer 5 or the base layer 6 by using a laminator or the like in terms of workability. As the elasticity modulus of the adhesive agent 8 after a heating and pressurization, the thing of 100 MPa-500 MPa can be used at 50 degreeC, About 500 MPa is especially preferable. In addition, the elasticity modulus was measured on the conditions which were tensile mode, the frequency of 10 Hz, and the temperature increase rate of 5 degree-C / min by DVE method using the Uhe M make, Rheogel E-4000 type viscoelasticity measuring apparatus. The resin flow amount (the amount of resin flow at the end after heating and pressurization) can be 50 μm to 1500 μm, and is 100 μm to 500 due to the balance of the amount of bleed into the via having the bottom and the moldability. The micrometer is preferable, and the thing of about 300 micrometers is especially preferable. The resin flow amount was a sample obtained by punching out the sheet-like adhesive 8 before heating and pressing into a circular shape having a diameter of 10 mm, and sandwiching it in a PET (polyethylene terephthalate) film to press the press (100). After performing (degree. C., 3 MPa, 5 minutes), the diameter of the sample was measured and averaged 3 places, and it measured by calculating | requiring the difference with the dimension before a press by calculation. Examples of the rubber-modified epoxy resin include CTBN (carboxyl terminal butadiene nitrile rubber) modified products, and modification rates of 30% to 60%. As a rubber component, the epoxy group containing acrylonitrile butadiene rubber of molecular weight 50,000 or more is mentioned. A semi-hardened state can be obtained by making it the hardening rate of 10%-60% by the heat processing after apply | coating to a base film. By using the adhesive 8 having such an elastomer, the adhesive 8 as the elastomer material absorbs the distortion caused by the difference in the behavior of the dimensional change between the cavity layer 5 and the base layer 6, The curvature of the package substrate 1 for semiconductor element mounting can be suppressed. In particular, when the opening ratio is different from the material used in the cavity layer 5 and the base layer 6, or because the opening 25 for the cavity part 9 is different, the cavity at the time of manufacture and use is different. Since the behavior of the dimensional change of the layer 5 and the base layer 6 is different, it is effective to use an elastomeric material as the adhesive agent 8 used for lamination. As such an adhesive agent 8, AS2600, AS3000, GF3500, GF3600 (all are the Hitachi Chemical Co., Ltd. product names) are mentioned, for example. As thickness of the adhesive agent 8, 10 micrometers-50 micrometers can be used, 20 micrometers-50 micrometers are preferable, and 25 micrometers-40 micrometers are especially preferable. In the case of thinner than this, the step due to the thickness of the inner circuit 19 of the cavity layer 5 cannot be filled, and the distortion caused by the difference in the behavior of the dimensional change between the cavity layer 5 and the base layer 6 is prevented. It becomes difficult to absorb. When thicker than this, the movement of the adhesive agent 8 which is an elastomer material becomes large, and there exists a possibility that adhesive reliability may fall.

베이스층(6)은, 캐비티층(5)과 적층되어 캐비티부(9)를 형성함과 아울러, 반도체소자(2)를 탑재하기 위한 기판이다. 베이스층(6)은, 절연층인 베이스재(21)의 캐비티층(5) 측의 면에, 반도체와 전기적으로 접속되는 와이어 본드단자(12)와, 이 와이어 본드단자(12)와 인출선(도시하지 않음)에 의해 전기적으로 접속하는 접속패드(11)를 갖고, 베이스재(21)의 캐비티층(5)과 반대측의 면에, 다른 기판 등과 접속하기 위한 접속단자B(15)를 갖고, 이들의 접속패드(11)와 접속단자B(15)를 전기적으로 접속하는 층간접속(42)을 갖는다. 와이어 본드단자(12), 인출선(도시하지 않음), 접속패드(11) 및 접속단자B(15)를 형성하는 패턴은 서브트랙트법 등에 의해 제작할 수 있다. 베이스재(21)는, 반도체소자 탑재용 패키지 기판(1)의 제조에 사용되는 일반적인 동장적층판이나 빌드업재를 사용하여 제작할 수 있다. 또한, 도 4에 나타낸 바와 같이, 이들의 동장적층판을 베이스재a(28)로 하고, 빌드업재를 베이스재b(29) 및 베이스재c(30)로 하여, 이들을 조합시켜 다층화한 베이스재(21)도 사용할 수 있다. 층간접속(42)은, 드릴가공이나 레이저 가공을 이용하여 관통공과 비(非)관통공을 형성하여, 이들의 구멍 안에 도금을 형성하는 등에 의해 제작할 수 있다. 또한, 상기는, 반도체소자(2)와 접속패드(11)의 전기적 접속이, 와이어 본드단자(12)만으로 행해지는 경우에 대해서 서술했지만, 도 6에 나타낸 바와 같이, 와이어 본드단자(12)에 더해 접속단자C(27)에 의해 전기적으로 접속되는 경우도 마찬가지로 하여, 베이스층(6)을 형성할 수 있다.The base layer 6 is a substrate for stacking the cavity layer 5 to form the cavity 9 and mounting the semiconductor element 2 thereon. The base layer 6 is a wire bond terminal 12 electrically connected to a semiconductor on the surface of the cavity layer 5 side of the base material 21, which is an insulating layer, the wire bond terminal 12, and a lead wire. It has the connection pad 11 electrically connected by not shown, and has the connection terminal B15 for connecting to another board | substrate etc. in the surface on the opposite side to the cavity layer 5 of the base material 21. And an interlayer connection 42 for electrically connecting these connection pads 11 and the connection terminals B15. The pattern which forms the wire bond terminal 12, the lead wire (not shown), the connection pad 11, and the connection terminal B 15 can be manufactured by the subtract method. The base material 21 can be manufactured using the general copper clad laminated board and buildup material used for manufacture of the package substrate 1 for semiconductor element mounting. In addition, as shown in FIG. 4, the copper clad laminated board is made into the base material a28, the buildup material is made into the base material b29 and the base material c30, and these are combined and multilayered. 21) can also be used. The interlayer connection 42 can be produced by forming through-holes and non-through-holes by using drilling or laser processing to form plating in these holes. In addition, although the above has demonstrated the case where the electrical connection of the semiconductor element 2 and the connection pad 11 is performed only by the wire bond terminal 12, as shown in FIG. 6, it connected to the wire bond terminal 12. As shown in FIG. In addition, the base layer 6 can be formed similarly also in the case where it is electrically connected by the connection terminal C27.

접속패드(11)는, 베이스층(6)의 캐비티층(5)측의 면의 캐비티부(9)에 대응하는 영역 이외의 영역에 설치되고, 이 접속패드(11)를 저면으로 한 바닥을 갖는 비아(13)가 캐비티층(5)에 형성된다. 이 바닥을 갖는 비아(13)의 형성은, 일예로서는, 도 3에 나타낸 바와 같이, 캐비티재(7)에 드릴가공, 레이저가공, 펀치가공, 라우터가공 등으로 관통공A(24)를 형성해 두고, 접착제(8)를 임시부착하여, 관통공A(24)에 대응하는 부분의 접착제(8)를 드릴가공, 레이저가공, 펀치가공, 라우터가공 등으로 제거한 후, 도 5에 나타낸 바와 같이, 이 관통공A(24)의 위치와, 접속패드(11)의 위치가 대응하도록, 캐비티층(5)과 베이스층(6)을 적층함으로써 이루어 질 수 있다. 다른 예로서는, 캐비티재(7)와 접착제(8)의 양자에 드릴가공, 레이저가공, 펀치가공, 라우터가공 등으로 관통공A(24)를 형성해 두고, 캐비티재(7)와 접착제(8)의 관통공A(24)의 위치를 합쳐서 캐비티재(7)에 접착제(8)를 임시부착하고, 이 관통공A(24)의 위치와, 접속패드(11)의 위치가 대응하도록, 캐비티층(5)과 베이스층(6)을 적층함으로써 이루어질 수 있다. 또한, 다른 예로서는, 캐비티층(5)과 베이스층(6)을 적층한 후에, 접속패드(11)에 대응하는 부분의 캐비티층(5)을 제거하는 방법이 있다. 이 경우는, 제거를 오목(凹)가공이나 레이저가공으로 행하는 방법, 혹은 캐비티층(5)으로서 감광성의 재료를 사용하는 방법을 이용할 수 있다.The connection pad 11 is provided in an area | region other than the area | region corresponding to the cavity part 9 of the surface by the side of the cavity layer 5 of the base layer 6, and has the bottom which made this connection pad 11 the bottom surface. Vias 13 having are formed in the cavity layer 5. For example, as shown in FIG. 3, through-hole A 24 is formed in cavity material 7 by drilling, laser processing, punching, router processing, and the like. After adhering the adhesive 8 temporarily, the adhesive 8 of the portion corresponding to the through hole A 24 is removed by drilling, laser processing, punching, router processing, or the like, as shown in FIG. It can be achieved by laminating the cavity layer 5 and the base layer 6 so that the position of the through hole A 24 and the position of the connection pad 11 correspond. As another example, the through hole A 24 is formed in both the cavity material 7 and the adhesive 8 by drilling, laser processing, punching, router processing, and the like. The adhesive layer 8 is temporarily attached to the cavity material 7 by joining the positions of the through holes A 24, and the cavity layer (so that the position of the through holes A 24 and the position of the connection pad 11 correspond to each other). 5) and the base layer 6 by laminating. As another example, after laminating the cavity layer 5 and the base layer 6, there is a method of removing the cavity layer 5 in the portion corresponding to the connection pad 11. In this case, the method of performing removal by concave processing or laser processing, or using the photosensitive material as the cavity layer 5 can be used.

도 2에 나타낸 바와 같이, 베이스층(6)의 캐비티층(5)과 적층되는 측에, 감광성 수지층(10)이 형성되는 것이 바람직하다. 그리고, 바닥을 갖는 비아(13)에 의한 층간접속(31)을 형성할 목적으로, 접속패드(11)는 적어도 일부가 노출한 상태로 되어, 캐비티층(5)과 베이스층(6)을 적층할 때는, 캐비티층(5)의 접착제(8)와 베이스층(6)의 감광성수지층(10)이 접착하도록 하는 것이 바람직하다. 이것에 의해, 접착제(8)가 베이스층(6)의 접속패드(11)에 직접 접착하지 않도록 할 수 있어, 적층시에 접착제(8)가 접착패드(11) 상으로 퍼져, 접속면적을 축소시켜, 접속저항이 크게 되거나, 접속신뢰성이 저하하는 것을 억제할 수 있다. 즉, 감광성수지층(10)이, 접속패드(11)와 접착제(8) 사이에 배치됨으로써, 적층시에 접착제(8)가 접착패드(11) 상에 유동하는 것을 방해하는 작용을 갖는다. 또한, 베이스층(6)의 캐비티층(5)과의 접착면에 있는 접착패드(11) 등에 의한 단차를 평탄하게 할 수 있고, 캐비티층(5)과의 접착에 사용되는 접착제(8)가 얇아서, 유동성이 낮은 것을 사용해도, 접착제(8)의 추종을 확보할 수 있다.As shown in FIG. 2, it is preferable that the photosensitive resin layer 10 is formed in the side laminated | stacked with the cavity layer 5 of the base layer 6. As shown in FIG. And for the purpose of forming the interlayer connection 31 by the bottomed via 13, the connection pad 11 is in the state which at least one part exposed, and laminated | stacked the cavity layer 5 and the base layer 6 In this case, it is preferable that the adhesive 8 of the cavity layer 5 and the photosensitive resin layer 10 of the base layer 6 adhere to each other. Thereby, the adhesive agent 8 can be prevented from adhering directly to the connection pad 11 of the base layer 6, and the adhesive agent 8 spreads on the adhesive pad 11 at the time of lamination, and reduces a connection area. It is possible to suppress that the connection resistance increases or the connection reliability decreases. That is, since the photosensitive resin layer 10 is arrange | positioned between the connection pad 11 and the adhesive agent 8, it has an effect which prevents the adhesive agent 8 from flowing on the adhesive pad 11 at the time of lamination | stacking. Moreover, the level | step difference by the adhesive pad 11 etc. in the adhesion surface with the cavity layer 5 of the base layer 6 can be flattened, and the adhesive agent 8 used for adhesion | attachment with the cavity layer 5 is Even if it is thin and the fluidity | liquidity thing is used, the following of the adhesive agent 8 can be ensured.

감광성수지층(10)으로서는, 배선판이나 실장기판의 제조에 사용되는 감광성의 솔더레지스트(solder resist)를 사용할 수 있다. 감광성의 솔더레지스트로서는, 반도체소자 탑재용 패키지 기판이나, 배선판에서 일반적으로 사용되는 것을 이용할 수 있다. 이러한 것으로서는, 액상 타입의 PSR4000(다이요잉키가부시키가이샤제 상품명)나, 드라이필름 타입의 포텍SR3000G(히타치가세이가부시키가이샤제, 상품명)를 사용할 수 있다. As the photosensitive resin layer 10, a photosensitive solder resist used for manufacturing a wiring board or a mounting board can be used. As a photosensitive soldering resist, what is generally used by the package board | substrate for semiconductor element mounting, or a wiring board can be used. As such a liquid, PSR4000 (trade name manufactured by Daiyo Inky Industries Co., Ltd.) and Potec SR3000G (trade name, manufactured by Hitachi Chemical Co., Ltd.) of the dry film type can be used.

도 5에 나타낸 바와 같이, 바닥을 갖는 비아(13) 안에는 도전수지(17)가 충전된다. 도전수지(17)의 바닥을 갖는 비아(13)로의 충전은, 도전수지(17)를 인쇄로 도포함으로써 행할 수 있다. 바닥을 갖는 비아(13)의 종횡비가 큰 경우에는, 예를 들면, 진공인쇄장치를 이용함으로써, 바닥을 갖는 비아(13) 안으로의 기포의 잔류를 억제할 수 있어, 충전성을 확보할 수 있다. 또한, 도전수지(17)를 충전하기 전에, 바닥을 갖는 비어(13) 안에, 금속피복(18)을 형성하는 것이 바람직하다. 금속피복(18)은, 예를 들면, 전기구리도금이나 무전해구리도금에 의해 형성할 수 있다. 이것에 의해, 바닥을 갖는 비아(13)의 내벽이 매끄럽게되어, 도전수지(17)가 바닥을 갖는 비아(13) 안으로 들어가기 쉽게 되기 때문에, 도전수지(17)가 충전하기 쉽게된다. 또한, 도금에 의한 금속피복(18)과 도전수지(17)의 양자로 층간접속(31)을 형성하기 때문에, 층간접속 신뢰성이 향상된다.As shown in FIG. 5, the conductive resin 17 is filled in the via 13 having a bottom. Filling the via 13 having the bottom of the conductive resin 17 can be performed by applying the conductive resin 17 by printing. When the aspect ratio of the bottomed vias 13 is large, for example, by using a vacuum printing apparatus, the remaining of bubbles in the bottomed vias 13 can be suppressed, and filling can be ensured. . In addition, it is preferable to form the metal coating 18 in the bottomed via 13 before filling the conductive resin 17. The metal coating 18 can be formed by, for example, electric copper plating or electroless copper plating. As a result, the inner wall of the bottomed via 13 is smoothed, and the conductive resin 17 easily enters the bottomed via 13, so that the conductive resin 17 is easy to fill. In addition, since the interlayer connection 31 is formed by both the metal coating 18 and the conductive resin 17 by plating, the interlayer connection reliability is improved.

이와 같이, 접속패드(11)와 접속단자A(14)의 층간접속(31)이, 바닥을 갖는 비아(13) 안으로 도전수지(17)를 충전함으로써 형성되므로, 소위 필드비아도금에 의한 도금의 충전과 비교하여, 급전을 위한 도금리드를 설치할 필요가 없으므로, 설계의 자유도가 크고, 또한, 그만큼, 고밀도화를 도모할 수 있다. 또한, 필드비아 도금에 비하여, 보다 종횡비가 큰 경우(예를 들면, 층간접속(31)을 위한 바닥을 갖는 비아(13)의 직경이 φ0.2mm, 깊이 0.2mm ~ 0.5mm)라도, 접속패드(11)와 접속단자A(14)의 층간접속(31)을 형성할 수 있다. 이 때문에, 캐비티부(9) 안에 복수의 반도체소자(2)를 겹쳐 수납하는 것이 가능하게 된다. 또한, 이 때문에, 복수의 반도체소자(2)를 겹쳐 수납한 경우라도, 봉지제(3)의 최상부가, 접속단자A(14)와 동등이하의 높이가 되도록 하는 것이 가능하다. 따라서, 본 발명의 반도체소자 탑재용 패키지 기판(1)이 PoP에서 하부 기판(33)으로서 사용되는 경우, 또는 본 발명의 반도체 패키지(36)가 PoP에서 하부 패키지(35)로서 사용되는 경우는, 접속단자A(14)보다도 위쪽으로 봉지제(3)가 튀어나오는 경우가 없으므로, 상부 기판(32) 또는 상부 패키지(34)와의 접속 시에, 봉지제(3)의 높이를 고려한 땜납볼 직경을 이용할 필요성이 없고, 땜납볼 직경의 소경화(小徑化)가 가능하게 된다. 또한, 이것에 따라, 접속단자A(14)의 직경(크기)이나 피치의 미세화가 가능하게 된다.In this way, the interlayer connection 31 of the connection pad 11 and the connection terminal A 14 is formed by filling the conductive resin 17 into the via 13 having a bottom, so that the plating of the connection pad 11 by the field via plating is performed. In comparison with the charging, there is no need to provide a plating lead for power feeding, so the degree of freedom in design is large, and the density can be increased accordingly. In addition, even when the aspect ratio is larger than the field via plating (for example, the diameter of the via 13 having the bottom for the interlayer connection 31 is φ 0.2 mm and the depth is 0.2 mm to 0.5 mm), the connection pad may be used. The interlayer connection 31 between the connection member A and the connection terminal A 14 can be formed. For this reason, it becomes possible to store the some semiconductor element 2 in the cavity part 9 overlappingly. For this reason, even when the some semiconductor element 2 is piled up and stored, it is possible to make the uppermost part of the sealing agent 3 become a height equal to or less than the connection terminal A14. Therefore, when the semiconductor device mounting package substrate 1 of the present invention is used as the lower substrate 33 in the PoP, or when the semiconductor package 36 of the present invention is used as the lower package 35 in the PoP, Since the encapsulant 3 does not protrude upward from the connection terminal A 14, the diameter of the solder ball considering the height of the encapsulant 3 in connection with the upper substrate 32 or the upper package 34 is determined. There is no necessity to use it, and small diameter of a solder ball diameter is attained. In this way, the diameter (size) and the pitch of the connection terminal A 14 can be reduced.

도 7에 나타낸 바와 같이, 일반적으로, PoP용의 하부 기판(33)이나 하부 패키지(35)에서는, 상부 기판(32) 또는 상부 패키지(34)와 접속되는 접속단자A(14) 쪽이 땜납볼(38)의 직경이 크기(예를 들면, φ0.6mm)때문에, 반대측의 면의 접속단자B(15)보다도, 단자의 직경(크기)이 크고(예를 들면,φ0.5mm), 피치도 크게(예를 들면, 0.8mm) 형성되어 있다. 그러나, 도 6에 나타낸 바와 같이, 본 발명에서는, 상부 기판(32) 또는 상부 패키지(34)와 접속되는 접속단자A(14) 쪽이, 반대측의 면의 접속단자B(15)보다도, 단자의 직경(크기)이 작고(예를 들면, φ 0.25mm), 피치도 작게(예를 들면, φ0.4mm) 형성하는 것이 가능하게 된다. 이 때문에, 보다 단자 수가 많은 상부 기판(32) 또는 상부 패키지(34)의 고밀도인 접속이 가능하게 된다.As shown in FIG. 7, generally, in the lower substrate 33 or the lower package 35 for PoP, the connection terminal A 14 connected to the upper substrate 32 or the upper package 34 is the solder ball. Since the diameter of (38) is large (for example, φ 0.6 mm), the diameter (size) of the terminal is larger (for example, φ 0.5 mm) than the connection terminal B 15 on the opposite side, and the pitch It is formed large (for example, 0.8 mm). However, as shown in FIG. 6, in the present invention, the connection terminal A 14 connected to the upper substrate 32 or the upper package 34 has a lower end than that of the connection terminal B 15 on the opposite side. It becomes possible to form small diameter (size) (for example, (phi) 0.25 mm), and small pitch (for example, (phi) 0.4mm). For this reason, the high density connection of the upper board 32 or the upper package 34 with many more terminal numbers is attained.

또한, 종래의 스루홀 도금에 의한 층간접속(31)의 형성에서는, 바닥을 갖는 비아(13)의 바로 위에 접속단자를 설치할 수 없었지만, 본 발명에 의하면, 바닥을 갖는 비아(13) 위에 금속피복(18)을 실시하는 것도 가능하므로, 바닥을 갖는 비아(13)의 바로 위에 외부접속단자(접속단자A(14))를 설치할 수 있어, 고밀도화를 도모할 수 있다.In addition, in the conventional formation of the interlayer connection 31 by through-hole plating, the connection terminal cannot be provided directly on the via 13 having a bottom, but according to the present invention, the metal coating on the via 13 having a bottom is performed. Since 18 can be implemented, an external connection terminal (connection terminal A 14) can be provided directly above the via 13 having a bottom, and the density can be increased.

도전수지(17)는, 도전성분으로서 은, 구리, 카본 등을, 바인더로서 에폭시수지, 페놀수지 등의 열경화성 수지를 포함하는 것을 이용할 수 있다. 또한, 충전 후의 도전수지(17)를 경화시킨다. 도전수지(17)가 충분히 경화되지 않으면, 후의 가공에서 도전수지(17)의 가교밀도가 증가하여, 체적수축에 의한 보이드나 크랙, 계면파괴가 발생하여, 접속신뢰성이 저하된다. 도전수지(17)의 바인더는 재경화하지 않은 것이 바람직하다.The conductive resin 17 may include silver, copper, carbon, or the like as the conductive powder, and thermosetting resin such as epoxy resin or phenol resin as the binder. In addition, the conductive resin 17 after curing is cured. If the conductive resin 17 is not sufficiently cured, the crosslinking density of the conductive resin 17 increases in subsequent processing, voids, cracks, and interface breakage due to volume shrinkage occur, resulting in a decrease in connection reliability. It is preferable that the binder of the conductive resin 17 is not recured.

바닥을 갖는 비아(13) 안으로 도전수지(17)가 충전되어, 경화됨으로써, 바닥을 갖는 비아(13) 전체의 강성이 향상된다. 상술한 것처럼, 접착제(8)로서 엘라스토머재를 사용한 경우, 캐비티층(5)과 베이스층(6)의 치수변화의 거동이 다른 경우라도, 접착제(8)가 그 뒤틀림을 흡수하여, 휨이나 비틀림 등의 발생을 억제한다. 한편으로, 이 뒤틀림을 흡수할 때에, 접착제(8)에 뒤틀림 응력이 집중하여 변형한다. 이 때문에, 예를 들면, 일반적인 스루홀 도금만으로 바닥을 갖는 비아(13)의 층간접속을 형성한 경우, 접착제(8) 부분에서 크랙이 발생하여, 접속불량이 발생하는 것이 고려될 수 있다. 그러나, 바닥을 갖는 비아(13) 안에는, 도전수지(17)가 충전되어, 경화되어 있으므로, 바닥을 갖는 비아(13) 전체의 강성이 향상되어 있기 때문에, 도전수지(17)에 의해 층간접속(31)이 형성된 개소는, 접착제(8)의 변형이 억제된다. 도전수지(17)를 충전하기 전에, 바닥을 갖는 비아(13) 안에, 도금에 의해 금속피복(18)을 형성하는 것이, 도전수지(17)의 충전성이나 층간접속 신뢰성이라는 관점에서 보다 바람직하다. 층간접속(31)이 형성되어 있지 않고, 도전수지(17)가 없는 부분에서는, 접착제(18)가 변형하여 뒤틀림을 흡수한다. 이렇게 해서, 접착체(8)로서 엘라스토머재를 사용한 경우라도, 바닥을 갖는 비아(13) 안에 도전수지(17)가 충전되어, 경화됨으로써, 접착 신뢰성을 확보하면서, 휨이나 변형을 억제할 수 있는 반도체소자 탑재용 패키지 기판을 제공할 수 있다.The conductive resin 17 is filled into the bottom via 13 and cured, thereby improving the rigidity of the entire bottom via 13. As described above, when an elastomeric material is used as the adhesive 8, even if the behavior of the dimensional change of the cavity layer 5 and the base layer 6 is different, the adhesive 8 absorbs the distortion and warns or twists. Suppress the occurrence of On the other hand, when absorbing this distortion, distortion stress concentrates on the adhesive agent 8, and deforms. For this reason, for example, when the interlayer connection of the via 13 having a bottom is formed only by general through-hole plating, cracks may occur in the adhesive 8 part, and connection failure may be considered. However, since the conductive resin 17 is filled and hardened in the bottomed vias 13, the rigidity of the entire vias 13 having bottoms is improved, so that the interlayer connection ( The deformation | transformation of the adhesive agent 8 is suppressed in the location in which 31) was formed. Prior to filling the conductive resin 17, it is more preferable to form the metal coating 18 in the via 13 having a bottom by plating from the viewpoint of the filling property of the conductive resin 17 and the reliability of the interlayer connection. . In the portion where the interlayer connection 31 is not formed and the conductive resin 17 is not present, the adhesive 18 deforms and absorbs the distortion. In this way, even when an elastomeric material is used as the adhesive 8, the conductive resin 17 is filled and cured in the via 13 having a bottom, whereby curvature and deformation can be suppressed while ensuring adhesion reliability. A package substrate for mounting a semiconductor device can be provided.

도전성분은, 평균입경 30㎛이하의 구리분말(銅粉) 또는 구리분말의 표면에 은도금한 것(이하, 「은도금 구리분말」이라 한다.) 또는 구리분말의 표면에 금도금한 것(이하, 「금도금 구리분말」이라 한다.)을 포함하는 금속분말을 사용하는 것이 바람직하다. 이들 중에서도, 무전해 니켈 도금이나 무전해 금도금의 석출성이 우수한 점에서, 주된 도전성분이, 은도금 구리분말나 금도금 구리분말인 것이 바람직하다. 금속분말의 평균입경이 30㎛을 넘으면, 인쇄시에 스크린이 막히거나, 페이스트의 연신이 나쁘게 되어, 인쇄성이 뒤떨어진다. 금속분말의 형상은, 플레이크상 또는 수지(樹枝) 상이면, 금속분말끼리의 접촉이 좋게되어, 도전성이 향상되므로 바람직하다. 또한, 다른 형상의 금속분말을 스탬핑 등의 처리를 하여 플레이크상으로 하여 사용해도 좋다. 은도금 구리분말에서의 은도금이나 금도금 구리분말에서의 금도금은, 전해도금법, 무전해도금법, 치환도금법 등의 어떠한 방법으로 도금한 것이라도 좋고 특별히 제한되지 않는다. 도전수지(17) 중의 도전성분의 함유량으로서는, 65질량% ~ 80질량%가 바람직하고, 특히 76질량% 정도가 바람직하다. 이보다 적은 경우는, 무전해 도금의 석출성이 저하하여, 도전수지(17) 상이 금속피막(16)에 의해 피복되지 않는 경우가 있고, 이보다도 많은 경우는, 도전수지(17)의 페이스트상태에서의 점도가 높게 되어, 인쇄성이 저하하여, 바닥을 갖는 비아(13)로의 충전이 곤란하게 된다.The electroconductive powder was silver-plated on the surface of copper powder or copper powder with an average particle diameter of 30 micrometers or less (henceforth "silver plating copper powder."), Or gold-plated on the surface of copper powder (hereinafter, " It is preferable to use a metal powder containing a " gold plated copper powder ". Among these, it is preferable that the main electroconductive powder is silver plating copper powder or gold plating copper powder from the point which is excellent in the precipitation property of electroless nickel plating and electroless gold plating. If the average particle diameter of the metal powder exceeds 30 µm, the screen may be clogged during printing, or the stretching of the paste may be poor, resulting in poor printability. If the shape of a metal powder is a flake shape or a resin phase, since the contact of metal powder becomes good and electroconductivity improves, it is preferable. Alternatively, metal powders of different shapes may be used as a flake by processing such as stamping. Silver plating in silver plating copper powder and gold plating in gold plating copper powder may be plated by any method, such as an electroplating method, an electroless plating method, a substitution plating method, and is not specifically limited. As content of the electrically conductive powder in the conductive resin 17, 65 mass%-80 mass% are preferable, and about 76 mass% is especially preferable. When less than this, the precipitation property of electroless plating may fall, and the conductive resin 17 may not be coat | covered by the metal film 16, and when more than this, in the paste state of the conductive resin 17, Viscosity becomes high, printability falls, and filling to the via 13 which has a bottom becomes difficult.

이렇게, 도전성분으로서, 구리분말, 은도금 구리분말, 금도금 구리분말를 포함하는 것을 사용하면, 도전수지(17) 상에 금속피막(16)을 형성할 때에는, 도전수지(17) 상에 촉매를 부여하는 처리를 행하지 않고, 도전성분을 노출시키는 것만으로, 무전해도금 또는 전기도금에 의해 직접 금속피막(16)을 형성할 수 있다는 점에서 바람직하다. 이들 중에서도, 주된 도전성분이, 은도금 구리분말, 금도금 구리분말인 것이, 무전해 니켈도금이나 무전해 금도금 또는 전기 니켈도금이나 전기 금도금, 전기 구리도금의 석출성이 우수하다는 점에서 바람직하다. 이경우는, 도전수지(17) 중의 도전성분을 노출시키는 것만으로, 무전해도금이, 도전수지(17) 중에 포함되는 도전성분의 도금촉매활성에 의해, 직접 도전성분 상에 석출되므로, 무전해 도금을 소정의 두께까지 형성함으로써, 도전수지(17) 상 전체가 무전해도금에 의해 완전히 피복되어, 결과적으로 도전수지(17) 상에 직접 금속피막(16)이 형성된다. 또한, 도전수지(17) 중의 도전성분을 노출시키는 것만으로, 이 도전성분으로부터의 급전에 의해, 전기도금이 직접 도전성분 상에 석출되므로, 전기 도금을 소정의 두께까지 형성함으로써, 도전수지(17) 상 전체가 전기도금에 의해 완전히 피복되어, 결과적으로 도전수지(17) 상에 직접 금속피막(16)이 형성된다. 또한, 도전수지(17)를 충전한 후에는, 바닥을 갖는 비아(13)의 입구측의 표면을 평활화(平滑化)하기 위해서 버프연마 등의 물리적 연마를 행하지만, 이 물리적 연마에 의해, 도전수지(17) 중의 도전성분이 노출된 상태에서 바닥을 갖는 비아(13)의 입구측에 배치되므로, 과망간산이나 황산을 사용한 데스메어(desmear) 처리를 사용해서 도전수지(17)를 에칭하여 도전성분을 노출시키는 것을 필요로 하지 않아서, 무전해 도금 또는 전기도금에 의해, 도전성분상에 금속피막(16)을 직접 형성할 수 있다는 점에서 바람직하다. 또한, 데스메어 처리를 필요로 하지 않기 때문에, 도전수지(17) 이외의 부분(예를 들면, 접착제(8)나 감광성수지층(10) 등)에 데스메어 처리에 의한 영향이 없도록, 마스킹(masking)하거나 하는 공정이 불요하게 된다는 점에서 바람직하다. 또한, 도전수지(17)에 대하여 데스메어 처리를 행한 경우는, 도전수지(17)의 도전성분을 유지하는 수지성분까지도 에칭되어버려, 도전성분이 탈락하는 결과, 도전수지(17) 상에서 무전해도금 또는 전기도금의 석출성이 저하되고, 완전히 금속피막(16)으로 피복할 수 없는 문제와, 도전수지(17) 상의 금속피막(16)의 밀착을 얻기 어렵다는 문제가 있지만, 본 발명에서는, 물리적 연마에 의해서만 도전수지(17) 중의 도전성분을 노출시키므로, 이러한 문제가 없기 때문에, 도전수지(17) 상을 금속피막(17)으로 완전히 피복할 수 있고, 또한, 도전수지(17)와 금속피막(16)의 밀착을 확보할 수 있다. 또한, 물리적 연마에 의해 도전수지(17) 상에 형성된 요철(凹凸)이, 투묘(投錨)효과에 의해 금속피막(16)과의 밀착을 향상시키는 효과를 더 갖는다. 또한, 이렇게, 본 발명에서는, 도전수지(17) 상에 금속피막(16)을 형성할 때에는, 도전수지(17) 상에 촉매를 부여하는 처리와 데스메어 처리를 어느 것도 행하지 않고, 물리적 연마로 도전성분을 노출시키는 것만으로, 무전해도금 또는 전기도금에 의해 직접 금속피막(16)을 형성할 수 있다. 이 때문에, 금속피막(16)을 형성하는 부분 이외에 대해서, 보호를 위해 마스킹을 행하는 공정이나 촉매를 제거하는 공정이 불필요하며, 또한, 도전수지(17) 상 이외에, 금속피막(16)을 형성하는 부분이 있는 경우(예를 들면, 캐비티부(9) 안에 노출된 베이스층(6) 상의 와이어 본드단자(12) 등)라도, 도전수지(17) 상과 이것 이외의 금속피막(16)을 형성하고 싶은 부분의 양자를, 일괄처리에 의해, 동시에 금속피막(16)을 형성할 수 있다. 따라서 대폭으로 공수(工數)저감을 도모할 수 있다.Thus, when the conductive powder includes copper powder, silver plated copper powder, and gold plated copper powder, a catalyst is provided on the conductive resin 17 when the metal film 16 is formed on the conductive resin 17. It is preferable at the point that the metal film 16 can be formed directly by electroless plating or electroplating only by exposing an electroconductive powder, without performing a process. Among these, it is preferable that the main electroconductive powder is silver plating copper powder and gold plating copper powder from the point which is excellent in the precipitation property of electroless nickel plating, an electroless gold plating, or electro nickel plating, electroplating, and electrocopper plating. In this case, only by exposing the conductive powder in the conductive resin 17, the electroless plating is directly deposited on the conductive powder by the plating catalyst activity of the conductive powder contained in the conductive resin 17, thereby electroless plating. Is formed to a predetermined thickness, the whole of the conductive resin 17 is completely covered by electroless plating, and as a result, the metal film 16 is directly formed on the conductive resin 17. In addition, since only the conductive powder in the conductive resin 17 is exposed, electroplating directly precipitates on the conductive powder by feeding from the conductive powder, thereby forming the electroplating to a predetermined thickness, thereby forming the conductive resin 17 The entire phase) is completely covered by electroplating, resulting in the formation of a metal film 16 directly on the conductive resin 17. In addition, after the conductive resin 17 is filled, physical polishing such as buff polishing is performed to smooth the surface of the inlet side of the bottomed via 13. Since the conductive powder in the resin 17 is exposed at the inlet side of the bottomed via 13, the conductive resin 17 is etched by using a desmear treatment using permanganic acid or sulfuric acid. It is preferable in that the metal film 16 can be directly formed on the conductive powder by the electroless plating or the electroplating, since it is not necessary to expose them. In addition, since the desmare treatment is not required, the masking is performed so that the parts other than the conductive resin 17 (for example, the adhesive 8 or the photosensitive resin layer 10, etc.) are not affected by the desmear treatment. It is preferable at the point that the process of masking) becomes unnecessary. When the desmearing process is performed on the conductive resin 17, even the resin component holding the conductive powder of the conductive resin 17 is etched, and as a result, the conductive powder is eliminated, resulting in electroless discharge on the conductive resin 17. Although the precipitation property of gold or electroplating falls and it cannot fully coat | cover with the metal film 16, and there exists a problem that it is difficult to obtain the close_contact | adherence of the metal film 16 on the conductive resin 17, in this invention, Since the conductive powder in the conductive resin 17 is exposed only by polishing, since there is no such problem, the conductive resin 17 can be completely covered with the metal film 17, and the conductive resin 17 and the metal film Adhesion of (16) can be secured. In addition, the unevenness formed on the conductive resin 17 by physical polishing further has an effect of improving adhesion to the metal film 16 by the anchoring effect. As described above, in the present invention, when the metal film 16 is formed on the conductive resin 17, neither the process of applying the catalyst on the conductive resin 17 nor the desmear treatment are performed. The metal film 16 can be formed directly by electroless plating or electroplating only by exposing an electroconductive powder. For this reason, the masking process and the step of removing the catalyst are unnecessary for the protection except for the portion where the metal film 16 is formed, and the metal film 16 is formed in addition to the conductive resin 17. Even when there is a portion (for example, the wire bond terminal 12 on the base layer 6 exposed in the cavity portion 9), the metal film 16 other than the conductive resin 17 is formed. Both of the portions to be desired can be formed simultaneously with the metal coating 16. Therefore, the reduction of air-conditioning can be aimed at significantly.

도전수지(17) 상에 형성하는 무전해도금으로서는, 도전수지(17) 중에 포함되는 도전성분의 도금촉매활성에 의해 석출되는 것이라면, 사용하는 것이 가능하지만, 석출성이 좋다는 점에서 무전해 니켈도금이나 무전해 금도금이 바람직하다. 무전해 니켈도금을 행한 것에 대해 치환 금도금이나 무전해 금도금을 더 행하면, 이 금속피막(16)에 의해 형성되는 접속단자A(14) 표면의 산화가 억제되기 때문에, 접속시의 접속저항의 상승을 억제하고, 또한 땜납누출성을 유지할 수 있다는 점에서 바람직하다. 또한, 본 발명에서, 무전해 금도금이란, 소위 환원형의 무전해 금도금을 말하며, 치환형의 금도금과 구별되는 것을 말한다. 무전해 니켈도금의 두께는 4㎛ ~ 6㎛가 바람직하다. 무전해 니켈도금의 두께가 이보다 얇으면 도전수지(17) 상의 금속피막(16)에 의한 피복이 불충분하게 되어 신뢰성 저하의 가능성이 있다. 무전해 니켈 도금의 두께가 이보다 두꺼우면, 비용상승으로 이어지고, 또한 도금응력이 크게 되어 금속피막(16)의 밀착이 저하될 가능성이 있다. 또한, 종래의 스루홀 도금과 구멍메움수지의 충전에 의한 층간접속(31)의 형성에서는, 구멍메움수지가 무전해 도금에 대하여 촉매활성을 갖지 않으므로, 도금촉매의 부여가 필요하고, 이 경우는, 도금이 불필요한 영역에서는, 도금촉매가 묻지 않도록 마스킹할 필요가 있기 때문에, 공수가 많아진다는 문제가 있었다. 본 발명에 의하면, 무전해 도금에 대하여 촉매활성을 갖는 도전수지(17)를 사용하고, 도전수지(17) 중의 도전성분의 노출을 버프연마 등의 물리적 연마로 행하므로, 무전해 도금의 석출성과 밀착성을 확보할 수 있다. 이 때문에, 무전해 도금으로서, 종래와 같이 하지도금으로서 무전해 구리도금을 행하고 나서 무전해 니켈도금과 치환 금도금이나 무전해 금도금 등을 행할 필요가 없이, 적은 공수로, 바닥을 갖는 비아(13)의 바로 위에, 땜납누출성을 확보한 접속단자를 형성할 수 있다.As the electroless plating formed on the conductive resin 17, it can be used as long as it is precipitated by the plating catalyst activity of the conductive powder contained in the conductive resin 17. However, the electroless nickel plating is possible in that the precipitation property is good. Electroless gold plating is preferred. Substituting gold plating or electroless gold plating with respect to electroless nickel plating further inhibits oxidation of the surface of the connection terminal A 14 formed by the metal film 16, thereby increasing the connection resistance at the time of connection. It is preferable at the point which can suppress and maintain solder leakage property. In addition, in this invention, an electroless gold plating means what is called a reduced type electroless gold plating, and is distinguished from a substituted gold plating. The thickness of the electroless nickel plating is preferably 4 µm to 6 µm. If the thickness of the electroless nickel plating is thinner than this, the coating by the metal film 16 on the conductive resin 17 becomes insufficient, which may lead to a decrease in reliability. If the thickness of the electroless nickel plating is thicker than this, the cost increases, and the plating stress becomes large, whereby the adhesion of the metal film 16 may be reduced. In the conventional formation of the interlayer connection 31 by through-hole plating and filling of the hole filling resin, since the hole filling resin does not have catalytic activity against electroless plating, provision of a plating catalyst is necessary, in this case In the area where plating is not necessary, it is necessary to mask the plating catalyst so that it does not adhere, and thus there is a problem that the number of man-hours increases. According to the present invention, since the conductive resin 17 having catalytic activity against the electroless plating is used and the conductive powder in the conductive resin 17 is exposed by physical polishing such as buff polishing, the precipitation performance of the electroless plating Adhesion can be secured. Therefore, as the electroless plating, the electroless copper plating is performed as the base plating as in the prior art, and then the electroless nickel plating, the substitutional gold plating, the electroless gold plating, and the like do not need to be carried out. Directly above the connection terminal, the solder leakage property can be formed.

도전수지(17) 상에 형성하는 전기도금으로서는, 도전수지(17) 중에 포함되는 도전성분의 도전성을 이용하여 급전함으로써, 직접 도전성분 상에 석출되는 것이라면, 사용하는 것이 가능하지만, 석출성이 좋다는 점에서 전기 니켈도금이나 전기 금도금, 전기 구리도금이 바람직하다. 도전수지(17)의 도전성분 상에 직접 전기 구리도금을 행한 것에 더해 무전해 니켈도금 또는 전기 니켈도금을 행하고, 치환 금도금 또는 무전해 금도금 또는 전기 금도금을 더 행하는 경우, 또는 도전수지(17)의 도전성분 상에 직접 전기 니켈도금을 행한 것에 더해, 치환 금도금 또는 무전해 금도금 또는 전기 도금을 더 행하는 경우는, 이 금속피막(16)에 의해 형성되는 접속단자A(14) 표면의 산화가 억제되기 때문에, 접속시의 접촉저항의 상승을 억제하고, 또한, 땜납누출성을 유지할 수 있다는 점에서 바람직하다. 특히, 후자와 같이, 도전수지(17)의 도전성분 상에 직접 전기 니켈도금을 행하면, 전자와 같이, 전기 니켈도금의 하지도금으로서 전기 구리도금을 행할 필요가 없이, 적은 공수로, 바닥을 갖는 비아(13)의 바로 위에, 땜납누출성을 확보한 접속단자를 형성할 수 있다. 이렇게, 도전수지(17)의 도전성분 상에 직접 전기 니켈도금을 행하는 경우, 전기 니켈도금의 두께는, 4㎛ ~ 16㎛가 바람직하다. 전기 니켈도금의 두께가 이보다 얇으면 도전수지(17) 상의 금속피막(16)에 의한 피복이 불충분하게 되어 신뢰성 저하의 가능성이 있다. 전기 니켈도금의 두께가 이보다 두꺼우면, 비용상승으로 이어지고, 또한 도금응력이 크게 되어 금속피막(16)의 밀착이 저하될 가능성이 있다. 또한, 전기 니켈도금의 위에 전기 금도금을 행하는 경우, 전기 금도금의 두께는, 0.5㎛ ~ 1.5㎛가 바람직하다. 전기 금도금의 두께가 이보다 얇으면, 표면의 산화를 억제하는 효과가 저하되고, 한편, 전기 금도금의 두께가 이보다 두꺼우면, 비용상승으로 이어진다.As the electroplating formed on the conductive resin 17, it can be used as long as it is directly deposited on the conductive powder by feeding power using the conductivity of the conductive powder contained in the conductive resin 17, but the precipitation property is good. Electroplating nickel plating, electroplating, and electroplating are preferable at this point. In addition to electroplating copper directly on the conductive powder of the conductive resin 17, electroless nickel plating or electronickel plating is performed, and substitution gold plating or electroless gold plating or electrogold plating is further performed, or the conductive resin 17 In addition to electroplating nickel directly on the conductive powder, in addition to substitution gold plating, electroless gold plating or electroplating, oxidation of the surface of the connection terminal A 14 formed by the metal film 16 is suppressed. Therefore, it is preferable at the point which can suppress the raise of the contact resistance at the time of connection, and can maintain solder leakage property. In particular, when the latter is subjected to electro-nickel plating directly on the conductive powder of the conductive resin 17, like the former, it is not necessary to perform electro-copper plating as the base plating of the electro-nickel plating. Immediately on the via 13, a connection terminal having a solder leakage property can be formed. In this way, when electro-nickel plating is directly performed on the conductive powder of the conductive resin 17, the thickness of the electro-nickel plating is preferably 4 µm to 16 µm. If the thickness of the electric nickel plating is thinner than this, the coating by the metal film 16 on the conductive resin 17 becomes insufficient, which may lead to a decrease in reliability. If the thickness of the electric nickel plating is thicker than this, the cost increases, and the plating stress becomes large, whereby the adhesion of the metal film 16 may decrease. In addition, when electroplating is carried out on electronickel plating, the thickness of electroplating is preferably 0.5 µm to 1.5 µm. If the thickness of the electro-gold plating is thinner than this, the effect of suppressing the oxidation of the surface is lowered. On the other hand, if the thickness of the electro-gold plating is thicker than this, the cost is increased.

도전수지(17) 상에는, 접속단자A(14)가 설치된다. 접속단자A(14)는, 외부기판과 전기적으로 접속하기 위한 것으로, 본 발명의 반도체소자 탑재용 패키지 기판(1)이 PoP에서 하부 기판(33)으로서 사용되는 경우, 또는 본 발명의 반도체 패키지(36)가 PoP에서 하부 패키지(35)로서 사용되는 경우는, 상부 기판(32)(다른 반도체소자 탑재용 패키지 기판(1)) 또는 상부 패키지(34)(다른 패키지 기판)와의 접속을 위해 접속단자로서 사용된다.The connection terminal A 14 is provided on the conductive resin 17. The connection terminal A 14 is for electrically connecting with an external substrate. When the semiconductor device mounting package substrate 1 of the present invention is used as the lower substrate 33 in PoP, or the semiconductor package of the present invention ( When 36 is used as the lower package 35 in the PoP, the connection terminal for connection with the upper substrate 32 (package substrate 1 for mounting another semiconductor element) or the upper package 34 (other package substrate) Used as

도전수지(17)를 충전하여 경화한 후에, 바닥을 갖는 비아(13)보다도 위쪽으로 튀어나온 도전수지(17)에 대하여 행하는 연마로서는, 예를 들면, 버프연마나 벨트센더(belt sander) 등을 사용하는 물리적 연마를 사용할 수 있다. 가운데에서도 버프롤에 의한 기계연마가 바람직하고, 버프의 번수는, 600번, 800번, 1000번, 혹은 그들을 조합하여 사용한다. 버프롤로서는, 예를들면, 구멍메움수지 연마용의 JP버프몬스터 V3/V3-D2(쟈브로고교제 상품명)를 사용할 수 있다. 또한, 연마전류는 0.1A ~ 2.0A 정도로 연마를 행하지만, 삭감하는 도전수지(17)의 양에 따라 전류값도 조정한다. 바람직하게는 1.0A ~ 1.4A정도이다.After the conductive resin 17 is filled and cured, the polishing performed on the conductive resin 17 protruding upward from the bottomed via 13 may include, for example, buff polishing or a belt sander. The physical polishing used can be used. Among them, mechanical polishing by buffing is preferred, and the number of buffs is 600, 800, 1000, or a combination thereof. As the buff roll, for example, JP buff monster V3 / V3-D2 (trade name, manufactured by Jabro Kogyo Co., Ltd.) for hole filling resin polishing can be used. The polishing current is polished at about 0.1A to 2.0A, but the current value is also adjusted in accordance with the amount of the conductive resin 17 to be reduced. Preferably it is about 1.0A-1.4A.

접속단자A(14)의 형성의 일예로서는, 우선 바닥을 갖는 비아(13) 안에 충전된 도전수지(17) 위에, 금속피막(16)을 형성함으로써 행해진다. 예를 들면, 바닥을 갖는 비아(13) 안에 도전수지(17)를 충전한 후, 연마하여, 도전수지(17) 표면을 캐비티재(7)와 한면으로 함과 아울러, 미리 캐비티재(7) 상에 구비한 동박(銅箔, 40)을 노출시킨다(여기서, 도전수지(17)를 충전하기 전에 바닥을 갖는 비아(13) 안에 금속피복(18)을 행한 경우는, 금속피복(18)을 노출시킨다). 그리고, 노출한 동박(40)(또는 금속피복(18))과 도전수지(17) 상에 도금 레지스트(도시하지 않음)를 형성 후, 무전해 도금 또는 전기 도금으로 금속피막(16)을 형성하고, 이것을 에칭레지스트로서 에칭함으로써, 불필요한 개소의 동박(40)을 제거하여 접속단자A(14)를 형성한다. 무전해 도금은, 무전해 구리도금, 무전해 니켈도금, 무전해 금도금 등을 사용할 수 있고, 전기 도금은, 전기 구리도금, 전기 니켈도금, 전기 금도금 등을 사용할 수 있다. 이 경우의 무전해 도금으로서는, 촉매부여를 행하지 않아도 도전수지(17) 상으로의 석출성이 좋다는 점에서, 무전해 니켈도금이나 무전해 금도금이 바람직하다. 전기 도금으로서는, 도전수지(17) 상으로의 석출성이 좋다는 점에서, 전기 니켈도금이나 전기 금도금이 바람직하다. 이와 같이, 도전수지(17)와 랜드패턴만으로 선택적으로 직접 금속피막(16)을 형성할 수 있음으로써, 캐비티재(7) 상의 다른 부분의 도체 두께를 얇게 할 수 있으므로, 미세한 피치의 단자가 형성되기 쉽고, 고밀도화를 도모하는 것이 가능하게 된다.As an example of formation of the connection terminal A 14, first, the metal film 16 is formed on the conductive resin 17 filled in the via 13 having a bottom. For example, the conductive resin 17 is filled into the via 13 having a bottom, and then polished to make the surface of the conductive resin 17 one side with the cavity material 7, and the cavity material 7 in advance. The copper foil 40 provided on the surface is exposed. (In this case, when the metal coating 18 is performed in the bottomed via 13 before the conductive resin 17 is filled, the metal coating 18 is removed. Exposure). Then, after forming a plating resist (not shown) on the exposed copper foil 40 (or the metal coating 18) and the conductive resin 17, the metal coating 16 is formed by electroless plating or electroplating. By etching this as an etching resist, the unnecessary copper foil 40 is removed and the connection terminal A 14 is formed. Electroless plating may use electroless copper plating, electroless nickel plating, electroless gold plating, etc., and electroplating may use electric copper plating, electric nickel plating, electroplating, and the like. As the electroless plating in this case, electroless nickel plating or electroless gold plating are preferable in that the precipitation property on the conductive resin 17 is good even without applying the catalyst. As electroplating, electroplating and electroplating are preferable at the point that precipitation property on the electrically conductive resin 17 is good. In this way, the metal film 16 can be selectively formed directly only by the conductive resin 17 and the land pattern, so that the conductor thickness of the other part on the cavity material 7 can be made thin, so that fine pitch terminals are formed. It is easy to become high density, and it becomes possible to aim at high density.

반도체소자(2)는, 캐비티층(5) 측의 면의 캐비티부(9)에 대응하는 영역에 탑재된다. 반도체소자(2)의 탑재는, 예를 들면 다이본드필름으로 베이스층(6) 상에 접착되어, 와이어 본드단자(12)와 본딩 와이어(4)에 의해 반도체소자(2)와 전기적으로 접속된다. 이 반도체소자(2)의 베이스층(6)에의 탑재는, 접속단자C(27)(도 6)를 사용하여, 플립칩(flip chip)접속이나 도전성 접착제에 의한 접속을 사용할 수도 있다.The semiconductor element 2 is mounted in a region corresponding to the cavity portion 9 on the surface of the cavity layer 5 side. The mounting of the semiconductor device 2 is, for example, bonded to the base layer 6 with a die bond film and electrically connected to the semiconductor device 2 by the wire bond terminal 12 and the bonding wire 4. . The semiconductor element 2 can be mounted on the base layer 6 by using a connection terminal C 27 (FIG. 6), and using flip chip connection or connection with a conductive adhesive.

반도체소자(2)는, 습기 등의 환경으로부터 보호하기 위해서, 봉지제(3)에 의해 봉지된다. 이러한 봉지제(3)로서, 에폭시수지, 폴리이미드수지, 실리콘, 우레탄페놀계수지, 폴리에스테르계수지, 아크릴계수지 그밖에 열경화성수지, 열가소성수지 등을 사용할 수 있다.
The semiconductor element 2 is sealed by the sealing agent 3 in order to protect it from the environment, such as moisture. As such encapsulant (3), epoxy resins, polyimide resins, silicones, urethane phenol resins, polyester resins, acrylic resins, thermosetting resins, thermoplastic resins and the like can be used.

실시예Example

이하에서, 본 발명의 실시예를 설명하지만, 본 발명은 본 실시예에 한정되지 않는다.In the following, an embodiment of the present invention is described, but the present invention is not limited to this embodiment.

(실시예 1)(Example 1)

[캐비티층의 제작][Production of cavity layer]

도 3에 나타낸 바와 같이, 캐비티재(7)로서, 양면에 두께 9㎛, 12㎛, 18㎛의 동박을 붙인 두께 0.2mm의 에폭시수지 글라스 포(布) 동장적층판인 MCL-E679F(히다치가세이고쿄가부시키가이샤제, 상품명)를 준비했다. NC드릴머신인 MARK-100(히타치세이코가부시키가이샤제, 상품명)에 의해 가이드공(도시하지 않음)과 관통공A(24)를 뚫었다.As shown in FIG. 3, MCL-E679F (Hitachi Kasei) which is an epoxy resin glass cloth copper clad laminated board of thickness 0.2mm which attached the copper foil of thickness 9 micrometers, 12 micrometers, and 18 micrometers on both surfaces as the cavity material 7 is shown. (Trade name), manufactured by Tokyo Corporation. A guide hole (not shown) and a through hole A 24 were drilled by MARK-100 (trade name, manufactured by Hitachi Seiko Co., Ltd.), an NC drill machine.

다음으로, 캐비티재(7)의 동박 표면에, 자외선경화형 에칭레지스트용 드라이필름 H-W425(히다치가세이고쿄가부시키가이샤제 상품명)를 라미네이터로, 압력 0.2MPa, 온도 110℃, 속도1.5m/분인 조건에서 임시압착하고, 이어서, 그 위에 네가티브형 마스크를 붙이고, 자외선으로 노광하여, 회로를 소부(燒付)하고, 1질량%의 탄산나트륨 수용액으로 현상하고, 에칭레지스트를 형성한 후, 동박(40) 상의 에칭레지스트가 없는 부분을 스프레이 분무에 의해, 염화 제2구리, 염산, 황산과수의 조성으로 이루어지는 염화 제2구리 에칭액으로 압력 0.2MPa, 속도 3.5m/분인 조건에서 행하고, 3질량% 수산화나트륨 수용액을 더 분무하여 에칭레지스트를 박리제거하여, 구리 패턴을 형성했다. 이것에 의해, 한쪽 면에 대해서는, 관통공A(40)의 주위에 환상링이 되는 내층회로(19)를 형성했다. 이때의 내층회로(19)의 두께는, 캐비티재(7)로서 사용한 MCL의 동박의 두께(9㎛, 12㎛, 18㎛)에 대응하고 있어, 각각, 9㎛, 12㎛, 18㎛ 었다. 다른쪽 면, 즉, 접속단자A(14)를 형성하는 면에 대해서는, 거의 전면(全面)에 동박(40)을 남겼다.Next, on the copper foil surface of the cavity material 7, dry film H-W425 (Hitachi Chemical Co., Ltd. brand name) for ultraviolet curing type etching resist was used as a laminator, pressure 0.2MPa, temperature 110 degreeC, speed 1.5m. Temporary compression was carried out under conditions of / min, and then a negative mask was applied thereon, followed by exposure to ultraviolet rays, baking the circuit, developing with an aqueous solution of 1% by mass sodium carbonate, and forming an etching resist, followed by copper foil. The part without the etching resist on (40) was spray-sprayed, and it carried out by the conditions of the cupric chloride etching liquid which consists of a composition of cupric chloride, hydrochloric acid, and a sulfuric acid under the pressure of 0.2 MPa and a speed of 3.5 m / min, 3 masses The aqueous solution of% sodium hydroxide was further sprayed to remove the etching resist to form a copper pattern. Thereby, about one surface, the inner layer circuit 19 which becomes an annular ring was formed around the through-hole A40. The thickness of the inner layer circuit 19 at this time corresponded to the thickness (9 micrometers, 12 micrometers, 18 micrometers) of the copper foil of MCL used as the cavity material 7, and was 9 micrometers, 12 micrometers, and 18 micrometers, respectively. About the other surface, ie, the surface which forms the connection terminal A14, the copper foil 40 was left in almost the whole surface.

다음으로, 접착제(8)로서, 두께 25㎛의 에폭시계 드라이필름상의 접착시트 AS2600(히다치가세이고쿄가부시키가이샤제, 상품명)을 사용하고, 라미네이터에 의해, 90℃의 온도에서, 압력을 0.4MPa로 하고, 송출속도 0.4m/분으로, 가열?가압하여, 캐비티재(7)에 임시부착했다. 다음으로, 접착시트에는, 캐비티재(7)에 설치한 관통공A(24)에 합쳐서, 개구부를 타발금형으로 형성했다. 다음으로, NC라우터기를 사용하여, 12mm×12mm의 크기의 개구(25)를 형성했다.Next, as the adhesive 8, the adhesive sheet AS2600 (made by Hitachi Chemical Co., Ltd., brand name) of the epoxy-type dry film of thickness 25micrometer was used, and a pressure was applied by the laminator at the temperature of 90 degreeC. It was set to 0.4 MPa, and it heated and pressed at the feed rate of 0.4 m / min, and temporarily attached to the cavity material 7. Next, in the adhesive sheet, the openings were formed in a punching die together with the through holes A 24 provided in the cavity material 7. Next, the opening 25 of the magnitude | size of 12 mm x 12 mm was formed using NC router.

[베이스층의 제작][Production of base layer]

도 4에 나타낸 바와 같이, 베이스재a(28)로서, 양면에 두께 12㎛의 동박을 붙인 두께 0.06mm의 에폭시수지 글라스 포(布) 동장 적층판인 MCL-E679F(히다치가세이고쿄가부시키가이샤제, 상품명)에 NC드릴머신인 MARK-100(히타치세이코가부시키가이샤제, 상품명)에 의해, 관통공B(30)를 뚫었다.As shown in Fig. 4, MCL-E679F (Hitachi Kasei Kogyo Co., Ltd.), which is an epoxy resin glass cloth copper clad laminate having a thickness of 0.06 mm, having a copper foil having a thickness of 12 μm on both sides as a base material a 28. The through hole B 30 was drilled by MARK-100 (the Hitachi Seiko Co., Ltd. make, brand name) which is an NC drill machine.

다음으로, 이 관통공B(39)의 데스메어처리를 과망간산나트륨수용액에서 온도 85℃로 6분간인 조건에서 행하고, 무전해 구리도금인 CUST201(히다치가세이고쿄가부시키가이샤제, 상품명), 황산구리 10g/L, EDTA40g/L, 포르말린 10m/L, pH12.2)에 온도 24℃, 시간 30분인 조건에서, 관통공B(39) 안을 포함하는 베이스재a(28)의 전면(全面)에 0.5㎛의 하지 구리도금을 행했다. 다음으로, 황산 구리도금으로 온도 30℃, 전류밀도 1.5A/d㎡, 시간 60분인 조건에서, 관통공B(39) 안을 포함하는 베이스재a(28)의 전면에, 도금두께 20㎛의 전기 구리도금(41)을 형성했다.Next, the desmearing treatment of the through-hole B 39 is carried out in an aqueous sodium permanganate solution at a temperature of 85 ° C. for 6 minutes, CUST201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is electroless copper plating. Copper sulfate 10g / L, EDTA40g / L, formalin 10m / L, pH12.2) at a temperature of 24 ° C. and a time of 30 minutes, on the entire surface of the base material a 28 including the through hole B 39. 0.5 micrometer of base copper plating was performed. Next, an electroplating thickness of 20 μm was applied to the entire surface of the base material a 28 including the through hole B 39 under conditions of 30 ° C., a current density of 1.5 A / dm 2, and a time of 60 minutes with copper sulfate plating. Copper plating 41 was formed.

다음으로, 베이스재a(28)의 동박(40) 표면에, 자외선경화형 에칭레지스트용 드라이필름 H-W425(히다치가세이고쿄가부시키가이샤제, 상품명)를 라미네이터로, 압력 0.2MPa, 온도 110℃, 속도 1.5m/분인 조건에서, 임시압착하고, 이어서 그 상면에 네가티브형 마스크를 붙여, 자외선으로 노광하여, 회로를 소부하고, 1질량%의 탄산나트륨 수용액으로 현상하여, 에칭레지스트를 형성하고, 그 에칭레지스트가 없는 동박(40) 부분을 스프레이 분무에 의해, 염화 제2구리, 염산, 황산과수의 조성으로 이루어지는 염화 제2구리 에칭액으로 압력 0.2MPa, 속도 3.5m/분인 조건에서 행하고, 3질량% 수산화나트륨 수용액을 더 분무하여 에칭레지스트를 박리제거하여, 베이스재a(28)의 표리(表裏)에 회로를 형성했다. Next, on the copper foil 40 surface of the base material a28, dry film H-W425 (made by Hitachi Chemical Co., Ltd., brand name) for ultraviolet curing type etching resist is a laminator, pressure 0.2MPa, temperature 110 Temporary compression was carried out under the conditions of a temperature of 1.5 m / min, followed by a negative mask on the upper surface thereof, followed by exposure to ultraviolet rays to bake the circuit, and development with an aqueous solution of 1% by mass sodium carbonate to form an etching resist. The copper foil 40 part without the etching resist was spray-sprayed in a cupric chloride etching solution composed of cupric chloride, hydrochloric acid, and sulfuric acid fruit water under conditions of a pressure of 0.2 MPa and a speed of 3.5 m / min, 3 An aqueous solution of mass% sodium hydroxide was further sprayed to remove the etching resist, thereby forming a circuit in the front and back of the base material a (28).

다음으로, 베이스재b(29), 베이스재c(30)로서, 두께 0.06mm의 에폭시수지 글라스 크로스 포(布) 프리프레그인 GEA-679NUJY(히다치가세이고쿄가부시키가이샤제, 상품명)를 준비했다. 또한, 동박(40)으로서, 두께 12㎛의 동박인 3EC-VLP-12(미쓰이 킨죠쿠고교가부시키가이샤제, 상품명)를 준비했다. 이들의 에폭시수지 글라스 크로스 포 프리프레그를, 먼저 준비한 베이스재a(28)의 양면의 회로상에 겹치고, 두께 12㎛의 동박(40)을 그 위에 더 겹쳐서, 진공프레스를 사용하여, 압력 3MPa, 온도175℃, 유지시간 1.5시간인 조건에서 가압가열하여 적층 일체화했다. 이와 같이, 베이스재a(28)의 한 쪽면에 베이스재b(29)와 동박(40)을, 다른쪽 면에 베이스재c(30)와 동박(40)을 적층 일체화 함으로써, 베이스재(21)를 제작했다.Next, GEA-679NUJY (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an epoxy resin glass cross cloth prepreg having a thickness of 0.06 mm, is used as the base material b 29 and the base material c 30. Ready. Moreover, 3EC-VLP-12 (Mitsui Kinjoku Kogyo Co., Ltd. make, brand name) which is copper foil of 12 micrometers in thickness was prepared as the copper foil 40. These epoxy resin glass cross four prepregs are superimposed on the circuits on both sides of the base material a 28 prepared earlier, and the copper foil 40 having a thickness of 12 µm is further superimposed thereon, using a vacuum press to obtain a pressure of 3 MPa, The laminate was integrally heated under pressure under a condition of a temperature of 175 ° C and a holding time of 1.5 hours. In this way, the base material 21 is laminated by integrating the base material b 29 and the copper foil 40 on one surface of the base material a 28 and the base material c 30 and the copper foil 40 on the other surface. )

다음으로, 베이스재(21)의 동박(40) 표면에, 자외선경화형 에칭레지스트용 드라이필름 H-W425(히다치가세이고쿄가부시키가이샤제, 상품명)를 라미네이터로, 압력 0.2MPa, 온도110℃, 속도 1.5m/분인 조건에서 임시압착하고, 이어서 그 상면에 네가티브형 마스크를 붙이고, 자외선으로 노광하여, 회로를 소부하고, 1질량%의 탄산나트륨 수용액으로 현상하여, 에칭레지스트를 형성하고, 그 에칭레지스트가 없는 구리부분을 스프레이 분부에 의해, 염화 제2구리, 염산, 황산과수의 조성으로 이루어지는 염화 제2구리 에칭액으로 압력 0.2MPa, 속도 3.5m/분인 조건에서 행하고, 3질량% 수산화나트륨 수용액을 더 분무하여 에칭레지스트 박리제거하여, 컨포멀마스크(22)를 형성했다.Next, on the copper foil 40 surface of the base material 21, dry film H-W425 (made by Hitachi Chemical Co., Ltd., brand name) for ultraviolet curing type etching resists by a laminator, pressure 0.2MPa, temperature 110 degreeC. After the temporary compression under conditions of a speed of 1.5 m / min, a negative mask was attached to the upper surface thereof, and then exposed to ultraviolet rays, the circuit was baked, and developed with a 1 mass% sodium carbonate aqueous solution to form an etching resist. The copper part without a resist is sprayed with a cupric chloride etching solution composed of cupric chloride, hydrochloric acid, and sulfuric acid fruit water under a condition of 0.2 MPa pressure and 3.5 m / min. Was further sprayed to remove the etching resist and the conformal mask 22 was formed.

다음으로, 베이스제(21)에, NC레이저가공기 MARK-20(히타치세이코가부시키가이샤제, 상품명)을 사용하여, 애퍼처(aperture)직경 φ0.26, 출력 500W, 펄스폭 15㎲, 쇼트수 15인 조건에서 가공하여 레이저구멍(26)을 형성하고, 이어서, 이 레이저구멍(26)의 데스메어처리를 과망간산나트륨 수용액에서 온도 85℃로 6분간인 조건에서 행하고, 무전해 구리도금인 CUST201(히다치가세이고쿄가부시키가이샤제, 상품명), 황산구리 10g/L, EDTA 40g/L, 포르말린 10ml/L, pH12.2)에 온도 24℃, 시간 30분인 조건에서, 레이저구멍(26) 안을 포함하는 베이스재(21)의 전면에 0.5㎛의 하지 구리도금을 행했다.Next, an aperture diameter φ 0.26, an output 500 W, a pulse width of 15 s, and a short were used for the base 21 by using an NC laser processing machine MARK-20 (manufactured by Hitachi Seiko Co., Ltd.). The laser hole 26 was formed by processing under a condition of 15, and then the desmearing treatment of the laser hole 26 was carried out in an aqueous sodium permanganate solution at a temperature of 85 ° C. for 6 minutes, and the electroless copper plating CUST201 (Hitachi Chemical Co., Ltd. make, brand name), copper sulfate 10g / L, EDTA 40g / L, formalin 10ml / L, pH12.2) The inside of the laser hole 26 was opened on condition that temperature is 24 degreeC and time 30 minutes. 0.5 micrometer of base copper plating was performed to the whole surface of the base material 21 to include.

다음으로, 황산 구리도금으로 온도 30℃, 전류밀도 1.5A/d㎡, 시간 60분인 조건에서, 레이저구멍(26) 안을 포함하는 베이스재b(29), 베이스재c(30)의 전면에, 도금두께 20㎛의 전기 구리도금을 형성했다.Next, on the whole surface of the base material b29 and the base material c30 which contain the inside of the laser hole 26 on the conditions which are 30 degreeC, current density 1.5A / dm <2>, and 60 minutes time with copper sulfate plating, Electroplating copper plating with a thickness of 20 mu m was formed.

다음으로, 베이스제(21)의 전기 구리도금 표면에, 자외선경화형 에칭레지스트용 드라이 필름 H-W475(히다치가세이고쿄가부시키가이샤제, 상품명)를 라미네이터로, 압력 0.2MPa, 온도 110℃, 속도 1.5m/분인 조건으로 임시압착하고, 이어서 그 상면에 네가티브형 마스크를 붙이고, 자외선으로 노광하여, 회로를 소부하고, 1질량%의 탄산나트륨 수용액으로 현상하여, 에칭레지스트를 형성하고, 그 에칭레지스트가 없는 구리부분을 스프레이 분무에 의해, 염화 제2구리, 염산, 황산과수의 조성으로 이루어지는 염화 제2구리 에칭액으로 압력 0.2MPa, 속도 3.5m/분인 조건에서, 회로 형성하고, 이어서, 3질량% 수산화나트륨 수용액을 분무하여 에칭레지스트 박리제거를 행했다. 이것에 의해, 접속패드(11), 접속단자B(15) 등을 포함하는 회로를 형성했다. 이 때의 접속단자B(15)의 직경은 φ0.3mm, 피치는 0.5mm이었다.Next, on the electric copper plating surface of the base agent 21, dry film H-W475 (made by Hitachi Chemical Co., Ltd., brand name) for ultraviolet curing type etching resists by a laminator, pressure 0.2MPa, temperature 110 degreeC, Temporary compression was carried out under the condition of a speed of 1.5 m / min, and then a negative mask was attached to the upper surface thereof, followed by exposure to ultraviolet rays, the circuit was baked, developed with an aqueous solution of 1% by mass of sodium carbonate to form an etching resist, and the etching resist. The copper part without copper was formed by spray spraying in a cupric chloride etching solution composed of cupric chloride, hydrochloric acid, and sulfuric acid fruit water under a condition of 0.2 MPa pressure and a speed of 3.5 m / min, followed by 3 masses. Etching resist stripping was performed by spraying a% aqueous sodium hydroxide solution. Thereby, the circuit containing the connection pad 11, the connection terminal B15, etc. was formed. At this time, the diameter of the connection terminal B 15 was phi 0.3 mm and the pitch was 0.5 mm.

다음으로, 회로 형성을 행한 베이스재(21)의 표면에, 액상레지스트인 PSR-4000(다이요인키세이조가부시키가이샤제, 상품명)을 인쇄하고, 80℃, 20분간 건조 후, 그 상면에 네가티브형 마스크를 붙여 합치고, 자외선으로 노광하고, 또한 1.5질량% 탄산나트륨 수용액으로 현상하고, 자외선 1J/㎠의 조사에 의해 한층 더 경화를 행하고, 150℃로 60분 건조 후, 감광성수지층(10)으로서의 솔더레지스트(23)를 형성하여, 베이스층(6)을 제작했다. 또한, 이 솔더레지스트(23)(감광성수지층(10))의 형성은, 베이스재(21)의 접속패드(11)를 형성한 면 측에만 형성하고, 다른 면에는 형성하지 않았다.Next, PSR-4000 (manufactured by Daiyo Chemical Co., Ltd., trade name), which is a liquid resist, was printed on the surface of the base member 21 on which the circuit was formed, dried at 80 ° C. for 20 minutes, and then negative on the upper surface thereof. The paste was bonded together, exposed with ultraviolet light, further developed with a 1.5 mass% sodium carbonate aqueous solution, further cured by irradiation with ultraviolet light of 1 J / cm 2, and dried at 150 ° C. for 60 minutes, and then as the photosensitive resin layer 10. The soldering resist 23 was formed and the base layer 6 was produced. In addition, this soldering resist 23 (photosensitive resin layer 10) was formed only in the surface side in which the connection pad 11 of the base material 21 was formed, and was not formed in the other surface.

[반도체소자 탑재용 패키지 기판의 제작][Production of Package Substrate for Semiconductor Device Loading]

다음으로, 도 5에 나타낸 바와 같이, 캐비티층(5)의 접착제(8)를 임시부착한 면과, 베이스층(6)의 감광성수지층(10)(솔더레지스트(23))을 형성한 면이 마주보도록 겹치고, 진공프레스를 사용하여, 압력 3MPa, 온도 175℃, 유지시간 1.5시간인 조건에서 가압가열하여 적층 일체화하여, 반도체소자 탑재용 패키지 기판(1)으로 했다. 이 때, 캐비티층(5)에 설치된 관통공A(24)가, 베이스층(6)에 설치된 접속패드(11)에 의해 막히도록 적층되고, 접속패드(11)를 저면으로 한 바닥을 갖는 비아(13)가, 캐비티층(5)에 형성된다. 이 때, 접착제(8)가 유동하지만, 캐비티재(7) 상의 관통공A(24)의 주위에 설치한 환상링이, 관통공A(24)의 주위를 완전히 둘러싼 댐으로서 작용하므로, 접착제(8)가 관통공A(24) 내측으로 유동하는 것을 억제할 수 있었다. 관통공A(24) 내측으로의 접착제의 유동은, 관통공A(24)의 내벽에서 접속패드(11) 상으로의 배어 나오는 양(배어나온 거리)으로 관찰할 수 있고, 본 실시예에서는, 한쪽 측에서 30㎛이하의 레벨이었다. 또한, 내층회로(19)가 두께(9㎛, 12㎛, 18㎛)를 갖고 있으므로, 내층회로(19)에 대응하는 부분의 접착제(8)는, 그 이외의 부분에 비하여, 두께가 얇게 형성된다. 이 실시예 1에서는, 캐비티재(7) 상의 내층회로(19)와 베이스층(6)의 감광성수지(10) 사이에 끼워지는 부분의 접착제의 두께는, 1 ~ 5㎛이고, 이들에 끼워지지 않는 부분에 비하여 얇게 되었다.Next, as shown in FIG. 5, the surface which temporarily attached the adhesive agent 8 of the cavity layer 5, and the surface which formed the photosensitive resin layer 10 (solder resist 23) of the base layer 6 were formed. They were stacked so as to face each other, and were pressurized by heating under a pressure of 3 MPa, a temperature of 175 ° C., and a holding time of 1.5 hours to form a laminate, thereby forming a package substrate 1 for mounting a semiconductor element. At this time, the through-hole A 24 provided in the cavity layer 5 is laminated | stacked so that it may be blocked by the connection pad 11 provided in the base layer 6, and the via which has a bottom which made the connection pad 11 the bottom face is carried out. 13 is formed in the cavity layer 5. At this time, although the adhesive agent 8 flows, since the annular ring provided around the through hole A 24 on the cavity material 7 acts as a dam which completely encloses the periphery of the through hole A 24, the adhesive agent ( 8) can be prevented from flowing into the through hole A 24. The flow of the adhesive to the inside of the through hole A 24 can be observed by the amount of bleeding out from the inner wall of the through hole A 24 onto the connection pad 11, and in this embodiment, It was a level of 30 micrometers or less from one side. In addition, since the inner layer circuit 19 has a thickness (9 µm, 12 µm, 18 µm), the adhesive 8 in the portion corresponding to the inner layer circuit 19 is formed to be thinner than the other portions. do. In the first embodiment, the thickness of the adhesive at the portion sandwiched between the inner layer circuit 19 on the cavity material 7 and the photosensitive resin 10 of the base layer 6 is 1 to 5 탆, It became thin compared to the part which is not.

다음으로, 이 바닥을 갖는 비아(13) 안에, 베이스재(21)인 때와 마찬가지로 하여, 바닥을 갖는 비아(13) 안의 데스메어처리를 행하고, 바닥을 갖는 비아(13) 안을 포함하는 반도체소자 탑재용 패키지 기판(1)의 전면에 0.5㎛의 하지 구리도금을 행했다.Next, the semiconductor device including the inside of the via 13 having the bottom is subjected to a desmere treatment in the via 13 having the bottom, as in the case of the base material 21, in the bottom via 13 having the bottom. 0.5 micrometer of base copper plating was performed to the whole surface of the package substrate 1 for mounting.

다음으로, 하지 구리도금 표면에, 자외선경화형 에칭레지스트용 드라이 필름 H-W475(히다치가세이고쿄가부시키가이샤제, 상품명)를 라미네이터로, 압력 0.2MPa, 온도110℃, 속도 1.5m/분인 조건에서 임시압착하고, 이어서, 그 상면에 네가티브형 마스크를 붙여서, 자외선을 노광하여, 도금이 불필요한 부분(캐비티부(9) 안 및 베이스층(6)의 접속단자B(15)를 갖는 면)에 도금레지스트(43)를 형성했다. 또한, 캐비티부(9)는, 전기 구리도금 되지않도록, 도금 레지스트(43)로 완전히 피복했다. 다음으로, 황산 구리도금으로 온도 30℃, 전류밀도 1.5A/d㎡, 시간 60분인 조건에서, 도금두께 20㎛의 전기 구리도금(41)에 의해 금속피복(18)을 형성하고, 이어서, 3질량% 수산화나트륨 수용액을 분무하여 도금레지스트(43)의 박리제거를 행했다.Next, on the base copper plating surface, dry film H-W475 (made by Hitachi Chemical Co., Ltd., brand name) for UV cure etching resists is a laminator, and it is the conditions of pressure 0.2MPa, temperature 110 degreeC, and speed 1.5m / min. Is temporarily bonded to the upper surface, and then a negative mask is attached to the upper surface thereof, and the ultraviolet rays are exposed to the portions where plating is unnecessary (inside the cavity 9 and the surface having the connection terminals B 15 of the base layer 6). The plating resist 43 was formed. The cavity portion 9 was completely covered with the plating resist 43 so as not to be electroplated. Next, the metal coating 18 is formed by the electroplating copper plating 41 of 20 micrometers of plating thickness on the conditions which are 30 degreeC, current density 1.5A / dm <2>, and time 60 minutes with copper sulfate plating, and then 3 The plating solution 43 was peeled off by spraying the mass% sodium hydroxide aqueous solution.

다음으로, 황산과수 에칭조성으로 이루어지는 코브라 에칭액(에바라유지라이트가부시키가이샤제, 상품명)을 사용하여, 캐비티부(9) 안에 석출된 하지 구리도금(도시하지 않음.)을, 온도50℃, 스프레이 압력 0.2MPa, 속도 1.0m/분인 조건에서 에칭하고, 이어서, 과망간산나트륨 수용액, 온도 85℃로 15분간인 조건에서 촉매의 제거를 행했다.Subsequently, a base copper plating (not shown) deposited in the cavity portion 9 was prepared by using a cobra etching solution (trade name, manufactured by Ebara Oil Light Co., Ltd.) composed of sulfuric acid permeate etching composition. Etching was carried out under the conditions of 0 ° C. and a spray pressure of 0.2 MPa and a speed of 1.0 m / min, and then the catalyst was removed under a condition of 15 minutes at an aqueous sodium permanganate solution and a temperature of 85 ° C.

다음으로, 반도체소자 탑재용 패키지 기판(1)의 바닥을 갖는 비아(13)(구멍직경φ약 0.2mm, 깊이 약 0.25mm) 안에, 도전수지(17)로서 AE1244(타츠타덴센가부시키가이샤제, 상품명)를 스크린인쇄법으로 충전했다. 스크린인쇄에는, 바닥을 갖는 비아(13) 안으로의 기포의 잔류를 없애기 위해, 진공인쇄장치 VE500(토레이 엔지아링 가부시키가이샤제, 상품명)을 사용했다. 충전한 도전수지(17)를 완전경화하기 위해, 반도체소자 탑재용 패키지 기판(1) 전체를 110℃로 15분 가열하고, 170℃로 60분 더 가열했다. 이때, 도전수지(17)는, 바닥을 갖는 비아(13)의 입구의 랜드패턴보다도 튀어나온 상태이었다.Next, in the via 13 (hole diameter phi about 0.2 mm, depth about 0.25 mm) having a bottom of the package substrate 1 for mounting a semiconductor element, AE1244 (manufactured by Tatsuta Densen Co., Ltd.) as the conductive resin 17 was formed. , Brand name) was screen-filled. In screen printing, vacuum printing apparatus VE500 (Toray Engineering Co., Ltd. make, brand name) was used, in order to remove the residue of the bubble in the bottomed via 13. In order to completely harden the filled conductive resin 17, the whole package substrate 1 for semiconductor element mounting was heated at 110 degreeC for 15 minutes, and was further heated at 170 degreeC for 60 minutes. At this time, the conductive resin 17 protruded more than the land pattern at the inlet of the bottomed via 13.

다음으로, 버프연마기(가부시키가이샤 이시이히요키제)를 사용하여, 바닥을 갖는 비아(13)의 입구의 전기 구리도금(41)의 표면이 노출되고, 도전수지(17)와 전기 구리도금(41)이 평활하게 되기까지 연마했다. 사용한 버프롤의 번수는, 600번, 800번, 1000번을 조합해서 사용했다. 버프롤로서는, 구멍메움수지 연마용의 JP버프몬스터 V3/V3-D2(쟈브로고쿄제, 상품명)를 사용했다. 또한, 연마전류는 1.2A이었다.Next, using a buffing machine (manufactured by Ishihihiki Co., Ltd.), the surface of the electric copper plating 41 at the inlet of the bottomed via 13 is exposed, and the conductive resin 17 and the electric copper plating ( 41) polished until smooth. The number of times of the used buffing roll was used combining 600, 800, and 1000 times. As the buff roll, JP buff monster V3 / V3-D2 (manufactured by Jabrogokyo Co., Ltd.) for hole filling resin polishing was used. In addition, the polishing current was 1.2 A.

다음으로, 전기 구리도금(41)표면에, 자외선경화형 에칭레지스트용 드라이필름 H-W475(히다치가세이고쿄가부시키가이샤제, 상품명)를 라미네이터로, 압력 0.2MPa, 온도 110℃, 속도 1.5m/분인 조건에서 임시압착하고, 이어서, 그 상면에 네가티브형 마스크를 붙여합치고, 자외선으로 노광하여, 도금이 불필요한 부분에 도금레지스트(43)를 형성했다. 또한, 캐비티부(9) 안의 와이어 본드단자(12)와 접속단자B(15)는, 도금되도록 하기 위해, 도금레지스트(43)로는 피복하지 않았다.Next, on the surface of electric copper plating 41, dry film H-W475 (made by Hitachi Chemical Co., Ltd., brand name) for ultraviolet curing type etching resists by a laminator, pressure 0.2MPa, temperature 110 degreeC, speed 1.5m. Temporary compression was carried out under the condition of / min. Then, a negative mask was attached to the upper surface thereof, and then exposed to ultraviolet light to form a plating resist 43 in a portion where plating was unnecessary. In addition, the wire bond terminal 12 and the connection terminal B 15 in the cavity portion 9 were not covered with the plating resist 43 so as to be plated.

다음으로, 연마 후의 도전수지(17) 상에 촉매를 부여하거나, 데스메어처리를 행하지 않고, 직접 무전해 도금에 의해 금속피막(16)을 형성했다. (도전수지(17) 이외의 부분은, 도시를 생략했다). 구체적으로는, 일반적으로 무전해 도금의 전처리로 행해지는 탈지(脫脂)나 소프트에칭, 산(酸)세정을 행한 후, 무전해 니켈도금액 NiPS100(히다치가세이고쿄가부시키가이샤제, 상품명)을 사용하여, 액온도 85℃로, 시간 20분인 조건에서, 침지(浸漬)처리를 행하여, 니켈도금을 5㎛석출시키고, 치환 금도금액 HGS-500(히다치가세이고쿄가부시키가이샤제, 상품명)에 온도 80℃로, 시간 10분인 조건으로 더 침지처리하고, 환원형의 무전해 금도금액인 HGS-2000(히다치가세이고쿄가부시키가이샤제, 상품명)에, 액온 65℃로, 시간 20분인 조건에서, 금도금을 0.5㎛의 두께로 석출시켰다. 이것에 의해, 반도체소자 탑재용 패키지 기판(1)의 한쪽 면에 설치된 접속단자A(14), 다른쪽 면에 설치된 접속단자B(15) 및 캐비티부(9) 안의 와이어 본드단자(12)(접속단자C(27)를 갖는 경우는 접속단자C(27)를 포함한다)의 표면에, 땜납볼 접속과 와이어 본드접속을 위한 니켈?금도금층을 형성했다. 또한, 이렇게 도전수지(17) 상에 금속피막(16)을 형성함과 동시에, 캐비티부(9) 안에 노출한 베이스층(6) 상의 와이어 본드단자(12)가 되는 전기 구리도금(41) 상, 및 접속단자B(15) 상에도, 도전수지(17) 상과 마찬가지로, 니켈도금과 금도금을 행했다(도시하지 않음).Next, the metal film 16 was formed by electroless plating directly, without imparting a catalyst or performing a desmere treatment on the conductive resin 17 after polishing. (Parts other than the conductive resin 17 have not shown in the drawing). Specifically, after degreasing, soft etching, and acid washing generally performed by pretreatment of electroless plating, an electroless nickel plating solution NiPS100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) Using a solution temperature of 85 ° C., a immersion treatment was carried out under a condition of 20 minutes to precipitate a nickel plating solution having a thickness of 5 μm, and the replacement gold plating solution HGS-500 (manufactured by Hitachi Chemical Co., Ltd.) ) At 80 ° C. and further immersed under conditions of 10 minutes, and at a liquid temperature of 65 ° C. for HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced electroless gold plating solution. Under the condition of powdering, gold plating was deposited to a thickness of 0.5 mu m. Thereby, the connection terminal A 14 provided in one side of the package substrate 1 for semiconductor element mounting, the connection terminal B 15 provided in the other side, and the wire bond terminal 12 in the cavity 9 ( In the case of having the connection terminal C 27, a nickel-plated layer for solder ball connection and wire bond connection was formed on the surface of the connection terminal C 27). In addition, the metal film 16 is formed on the conductive resin 17, and at the same time, on the electric copper plating 41, which becomes the wire bond terminal 12 on the base layer 6 exposed in the cavity 9. Nickel plating and gold plating were also performed on the connection terminal B 15 and the conductive resin 17 on the connection terminal B 15 (not shown).

다음으로, 자외선경화형 에칭레지스트용 드라이필름 H-W475(히다치가세이고쿄가부시키가이샤제, 상품명)를 라미네이터로, 압력 0.2MPa, 온도 110℃, 속도 1.5m/분인 조건에서 임시압착하고, 이어서 그 상면에 네가티브형 마스크를 붙이고, 자외선으로 노광하여, 회로를 소부하고, 1질량%의 탄산나트륨수용액으로 현상하여, 에칭레지스트를 형성하고, 그 에칭레지스트가 없는 구리부분을 스프레이 분무에 의해, 염화 제2구리, 염산, 황산과수의 조성으로 이루어지는 염화 제2구리 에칭액으로 압력 0.2MPa, 속도 3.5m/분인 조건에서, 회로를 형성하고, 이어서 3질량% 수산화나트륨 수용액을 분무하여 에칭레지스트 박리제거를 행했다. 이것에 의해, 접속단자A(14)를 포함하는 회로를 형성했다. 이 캐비티층(5)의 접속단자A(14)의 직경은 0.25mm, 피치는 0.4mm이고, 베이스층(6)의 접속단자B(15)의 직경 0.3mm, 피치 0.5mm보다도 작다.Next, the dry film H-W475 (made by Hitachi Chemical Co., Ltd., brand name) for UV cure etching resists was temporarily pressed by the laminator on the conditions of the pressure of 0.2 MPa, the temperature of 110 degreeC, and the speed of 1.5 m / min. A negative mask was attached to the upper surface, exposed to ultraviolet light, the circuit was baked, developed with a 1% by mass aqueous sodium carbonate solution to form an etching resist, and the copper portion without the etching resist was sprayed to form a chloride agent. A cupric chloride etching solution composed of copper, hydrochloric acid, and sulfuric acid fruit water is used to form a circuit under conditions of a pressure of 0.2 MPa and a speed of 3.5 m / min, followed by spraying with a 3 mass% sodium hydroxide aqueous solution to remove the etching resist. Done. As a result, a circuit including the connection terminal A 14 was formed. The diameter of the connecting terminal A 14 of the cavity layer 5 is 0.25 mm and the pitch is 0.4 mm, which is smaller than the diameter of the connecting terminal B 15 of the base layer 6 and 0.3 mm of the pitch 0.5 mm.

다음으로, 반도체소자 탑재용 패키지 기판(1)의 양면에, 액상레지스트인 PSR-4000(다이요잉키세이조가부시키가이샤제, 상품명)을 인쇄하여, 80℃, 20분간 건조 후, 그 상면에 네가티브형 마스크를 붙이고, 자외선으로 노광하고, 1.5질량% 탄산나트륨 수용액으로 더 현상하고, 자외선 1J/㎠의 조사에 의해 한층 더 경화를 행하고, 150℃에서 60분 건조하여 솔더레지스트(23)를 형성했다. 이 솔더레지스트(23)는, 캐비티층(5) 표면측(상면측)에서는, 접속단자A(14)와 동등한 높이이고, 베이스층(6)의 표면측(하면측)에서는, 접속단자B(15)와 동등한 높이이다.Next, PSR-4000 (manufactured by Daiyo Inky Chemical Co., Ltd., trade name), which is a liquid resist, was printed on both surfaces of the package substrate 1 for semiconductor element mounting, dried at 80 ° C. for 20 minutes, and then negative on the upper surface thereof. A mold mask was affixed, it was exposed by ultraviolet-ray, it developed further with 1.5 mass% sodium carbonate aqueous solution, it hardened further by irradiation of 1J / cm <2> of ultraviolet rays, it dried at 150 degreeC for 60 minutes, and formed the soldering resist 23. The solder resist 23 is at the same height as the connection terminal A 14 at the surface side (upper surface side) of the cavity layer 5, and at the surface side (lower surface side) of the base layer 6. It is the same height as 15).

[반도체 패키지의 제작][Production of Semiconductor Package]

다음으로, 도 5에 나타낸 바와 같이, 반도체소자(2)를, 반도체소자 탑재용 패키지 기판(1)의 캐비티부(9) 안에, 다이본딩 필름(도시하지 않음)을 사용하여 고정한 후, 이 반도체소자(2) 위에, 하나 더 반도체소자(2)를 다이본딩 필름을 사용하여 고정했다. 그 후, 상단 및 하단의 반도체소자(2)와 반도체소자 탑재용 패키지 기판(1)의 와이어 본드단자(12)를 본딩와이어(4)로 접속했다. 이때, 본딩와이어(4)를 포함하는 상단의 반도체소자(2)의 최상부는, 반도체소자 탑재용 패키지 기판(1)의 접속단자A(14)와 동등 이하의 높이이었다.Next, as shown in FIG. 5, after fixing the semiconductor element 2 in the cavity part 9 of the package substrate 1 for semiconductor element mounting using a die-bonding film (not shown), this semiconductor The semiconductor element 2 was further fixed on the element 2 using the die-bonding film. Thereafter, the upper and lower semiconductor elements 2 and the wire bond terminals 12 of the semiconductor element mounting package substrate 1 were connected with the bonding wires 4. At this time, the uppermost part of the semiconductor element 2 of the upper end containing the bonding wire 4 was equal to or less than the connection terminal A 14 of the package element 1 for semiconductor element mounting.

다음으로, 트랜스퍼몰딩에 의해, 캐비티부(9) 안에 봉지제(3)를 충전하여 형성하고, 반도체 패키지(36)를 제작했다. 이때, 봉지제(3)의 최상부는, 반도체소자탑재용 패키지 기판(1)의 접속단자A(14)와 동등 이하의 높이(접속단자A(14)보다도 약 0.1mm 위쪽으로 튀어나온 정도)이다.Next, the sealing agent 3 was filled in the cavity part 9 by transfer molding, and the semiconductor package 36 was produced. At this time, the uppermost part of the encapsulant 3 has a height equal to or less than the connection terminal A 14 of the package substrate 1 for semiconductor element mounting (a degree that protrudes about 0.1 mm upward from the connection terminal A 14). .

[PoP의 제작][Production of PoP]

다음으로, 접속단자A(14)에 땜납페이스트를 인쇄하고, 도 6에 나타낸 바와 같이, 상기 실시예의 반도체 패키지(36)를 하부 패키지(35)로서 사용하고, 상부 패키지(34)의 접속단자와 위치맞춤한 후, 리플로우에 의해 반도체 패키지끼리를 접합했다. 이때, 반도체소자 탑재용 패키지 기판(1)의 캐비티부(9) 안에 봉지제(3)의 거의 전체가 수납되어, 거의 튀어 나오지 않으므로, 반도체 패키지끼리의 접합을 위한 땜납볼 직경은, 봉지제(3)의 높이를 고려할 필요가 없다. 이 때문에, 땜납볼 직경은 φ0.3mm이하로 접합이 가능하였다. 이 결과, 하부 패키지(35)의 봉지제(3)의 최상부가, 접속단자A(14) 위에 설치된 땜납볼(φ 0.3mm)의 1/3이하의 높이가 되는 상태에서(즉, 단자간 거리(44)의 1/3이하의 높이인 0.1mm이하 정도로), 상부 패키지(34)를 접합하는 것이 가능하였다.Next, a solder paste is printed on the connection terminal A 14, and as shown in FIG. 6, the semiconductor package 36 of the embodiment is used as the lower package 35, and the connection terminal of the upper package 34 After the alignment, the semiconductor packages were bonded to each other by reflow. At this time, almost all of the encapsulant 3 is accommodated in the cavity 9 of the package substrate 1 for semiconductor element mounting and hardly protrudes. Therefore, the solder ball diameter for joining the semiconductor packages is determined by the encapsulant ( It is not necessary to consider the height of 3). For this reason, the solder ball diameter was able to join below 0.3 mm. As a result, in the state where the uppermost part of the sealing agent 3 of the lower package 35 becomes a height equal to or less than 1/3 of the solder balls φ 0.3 mm provided on the connection terminal A 14 (that is, the distance between the terminals) It was possible to join the upper package 34 to about 0.1 mm or less, which is the height of 1/3 or less of (44).

(실시예 2)(Example 2)

[캐비티층의 제작][Production of cavity layer]

캐비티재(7)로서 사용하는 MCL-E679F(히다치가세이고쿄가부시키가이샤제, 상품명)의 양면에 붙이는 동박의 두께를 9㎛로 했다. 또한, 캐비티재(7)에 임시부착하는 접착시트 AS2600(히다치가세이고쿄가부시키가이샤제, 상품명)의 두께를, 10㎛로 변경했다. 이외에는, 실시예1과 마찬가지로 하여 캐비티층(5)을 제작했다. 이때의 내층회로(19)의 두께는, 9㎛이었다.The thickness of the copper foil stuck to both surfaces of MCL-E679F (made by Hitachi Chemical Co., Ltd., brand name) used as the cavity material 7 was 9 micrometers. In addition, the thickness of the adhesive sheet AS2600 (made by Hitachi Chemical Co., Ltd., brand name) temporarily attached to the cavity material 7 was changed to 10 micrometers. A cavity layer 5 was produced in the same manner as in Example 1 except for the above. The thickness of the inner layer circuit 19 at this time was 9 µm.

[베이스층의 제작][Production of base layer]

실시예1과 마찬가지로 제작했다.It produced similarly to Example 1.

[반도체소자 탑재용 패키지 기판의 제작][Production of Package Substrate for Semiconductor Device Loading]

실시예 1과 마찬가지로 하여, 캐비티층(5)과 베이스층(6)을 적층하고, 반도체소자 탑재용 패키지 기판을 제작했다. 이때 접착제(8)가 유동하지만, 캐비티재(7) 상의 관통공A(24)의 주위에 설치한 환상링이, 관통공A(24)의 주위를 완전히 둘러싼 댐으로서 작용하므로, 접착제(8)가 관통공A(24) 내측으로 유동하는 것을 억제할 수 있었다. 관통공A(24) 내측으로의 접착제의 유동은, 관통공A(24)의 내벽에서 접속패드(11) 상으로의 배어 나오는 양(배어나온 거리)으로서 관찰할 수가 있고, 본 실시예에서는, 한쪽 편에서 20㎛이하의 레벨이었다. 또한, 내층회로(19)가 두께(9㎛)를 갖기 때문에, 내층회로(19)에 대응하는 부분의 접착제(8)는, 그 이외의 부분과 비교하여, 두께가 얇게 형성된다. 이 실시예 1에서는, 캐비티제(7) 상의 내층회로(19)와 베이스층(6)의 감광성수지(10) 사이에 끼워지는 부분의 접착제의 두께는, 0.5 ~ 2㎛이고, 이들에 끼워지지 않는 부분에 비하여 얇게 되었다.The cavity layer 5 and the base layer 6 were laminated | stacked similarly to Example 1, and the package substrate for semiconductor element mounting was produced. Although the adhesive agent 8 flows at this time, since the annular ring provided around the through hole A 24 on the cavity material 7 acts as a dam which completely encloses the periphery of the through hole A 24, the adhesive agent 8 is carried out. Was prevented from flowing inside the through hole A 24. The flow of the adhesive to the inside of the through hole A 24 can be observed as the amount of bleeding out from the inner wall of the through hole A 24 onto the connection pad 11 (in the present embodiment). It was a level of 20 micrometers or less on one side. In addition, since the inner layer circuit 19 has a thickness (9 µm), the adhesive 8 in the portion corresponding to the inner layer circuit 19 is formed thinner than the other portions. In Example 1, the thickness of the adhesive at the portion sandwiched between the inner layer circuit 19 on the cavity agent 7 and the photosensitive resin 10 of the base layer 6 is 0.5 to 2 占 퐉, and is not fitted therewith. It became thin compared to the part which is not.

(실시예 3)(Example 3)

[캐비티층의 제작][Production of cavity layer]

캐비티재(7)로서 사용하는 MCL-E679F(히다치가세이고쿄가부시키가이샤제, 상품명)의 양면에 붙이는 동박의 두께를, 실시예1과 마찬가지로 9㎛, 12㎛, 18㎛로 했다. 또한, 캐비티재(7)에 임시부착하는 접착시트 AS2600(히다치가세이고쿄가부시키가이샤제, 상품명)의 두께를, 50㎛로 변경했다. 이외에는, 실시예1과 마찬가지로 하여 캐비티층(5)을 제작했다. 이때의 내층회로(19)의 두께는, 9㎛, 12㎛, 18㎛이었다.The thickness of the copper foil stuck to both surfaces of MCL-E679F (made by Hitachi Chemical Co., Ltd., brand name) used as the cavity material 7 was 9 micrometers, 12 micrometers, and 18 micrometers similarly to Example 1. In addition, the thickness of the adhesive sheet AS2600 (made by Hitachi Chemical Co., Ltd., brand name) temporarily attached to the cavity material 7 was changed to 50 micrometers. A cavity layer 5 was produced in the same manner as in Example 1 except for the above. The thickness of the inner layer circuit 19 at this time was 9 µm, 12 µm, and 18 µm.

[베이스층의 제작][Production of base layer]

실시예 1과 마찬가지로 제작했다.It produced similarly to Example 1.

[반도체소자 탑재용 패키지 기판의 제작][Production of Package Substrate for Semiconductor Device Loading]

실시예1과 마찬가지로 하여, 캐비티층(5)과 베이스층(6)을 적층하고, 반도체소자 탑재용 패키지 기판을 제작했다. 이때 접착제(8)가 유동하지만, 캐비티재(7) 상의 관통공A(24)의 주위에 설치한 환상링이, 관통공A(24)의 주위를 완전히 둘러싼 댐으로서 작용하므로, 접착제(8)가 관통공A(24) 내측으로 유동하는 것을 억제할 수가 있었다. 관통공A(24) 내측으로의 접착제의 유동은, 관통공(A24)의 내벽으로부터 접속패드(11) 상으로의 배어 나오는 양(배어나온 거리)으로서 관찰할 수 있고, 본 실시예에서는, 한쪽 편에서 50㎛이하의 레벨이었다. 또한, 내층회로(19)가 두께(9㎛)를 갖기 때문에, 내층회로(19)에 대응하는 부분의 접착제는(8), 그외의 부분과 비교하여, 두께가 얇게 형성된다. 이 실시예 1에서는, 캐비티재(7) 상의 내층회로(19)와 베이스층(6)의 감광성수지(10) 사이에 끼워지는 부분의 접착제의 두께는, 2 ~ 7㎛이고, 이들에 끼워지지않는 부분에 비하여 얇게 되었다.In the same manner as in Example 1, the cavity layer 5 and the base layer 6 were laminated to prepare a package substrate for mounting a semiconductor element. Although the adhesive agent 8 flows at this time, since the annular ring provided around the through hole A 24 on the cavity material 7 acts as a dam which completely encloses the periphery of the through hole A 24, the adhesive agent 8 is carried out. Flow to the inside of the through hole A 24 could be suppressed. The flow of the adhesive to the inside of the through hole A 24 can be observed as the amount of bleeding out from the inner wall of the through hole A24 onto the connection pad 11. In this embodiment, one side It was a level below 50 micrometers in a side. In addition, since the inner layer circuit 19 has a thickness (9 µm), the adhesive of the portion corresponding to the inner layer circuit 19 (8) is thinner than the other portions. In the first embodiment, the thickness of the adhesive at the portion sandwiched between the inner circuit 19 on the cavity material 7 and the photosensitive resin 10 of the base layer 6 is 2 to 7 탆, It became thin compared to the part which is not.

(비교예1)(Comparative Example 1)

[캐비티층의 제작][Production of cavity layer]

캐비티층(5)의 회로 형성시에, 한쪽 면에 대해서는, 관통공A(40)의 주위에 내층회로(19)를 남기지 않도록 형성했다. 다른쪽 면, 즉 접속단자A(14)를 형성하는 면에 대해서는, 거의 전면에 동박(40)을 남겼다. 이외에는, 실시예1과 마찬가지로 하여 캐비티재를 제작했다.At the time of circuit formation of the cavity layer 5, about one surface, it formed so that the inner layer circuit 19 might not be left around the through-hole A40. About the other surface, ie, the surface which forms the connection terminal A 14, the copper foil 40 was left in almost the whole surface. A cavity material was produced in the same manner as in Example 1 except for the above.

[베이스층의 제작][Production of base layer]

실시예1과 마찬가지로 제작했다.It produced similarly to Example 1.

[반도체소자 탑재용 패키지 기판 및 반도체소자 탑재용 패키지의 제작][Production of Package Board for Semiconductor Device and Package for Semiconductor Device]

실시예1과 마찬가지로 하여, 캐비티층(5)과 베이스층(6)을 적층하여, 반도체소자 탑재용 패키지 기판을 제작했다. 이때 접착제(8)가 유동하지만, 캐비티재(7) 상의 관통공A(24)의 주위에는, 환상링이 설치되어 있지 않기 때문에, 접착제(8)의 관통공A(24) 내층으로의 유동이 실시예에 비하여 컸다. 관통공A(24)의 내벽으로부터 접속패드(11) 상으로의 배어 나오는 양(배어나온 거리)은, 본 비교예에서는, 한쪽에서 80㎛이상의 레벨이었다. 또한, 관통공A(24)의 주위에는, 내층회로(19)를 설치하지 않는다. 이 때문에, 관통공A(24)의 주위 근방의 접착제(8)의 두께는, 유동에 의해 그 이외의 부분보다 얇게는 되지만, 내층회로(19)에 대응하는 부분보다도 두껍게 형성된다. 이 비교예1에서는, 관통공A(24)의 주위에 있어서, 캐비티재(7)와 베이스층(6)의 감광성수지(10) 사이에 끼워지는 부분의 접착제의 두께는, 10㎛이상이었다.The cavity layer 5 and the base layer 6 were laminated | stacked similarly to Example 1, and the package substrate for semiconductor element mounting was produced. Although the adhesive agent 8 flows at this time, since the annular ring is not provided in the circumference | surroundings of the through-hole A 24 on the cavity material 7, the flow to the inner layer of the through-hole A 24 of the adhesive agent 8 It was larger than the example. In the present comparative example, the amount of bleeding out from the inner wall of the through hole A 24 onto the connection pad 11 was a level of 80 µm or more on one side. In addition, the inner layer circuit 19 is not provided around the through hole A 24. For this reason, although the thickness of the adhesive agent 8 of the periphery vicinity of the through-hole A24 becomes thinner than the other part by flow, it is formed thicker than the part corresponding to the inner layer circuit 19. As shown in FIG. In the comparative example 1, the thickness of the adhesive agent in the part which fits between the cavity material 7 and the photosensitive resin 10 of the base layer 6 around the through-hole A24 was 10 micrometers or more.

(비교예2)(Comparative Example 2)

[캐비티층의 제작][Production of cavity layer]

실시예1과 마찬가지로 하여 캐비티층(5)을 작성했다.In the same manner as in Example 1, the cavity layer 5 was prepared.

[베이스층의 제작][Production of base layer]

실시예 1과 마찬가지로 하여 베이스층(6)을 제작했다.In the same manner as in Example 1, the base layer 6 was produced.

[반도체소자 탑재용 패키지 기판 및 반도체소자 탑재용 패키지의 제작][Production of Package Board for Semiconductor Device and Package for Semiconductor Device]

층간접속(31)을 형성하는 때에, 바닥을 갖는 비아(13) 안으로 스루홀 도금만을 행하고, 도전수지(17)를 충전하지 않았다. 또한, 이 때문에, 바닥을 갖는 비아(13)의 바로 위가 아닌 위치에 접속단자A(14)를 형성한 것 이외에는, 실시예1과 마찬가지이다.When the interlayer connection 31 was formed, only through hole plating was performed into the via 13 having a bottom, and the conductive resin 17 was not filled. For this reason, it is the same as that of Example 1 except having formed the connection terminal A14 in the position which is not directly over the via 13 which has a bottom.

실시예 및 비교예에 대해서의 내층회로(19)의 두께, 내층회로(19)에 대응하는 부분의 접착제(8)의 두께, 관통공A(24) 안으로의 접착제(8)의 배어 나오는 양과 접속신뢰성 시험은, 이하와 같이 행했다.The thickness of the inner layer circuit 19, the thickness of the adhesive agent 8 in the portion corresponding to the inner layer circuit 19, the amount of bleeding of the adhesive agent 8 into the through hole A 24 and the connection with respect to the Examples and Comparative Examples. The reliability test was performed as follows.

[내층회로(19)의 두께, 내층회로(19)에 대응하는 부분의 접착제(8)의 두께의 측정][Measurement of the thickness of the adhesive layer 8 in the portion corresponding to the thickness of the inner layer circuit 19 and the inner layer circuit 19]

바닥을 갖는 비아(13) 근방의 단면을, 광학현미경으로 관찰하여 행했다.The cross section of the vicinity of via 13 which has a bottom was observed and performed with the optical microscope.

[관통공A(24) 안으로의 접착제(8)의 배어 나오는 양][The amount of bleeding of the adhesive 8 into the through hole A 24]

관통공A(24) 안으로의 접착제(8)의 배어 나오는 양은, 관통공A(24)의 내벽으로부터 접속패드(11) 상으로의 배어 나오는 양(배어나온 거리)으로 해서 관찰할 수 있다. 이때문에, 캐비티층(5)과 베이스층(6)을 적층한 후, 관통공A(24)의 입구측에서, 관통공A(24)의 저부를 광학현미경으로 관찰하여 측정했다.The amount of bleeding of the adhesive agent 8 into the through hole A 24 can be observed as the amount of bleeding out from the inner wall of the through hole A 24 onto the connection pad 11. For this reason, after laminating the cavity layer 5 and the base layer 6, the bottom part of the through-hole A24 was observed and measured by the optical microscope from the inlet side of the through-hole A24.

[접속신뢰성 시험][Connection reliability test]

각 실시예 및 비교예에서 제작한 반도체소자 탑재용 패키지 기판(1)을 사용하여, -55 ~ 125℃의 냉열사이클시험(각각 15분)을 행하고, 100사이클 마다 바닥을 갖는 비아(13)의 층간접속(31)을 통해 접속저항을 측정하고, 1000사이클 후의 접속불량의 유무를 확인했다. 접속저항이, 초기값에 비하여 10%이상 증가한 것을 불합격(×)으로 했다.Using the semiconductor device mounting package substrate 1 produced in each of Examples and Comparative Examples, a cold cycle test (15 minutes each) of -55 to 125 ° C was carried out, and the via 13 having a bottom every 100 cycles was used. Connection resistance was measured through the interlayer connection 31, and the presence or absence of the connection failure after 1000 cycles was confirmed. An increase of 10% or more in connection resistance compared to the initial value was regarded as fail (x).

표 1에 그 결과를 나타낸다. 실시예 1에서 3에서는, 캐비티층(5)에 환상링으로 설치된 내층회로(19)와, 바닥을 갖는 비아(13) 내벽에 형성된 금속피복(18)의 내층접속(20)이 형성된다. 또한, 관통공A(24)의 주위에 환상링으로 형성된 내층회로(19)에 대응하는 부분(관통공A(24)의 주위 근방)에서, 접착제(8)의 두께는 얇고, 배어 나오는 양도 작다. 이 때문에, 바닥을 갖는 비아(13)로서의 접속 신뢰성은 합격(○)이었다. 비교예 1은, 캐비티층(5)의 관통공A의 주위에 내층회로(19)를 설치하지 않아서, 내층회로(19)와 바닥을 갖는 비아(13) 내벽에 형성한 금속피복(18)의 내층접속(20)이 형성되지 않는다. 또한, 관통공A(24)의 주위 근방의 접착제의 두께는 비교적 두껍고, 열팽창계수가 비교적 큰 접착제(8)의 영향을 억제할 수 없다. 이 때문에, 비교예 1은, 접속신뢰성이 불합격(×)이었다. 바닥을 갖는 비아(13) 안으로 환상링으로 설치한 내층회로(19)와, 바닥을 갖는 비아(13) 내벽에 형성한 금속피복(18)의 내층접속(20)을 형성하지만, 도전수지(17)를 충전하지 않은 비교예 2도, 접속신뢰성이 불합격(×)이었다.The results are shown in Table 1. In Embodiments 1 to 3, the inner layer circuit 19 provided on the cavity layer 5 by an annular ring and the inner layer connection 20 of the metal coating 18 formed on the inner wall of the via 13 having the bottom are formed. In addition, in the part corresponding to the inner layer circuit 19 formed by the annular ring around the through hole A 24 (in the vicinity of the periphery of the through hole A 24), the thickness of the adhesive agent 8 is thin and the amount of bleeding is small. . For this reason, the connection reliability as the bottomed via 13 was pass (circle). In Comparative Example 1, the inner layer circuit 19 was not provided around the through hole A of the cavity layer 5, and the metal coating 18 formed on the inner wall of the via 13 having the inner layer circuit 19 and the bottom was formed. The inner layer connection 20 is not formed. In addition, the thickness of the adhesive near the periphery of the through hole A 24 is relatively thick, and the influence of the adhesive 8 having a relatively large thermal expansion coefficient cannot be suppressed. For this reason, in Comparative Example 1, connection reliability was failed (x). Although the inner layer circuit 19 provided with the annular ring in the bottom via 13 and the inner layer connection 20 of the metal coating 18 formed in the inner wall of the via 13 with bottom are formed, the conductive resin 17 ) Was also failed (x).

Figure 112010071987287-pct00001
Figure 112010071987287-pct00001

1…반도체소자 탑재용 패키지 기판, 2…반도체소자, 3…봉지제, 4…본딩 와이어, 5… 캐비티층, 6…베이스층, 7…캐비티재, 8…접착제, 9…캐비티부, 10…감광성수지층, 11…접속패드, 12…와이어 본드 단자, 13… 바닥을 갖는 비아, 14…접속단자A, 15…접속단자B, 16…금속피막, 17…도전수지, 18…금속피복, 19…내층회로, 20…내층접속, 21…베이스재, 22…컨포멀마스크, 23…솔더레지스트, 24…관통공A, 25…개구, 26…레이저구멍, 27…접속단자C, 28…베이스재a, 29…베이스재b, 30…베이스재c, 31…층간접속, 32…상부 기판, 33…하부 기판, 34...상부 패키지, 35…하부 패키지, 36…반도체 패키지, 37…접속단자, 38…땜납볼, 39…관통공B, 40…동박, 41…도금, 42…층간접속, 43…도금레지스트, 44…단자간 거리One… Package substrate for semiconductor element mounting; Semiconductor element, 3... Sealing agent, 4... Bonding wire, 5... Cavity layer, 6... Base layer, 7... Cavity material, 8... Adhesive, 9... Cavity part, 10... Photosensitive resin layer, 11... Connection pad, 12.. Wire bond terminals, 13... . Bottom via, 14... Connection terminal A, 15... Connection terminal B, 16... Metal film 17... Conductive resin, 18... Metal coating, 19... Inner circuit, 20... Inner layer connection, 21... Base material, 22... Conformal mask, 23... Solder resist, 24... Through hole A, 25... Opening 26. Laser hole 27. Connection terminal C, 28... Base material a, 29... Base material b, 30... Base material c, 31... Interlayer connection, 32... Upper substrate, 33... Lower substrate, 34.. Top package, 35. Bottom package, 36... Semiconductor package, 37... 38,. Solder ball, 39... Through hole B, 40... Copper foil, 41... Plating, 42... Interlayer connection, 43... Plating resist, 44... Distance between terminals

Claims (7)

캐비티재와 접착제를 구비하고, 이들을 관통하는 개구 및 관통공을 갖는 캐비티(cavity)층과, 상기 접착제에 의해 상기 캐비티층에 적층된 베이스(base)층과, 상기 개구에 의해 형성된 캐비티부와, 상기 관통공에 의해 형성된 바닥을 갖는 비아(via)를 갖는 반도체소자 탑재용 패키지 기판에 있어서,
상기 캐비티층에 내층회로가 설치되고,
이 내층회로와 접합하도록, 상기 바닥을 갖는 비아의 내벽에 금속피복이 도금에 의해 형성되고,
상기 바닥을 갖는 비아에 도전수지가 충전되는 반도체소자 탑재용 패키지 기판.A cavity layer having a cavity material and an adhesive, the cavity layer having openings and through holes therethrough, a base layer laminated on the cavity layer by the adhesive, a cavity portion formed by the opening, In the package substrate for mounting a semiconductor device having a via having a bottom formed by the through hole,
An inner circuit is installed in the cavity layer,
In order to bond with this inner layer circuit, a metal coating is formed on the inner wall of the via having the bottom by plating,
A package substrate for mounting a semiconductor device, the conductive resin is filled in the via having the bottom. 제1항에 있어서,
바닥을 갖는 비아가, 캐비티재와 접착제를 관통하여, 베이스층 상의 캐비티층측에 설치되는 접속패드에 이르도록 설치되고,
상기 접속패드와, 상기 캐비티층 상의 베이스층과 반대측에 설치되는 접속단자A를 접속하는 층간접속이 형성되는 반도체소자 탑재용 패키지 기판.The method of claim 1,
A via having a bottom penetrates the cavity material and the adhesive to reach a connection pad provided on the cavity layer side on the base layer.
An interlayer connection for connecting the connection pads and the connection terminals A provided on the side opposite to the base layer on the cavity layer is formed. 제1항 또는 제2항에 있어서,
캐비티층에 설치되는 내층회로가 관통공의 주위에 설치되는 환상링(annular ring)이고,
이 환상링과 바닥을 갖는 비아의 내벽에 형성되는 금속피복이 내층접속을 형성하는 반도체소자 탑재용 패키지 기판.The method according to claim 1 or 2,
The inner layer circuit provided in the cavity layer is an annular ring provided around the through hole,
A semiconductor substrate mounted package substrate, wherein a metal coating formed on the inner wall of the via ring having the annular ring and the bottom forms an inner layer connection. 제1항에 있어서,
캐비티층에 설치되는 내층회로가, 상기 캐비티재 상의 접착제 측에 설치되는 반도체소자 탑재용 패키지 기판.The method of claim 1,
A package substrate for mounting a semiconductor element, wherein an inner layer circuit provided in the cavity layer is provided on the adhesive side on the cavity material. 제1항에 있어서,
캐비티층에 설치되는 접착제의 두께가, 내층회로에 대응하는 부분에서, 내층회로에 대응하지 않는 부분에 비하여 얇은 반도체소자 탑재용 패키지 기판.The method of claim 1,
A package substrate for mounting a semiconductor element, wherein the thickness of the adhesive provided in the cavity layer is thinner than the portion not corresponding to the inner layer circuit in the portion corresponding to the inner layer circuit. 제1항에 있어서,
캐비티층과 베이스층을 적층하기 위한 접착제가 엘라스토머재인 반도체소자 탑재용 패키지 기판.The method of claim 1,
A package substrate for mounting a semiconductor device, wherein the adhesive for laminating the cavity layer and the base layer is an elastomer material. 개구와 관통공과 내층회로를 갖는 캐비티재를 형성하는 공정과,
이 캐비티재에 접착제를 통해서 베이스층을 적층하고, 상기 개구에 의해 캐비티부를, 상기 관통공에 의해 바닥을 갖는 비아를 형성하는 공정과, 상기 바닥을 갖는 비아의 내벽에 금속피복을 형성하고, 이 금속피복과 상기 내층회로와의 내층접속을 형성하는 공정과, 상기 금속피복을 하지(下地)로 하여 상기 바닥을 갖는 비아에 도전수지를 충전하는 공정을 갖는 반도체소자 탑재용 패키지 기판의 제조방법.Forming a cavity material having an opening, a through hole, and an inner layer circuit,
The base layer is laminated to this cavity material through an adhesive agent, and a cavity part is formed by the said opening by the said through-hole, and the metal coating is formed in the inner wall of the via via which the bottom part is formed, A method of manufacturing a package substrate for mounting a semiconductor device, comprising: forming an inner layer connection between a metal coating and the inner layer circuit; and filling a conductive via in the bottom via with the metal coating.
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