JP2003078108A - Semiconductor package board, semiconductor package using the same and its laminate, and method of manufacturing them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package board which is superior in reliability, reduced in thickness and weight, and suitably improved in mounting density, a semiconductor package using the same, its laminate, and methods of manufacturing them. SOLUTION: A semiconductor package board is equipped with a wiring which is supported on an insulating board and electrically connected to a semiconductor chip, a conductive bump mount formed on the wiring, a device hole formed as a semiconductor chip mounting part, penetrating through the insulating board, and an adhesive tape whose base film is formed of resin film, metal foil, paper, cloth, or glass cloth or a combination of them, and a semiconductor package and a semiconductor package laminate are manufactured by the use of the above semiconductor package board, by which the problem is solved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package substrate, a semiconductor package using the same, and a laminated body thereof.
The present invention also relates to a manufacturing method thereof, and particularly to a technique suitable for a high-density semiconductor package.

[0002]

2. Description of the Related Art The number of input / output terminals has increased as the degree of integration of semiconductors has improved. Therefore, a semiconductor package having a large number of input / output terminals is needed. Generally, there are two types of input / output terminals, one type being arranged in a row around the semiconductor package and the other type being arranged not only in the periphery but also inside. Among the former, QFP (Quad Flat Package) is typical. In order to increase the number of terminals, it is necessary to reduce the terminal pitch, but in the area of 0.5 mm pitch or less, advanced technology is required for connection with the motherboard. In the latter case, the array type allows terminal arrangement at a relatively large pitch and is suitable for increasing the number of pins. The conventional array type has a PGA (Pin Grid Arra) with connection pins.
y) was common, but the connection to the motherboard is an insertion type and is not suitable for surface mounting. Therefore, a surface mountable semiconductor package called BGA (Ball Grid Array) has been developed.

Further, along with the miniaturization of electronic equipment, there is an increasing demand for further miniaturization of the semiconductor package size. In order to respond to this miniaturization, the so-called CSP (Chip Siz
e Package) is proposed. This is a package that has a connection portion with the motherboard in the mounting area, not in the peripheral portion of the semiconductor chip. As a specific example, a polyimide film with bumps is adhered to the surface of a semiconductor chip,
After electrical connection is made with the chip and gold wire, epoxy resin etc. is potted and sealed (NIKKEI M
ATERIALS & TECHNOLOGY 94.4, No.140, p18-19) or forming a metal bump on the temporary substrate at a position corresponding to the connection part with the semiconductor chip and the motherboard, and after face-down bonding the semiconductor chip, on the temporary substrate. Transfer Molded (Smallest Flip-Chip-Like Package
CSP; The Second VLSI Packaging Workshop of Japa
n, p46-50, 1994).

As a result of earnest studies, the inventors of the present invention have found that,
As disclosed in Japanese Unexamined Patent Publication No. 0-189820, a plurality of wirings are formed on one surface of an insulating substrate, and the wiring has at least an internal connecting portion for connecting to a semiconductor chip electrode and a semiconductor chip mounting area portion. Has an opening at a location where the wiring of the insulating substrate is formed and at an location where an external connection portion that conducts with the internal connection portion is provided.
At least one through hole (hereinafter referred to as a vent hole) is provided between the wirings in the semiconductor chip mounting area of the insulating substrate, and the semiconductor chip is mounted including the semiconductor chip mounting area portion of the wiring. An insulating film is placed and formed at the location, and the insulating film is a semiconductor package chip support substrate configured to form a hollow portion between the insulating substrate and the vent hole peripheral portion. The manufacturing method is proposed. With this proposal,
It enables the manufacture of small semiconductor packages with excellent reliability by preventing package cracks.

[0005]

However, the above-mentioned semiconductor package has a problem in that it cannot meet the demands for further reduction in thickness, weight and density.

Therefore, the present invention is excellent in reliability and is suitable for further thinning, weight reduction and high density, a semiconductor package substrate using the same, a semiconductor package using the same, and a manufacturing method thereof. The purpose is to provide.

[Means for Solving the Problems]

In order to solve the problems, the present invention provides an insulating base material, a wiring supported by the insulating base material and electrically connected to a semiconductor chip, and a conductive bump mounting portion formed on the wiring. A semiconductor package substrate, comprising at least a device hole formed as a semiconductor chip mounting portion penetrating an insulating base material, and an adhesive tape attached to one surface of the insulating base material. The first feature is that the base film of the adhesive tape is a semiconductor package substrate made of any one of resin film, metal foil, paper, cloth, glass cloth, or a combination thereof.

The semiconductor package substrate having the first characteristic includes a step of forming a wiring electrically connected to the semiconductor chip on the insulating base material and a step of forming a conductive bump mounting portion on the wiring. It is manufactured by a manufacturing method including a step of penetrating the insulating base material to form a device hole, and a step of attaching a tape with an adhesive to one surface of the insulating base material.

In the semiconductor package substrate obtained as described above, an insulating coating and a connecting conductor may be formed on the insulating base material and the wiring as required. When a resin film is used as the base film of the adhesive tape, the resin film may be stretched or
And heat treatment can be applied. According to this treatment, in particular, when problems such as peeling of the adhesive tape and package warpage due to heat shrinkage of the resin film in the heating step such as resin sealing and wire bonding occur, the heat shrinkage is suppressed and the problem is reduced. Since it can be reduced, it is possible to select a resin film such as polyethylene terephthalate that is inexpensive but has a relatively large heat shrinkage rate as the base film.

Furthermore, the present invention provides a semiconductor package substrate having the above-mentioned first characteristic, a semiconductor chip mounted on a tape with an adhesive in a device hole and electrically connected to wiring, and a semiconductor package substrate. The adhesive-attached tape is a sealing resin, including a sealing resin that seals a necessary portion of the adhesive and a conductive bump that is an external connection terminal and is formed on the conductive bump mounting portion formed on the wiring. The second feature is that the semiconductor package is peeled off after sealing the semiconductor chip by.

In the semiconductor package having the second characteristic, the step of mounting the semiconductor chip on the adhesive tape in the device hole, electrically connecting the wiring and the semiconductor chip, and sealing the necessary portion with resin. And a step of peeling the adhesive-attached tape, and a step of forming a conductive bump as an external connection terminal on the conductive bump mounting portion formed on the wiring.

Furthermore, a third feature of the present invention is that the semiconductor package having the second characteristic is laminated in two or more stages, and the semiconductor packages are electrically connected and fixed by conductive bumps. I am trying.
The voids between the semiconductor packages caused by the height of the conductive bumps can be further fixed by resin.

The semiconductor package laminate having the third characteristic is manufactured by a manufacturing method including a step of stacking the semiconductor packages having the second characteristic in two or more stages and conducting and fixing the semiconductor packages with conductive bumps. Is
The method may further include a step of further fixing, with a resin, voids between the semiconductor packages caused by the height of the conductive bumps. Further, when stacking and fixing the semiconductor packages, the semiconductor packages may be stacked and fixed one by one up to the required number of layers, or may be fixed collectively after the required number of layers are laminated.

According to the semiconductor package substrate having the first, second and third characteristics as described above, the semiconductor package using the same and the laminated body thereof, and the manufacturing methods thereof, the semiconductor chip is provided on the adhesive-attached tape. The semiconductor chip can be mounted in the device hole formed by penetrating the insulating base material by mounting the device, fixing it with a resin, and then peeling off the adhesive tape, which is a temporary fixing means. Therefore, the semiconductor package of the present invention and its laminated body are lighter in weight because the device holes are formed and thinner and higher in density because the semiconductor chips are accommodated in the device holes, as compared with the related art.

Further, according to the present invention, since the bottom surface of the semiconductor chip is exposed from the semiconductor package, it is possible to reliably exhaust gas or water vapor generated by reflow or the like when the semiconductor package is mounted on an external substrate to the outside of the package. It is also possible to prevent package cracks.

Furthermore, by stacking the semiconductor packages according to the present invention, it becomes possible to obtain a semiconductor package stacked body which is lighter, thinner and has a higher density than conventional ones, and in recent years, required miniaturization of electronic equipment. It becomes possible to deal with higher performance and higher performance.

The present invention will be described in more detail below.

[0018]

DETAILED DESCRIPTION OF THE INVENTION (Manufacturing of a substrate for a semiconductor package)
The semiconductor package substrate can be manufactured by a step of forming wiring on the insulating base material, a step of forming a conductive bump mounting portion on the wiring, a step of forming a device hole, and a step of attaching a tape with an adhesive. Either the step of forming the wiring or the step of forming the device hole may be performed first, and it is preferable to select an efficient order depending on the forming method. In addition to this, a step of forming an insulating coating and a step of forming a connection conductor are appropriately performed.

(Material of Insulating Base Material) As the insulating base material, a flexible insulating base material can be used. For example, a resin containing at least one or more of an imide group, an amide group, a phenol group, a phenylene group, an ester group, an ether group, a sulfone group, a carbonate group, a carbonyl group, and a silicone bond, or a liquid crystal polymer, a fluorine-based resin, an epoxy resin, or the like. Can be used. An insulating substrate can be obtained by impregnating a film or glass cloth with such a resin.

(Formation of Laminated Material) A laminated material composed of an insulating base material layer and a metal layer to be a wiring is formed by a method of bonding an insulating base material having an adhesive function to a metal foil, and an insulating varnish serving as an insulating base material on the metal foil. There is a method of casting, and a method of forming by depositing or plating on an insulating base material.

(Method of Bonding) As a method of forming a laminated material by bonding, there are a method of bonding a metal foil with an adhesive member and a method of directly bonding a semi-cured insulating base material to the metal foil. For example, MCL-E-679F (manufactured by Hitachi Chemical Co., Ltd., product name) has a sufficient adhesive force between the insulating base material and the metal foil as a semi-cured insulating base material directly bonded to the metal foil. Further, other properties required for the substrate, such as high heat resistance, are excellent and preferable. The thickness of the metal foil to be bonded onto the insulating base material having an adhesive function is preferably in the range of 5 to 50 μm, and it is difficult to bond the metal foil having a thickness of less than 5 μm. When formed, it may be difficult to form a fine shape. The metal foil is not particularly limited as long as it has high conductivity, but copper is preferable.

(Method by Casting) The laminated material having the insulating base material layer and the metal layer can also be manufactured by casting an insulating varnish serving as an insulating base material on a metal foil. In this case, if the surface of the metal foil is adjusted to have an appropriate roughness, there is no need to use an adhesive, which is economical. For example, when polyimide is cast on a copper foil as an insulating varnish, the surface roughness of the copper foil is 2
It is preferable that the particle size be ˜15 μm, and in order to adjust to such roughness, there is surface treatment with a generally known oxidizing agent, and sodium chlorite, alkali persulfate, potassium chlorate, potassium perchlorate, Alternatively, the treatment is performed by dipping or spraying the treatment liquid containing an oxidizing agent of an alkaline aqueous solution such as alkali peroxosulfate. Further, after this, copper oxide can be reduced to obtain metallic copper having a roughened surface while leaving unevenness. The resin varnish is cast on the copper foil whose surface is thus roughened. The casting conditions differ depending on the resin varnish used, but it is necessary to select the conditions such that warpage does not occur.

(Method by evaporation or plating) Further, a metal layer is formed on the insulating base material by evaporation or plating,
It may be a laminated material. For example, in the case of a polyimide resin film, in order to vapor-deposit copper, first, nickel or chromium, which is an adhesive metal, is vapor-deposited in a thickness of 5 to 100 nm, and then copper is vapor-deposited in a thickness of 10 to 600 nm. Further, by electroplating copper, a copper layer having a total thickness of 5 to 50 μm can be formed. Further, by electrolessly plating copper on the insulating base material to 0.5 to 3 μm, and then electroplating copper,
It is also possible to form a copper layer having a total thickness of 5 to 50 μm.

(Wiring formation) As a method of forming wiring, a method of etching away a metal layer in an unnecessary portion of a laminated material composed of a metal layer and an insulating base material layer or plating only in a necessary portion of the insulating base material is performed. There is a method of forming wiring.

(Wiring formation by etching) of the laminated material,
An etching resist can be formed on a portion of the metal layer to be wiring, and a chemical etching solution can be applied to a portion exposed from the etching resist to remove unnecessary metal foil by etching to form a wiring. As the etching resist, an etching resist material that can be used for ordinary wiring boards can be used, and the resist ink is formed by silk screen printing or a photosensitive dry film for etching resist is laminated on a metal foil. ,
On top of that, overlay a photomask that transmits light on the wiring shape,
It is formed by exposing it to ultraviolet rays and removing the unexposed areas with a developing solution. As the chemical etching solution, a chemical etching solution used for ordinary wiring boards such as a solution of cupric chloride and hydrochloric acid, a solution of ferric chloride, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

(Wiring formation by plating) Further, the wiring is
The insulating base material can be formed by plating only on necessary portions, and a wiring forming technique by ordinary plating can be used. For example, after depositing a catalyst for electroless plating on an insulating base material, form a plating resist on the surface part where plating is not performed, immerse it in an electroless plating solution, and only place it where it is not covered by the plating resist. Perform electroless plating. Then, if necessary, the plating resist is removed to obtain a semiconductor package substrate. Furthermore, wiring having a height of 5 to 50 μm can be formed by electrolytic plating.

(Formation of double-sided wiring) The wiring may be formed on only one surface of the insulating base material, but it can be formed on both surfaces of the insulating base material, and the wiring formed on both surfaces of the insulating base material is required. By electrically connecting the points with the connection conductor, the wiring density can be increased. Either the formation of the connection conductor or the formation of the wiring may be performed first, and it is preferable to select an efficient method. In addition, it is preferable that such a wiring is insulation-coated for insulation from the outside, formation of conductive bumps, and securing of reliability.

(Formation of Connection Conductor) The connection conductor can be formed by a method generally used for wiring boards, such as blind vias, through hole plating, and conductive paste. For example, in the case of blind vias, a laminated material in which metal foils are formed on both sides of an insulating base material is used, and an opening is formed by etching in one metal foil at the place where the connection conductor is formed, and then opened by laser processing or etching processing. It is possible to connect the metal foils on both sides by removing the insulating base material on the opposite side until reaching the metal foil on the opposite side, and forming a conductor layer on the inner wall of the insulating base material on the opening by electroless plating.

The necessary portions of the wiring formed as described above can be sequentially plated with nickel, gold or the like.
Furthermore, nickel, palladium, gold, or the like may be plated as necessary. These platings are generally applied to a portion of the wiring that is electrically connected to the semiconductor chip and a conductive bump mounting portion that is electrically connected to the mother board. This plating may use either electroless plating or electrolytic plating.

(Formation of Insulation Coating and Conductive Bump Mounted Section) The insulation coating used for the semiconductor package substrate requires highly accurate pattern formation in the external connection terminal section and the like.
Such pattern formation can be performed by printing if it is a varnish-like material, but in order to ensure more accuracy, a photosensitive solder resist, a coverlay film,
It is preferable to use a film resist. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, a fluorene-based material, or the like can be used. Since such an insulating coating shrinks during curing, if it is formed on only one side, the substrate is likely to warp significantly.In addition, when semiconductor packages are stacked, external connection such as conductive bumps is required on both sides of the semiconductor package. To form the terminals,
It is preferable to form an insulating coating on both surfaces of the insulating substrate.
Furthermore, since the warp changes with the thickness of the insulation coating,
It is more preferable to experimentally adjust the thickness of the insulating coatings on both surfaces so that warpage does not occur. To form a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less. The conductive bump mounting portion is formed by forming an insulating coating by opening it by etching or by forming a portion where the insulating coating is not formed.

(Formation of Device Hole) The device hole can be formed by router processing, die-cutting processing, laser processing, etching processing, etc., and an appropriate method can be selected depending on the material and thickness of the insulating base material, productivity, and processing accuracy. It is preferable to select. If the size of the device hole is too large, it is difficult to increase the density, and if it is small, the semiconductor chip cannot be inserted. Therefore, it is preferable that the size of the device hole is larger than the size of the semiconductor chip by 3 mm or less.

(Attachment of Adhesive Tape) The adhesive tape is attached to the semiconductor package substrate by applying an appropriate pressure. At this time, it can be attached while heating, and can be selected according to the type of the adhesive tape. Such pasting includes a method of manually or automatically using a roller, a method of using a roll laminator, and a pressure bonding device. At this time, it is preferable to select a condition in which the semiconductor package substrate does not warp after the adhesive tape is attached.

(Base Film of Adhesive Tape) As the base film of the adhesive tape, a resin film,
Any of metal foil, paper, cloth, glass cloth, or a combination thereof can be used.

As the material of the resin film, for example, polyamide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene ether, polybutylene terephthalate, polyester, aramid, polyether ether ketone, polyether ketone, polysulfone, polyether sulfone, polyarylate, Polyparaxylylene, polyparabanic acid, nylon, cellophane, silicone, fluorine resin, epoxy resin, liquid crystal polymer and the like can be used, and a combination including these may be used. To make these materials into a film, a resin varnish is applied to a supporting film or a supporting metal by using a kiss coater, a roll coater, a comma coater or the like, and the temperature is 120 to 350 ° C. for 20 to 18 ° C.
There is a method of forming by heating for about 0 minutes and completely curing. The heating is preferably performed under appropriate conditions depending on the resin used.

As the material of the metal foil, for example, aluminum,
Copper, lead, iron, chromium, nickel, etc. can be used, and an alloy containing them may be used. These materials can be made into metal foil by means such as rolling or plating.

As the paper, for example, kraft paper, high-quality paper, Japanese paper, etc. can be used, but it is not limited, but it is preferable to use flat paper or crepe paper combined with a resin. Further, the cloth is not particularly limited as long as it is a commonly used cloth.

The resin material of the resin film is paper, cloth,
The base film can also be formed by impregnating glass cloth or by applying heat or pressure to laminate and combine them.

Further, in order to reduce the peeling of the adhesive tape and the warpage of the semiconductor package, it is preferable to make the heat shrinkage of the base film of the adhesive tape equal to that of the insulating base material. The heat shrinkage of the base film is preferably within ± 2% of the heat shrinkage of the insulating base material, more preferably within ± 0.5%.

(Reduction of heat shrinkage of resin film) The conditions of the stretching treatment and the heat treatment depend on the kind of the resin film.
It is preferable to experimentally determine an appropriate value. In addition, it is possible to uniformly stretch or reduce the heat shrinkage rate by controlling the processing time and temperature distribution. For example, in the case of polyethylene terephthalate film, the machine direction is 80-140 ℃
It is generally stretched 4 times and stretched 2 to 4 times at 80 to 150 ° C in the transverse direction. Furthermore, by performing heat treatment in advance at a temperature of 170 to 240 ° C., the heat shrinkage ratio of 2% or more can be reduced to 1% or less.

(Thickness of Base Film) The thickness of the base film may be selected as appropriate depending on the material.
If the thickness is thin, the strength for withstanding the load at the time of applying the adhesive agent and for sticking to the semiconductor package substrate and peeling is insufficient, and if it is thick, peeling from the semiconductor package substrate becomes difficult. For example, 0.01 to 1.00 mm. Is more preferable, and 0.02 to 0.20 mm is more preferable.

(Adhesive) The adhesive-attached tape is required to have a function of fixing the semiconductor chip and a function of peeling after sealing with resin, and is preferably an adhesive tape which can be easily attached and peeled. Examples of such an adhesive include rubber-based, acrylic-based, silicone-based, epoxy-based,
A resin material such as polyimide can be used. The form of the adhesive is roughly classified into a solvent type and a solventless type.For example, when using a solvent type, the adhesive is dissolved in a solvent and applied to a base film, and dried to form an adhesive tape. You can For the adhesive, it is preferable to select a material, a thickness and an adhesive strength that are sufficiently close to the adherend and do not contaminate the surface during peeling.

Using such a semiconductor package substrate, a semiconductor chip is mounted on an adhesive tape, the wiring and the semiconductor chip are electrically connected, and then sealed by a sealing resin, and the adhesive tape is attached. Then, the semiconductor package can be manufactured by peeling off the conductive bumps and forming the conductive bumps to be the external connection terminals.

(Mounting of Semiconductor Chip and Connection with Wiring) The semiconductor chip is mounted on the adhesive tape in the device hole. At this time, it is preferable that the semiconductor chip and the adhesive-attached tape are sufficiently adhered to each other, and it is possible to pressurize and heat as necessary. A bonding wire can be used to electrically connect the semiconductor chip and the wiring plated with gold or the like. A gold wire is generally used as the bonding wire, but the method is not particularly limited as long as it is a commonly used method.

(Sealing of Semiconductor Chip with Sealing Resin) It is preferable that the semiconductor chip is sealed with a sealing resin from the viewpoint of moisture resistance. Such a sealing resin is not limited, but may be phenol. A thermosetting resin such as resin, melamine resin, epoxy resin, or polyester resin can be used. As a sealing method, transfer molding with a compound or potting or printing using a liquid resin sealing material so as to wrap the semiconductor chip can be performed. When manufacturing a thin semiconductor package, it is preferable to print using a liquid resin encapsulant in order to reduce warpage, and it is more preferable to use a vacuum differential pressure printing machine in order to prevent the inclusion of voids in the encapsulant. preferable.

(Peeling of Adhesive Tape) After sealing the semiconductor chip, the adhesive tape is peeled off. At this time, it is necessary to prevent damage to the semiconductor package, and it is preferable to peel off the adhesive tape with the semiconductor package adsorbed on a flat surface or fixed with a frame. The peeling step of the adhesive-attached tape is not particularly limited as long as it is after the semiconductor chip has been resin-sealed, but it is preferable to peel it before forming the conductive bumps.

(Formation of Conductive Bump) The conductive bump is
It can be formed on the conductive bump mounting portion formed on the wiring. As the conductive bump, for example, a solder bump, a polymer bump, a plating bump, a stud bump, or the like can be used. Further, when an alloy containing Sn such as solder is used, high-strength solder or lead-free solder can be used from the viewpoint of reliability improvement and environmental consideration. When forming a conductive bump using solder, paste paste solder is printed on the conductive bump mounting portion, or ball-shaped solder is placed on the conductive bump mounting portion and fused by a reflow device. There is a way. At this time, it is preferable to experimentally determine appropriate conditions for the printing amount of the paste and the ball diameter in consideration of reliability after mounting.

(Manufacturing Method of Semiconductor Package Laminate) By stacking semiconductor packages in two or more stages with conductive bumps, a high density semiconductor package laminate can be manufactured. For example, in order to stack semiconductor packages with solder bumps, it is effective to stack the semiconductor packages with solder bumps in place, melt and fuse the solder bumps by reflow, and make electrical and mechanical connections. Is preferred. At this time, there are a method of reflowing and laminating for each layer, a method of reflowing after laminating a required number of layers, and a method of laminating in multiple layers at once, and it is preferable to select an appropriate method in consideration of efficiency and reliability. . Further, it is preferable to fill the voids between the semiconductor packages caused by the height of the conductive bumps with a resin from the viewpoint of reliability, and as such a resin, a general underfill material can be used. Also, after temporarily fixing a varnish-like or film-like adhesive to one semiconductor package, stacking the other semiconductor package and heating / pressurizing the semiconductor package simultaneously achieves electrical / mechanical connection and resin fixing. You can also do it.

Although the present invention shows a plurality of embodiments below, it should not be understood that this description limits the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques not described here will be apparent to those skilled in the art. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims which are appropriate from the above description.

[0049]

EXAMPLES Example 1 Glass cloth impregnated with epoxy resin and semi-cured to a thickness of 60
As shown in FIG. 1 (a), a copper foil 2 was overlaid on a μm insulating base material 1 by heating and pressurizing to form a laminated material 14. Next, as shown in FIG. 1 (b), at the place where the connection conductor of one copper foil is formed,
An opening having a diameter of 0.15 mm was formed by etching, and the insulating base material at the opening was removed using a carbon dioxide laser until the metal foil on the opposite surface was reached. Subsequently, as shown in FIG. 1 (c), after performing a desmearing treatment on the hole processed portion, electroless plating and electrolytic plating were sequentially performed to form a blind via of the connection conductor 3. Further, as shown in FIG. 1 (d), after removing unnecessary copper foil 2 on both sides by etching to form wiring 4, as shown in FIG. 1 (e), epoxy acrylate that is insulating coating 5 on both sides. 25 μm of solder-based solder resist is printed, and semiconductor chip connection terminals and conductive bump mounting part 6
Was opened by exposure and development, and electroless nickel, palladium, and gold plating were sequentially applied to the wiring surface. Furthermore, the figure
As shown in 1 (f), the device hole 7 was processed using a router. Finally, the longitudinal direction is 3 degrees at 90 ° C by the sequential biaxial stretching method.
Double, and stretched in the transverse direction 3 times at 100 ℃, then 200 ℃
Adhesive tape 8 with an acrylic adhesive applied to a polyethylene terephthalate base film with a thickness of 50 μm that has been heat-treated in step 1 is pasted on one side with a roll laminator, as shown in Fig. 1 (g). It was The heat shrinkage rate of the base film after resin sealing was 1.4%.

As shown in FIG. 1 (h), the semiconductor chip 9 is mounted in the device hole 7 of the semiconductor package substrate manufactured as described above, and the wire bonder UTC230 (product name manufactured by Shinkawa Co., Ltd.) The diameter of the terminals on the chip and the semiconductor chip connecting terminals of the semiconductor package substrate is 2
A 5 μm gold wire 10 was used for wire bonding for connection. Next, as shown in FIG. 1 (i), the semiconductor chip 9 is sealed with a sealing resin 11
The liquid resin encapsulant, which is No. 1, was vacuum-pressure-differential printed, heated and cured to be encapsulated. Finally, as shown in FIG. 1 (j), the adhesive-attached tape 8 is peeled off, and the conductive bump mounting portion 6 on one surface is covered with tin.
A lead eutectic solder ball was melted to form conductive bumps 12 to obtain a semiconductor package.

Next, as shown in FIG. 1 (k), the conductive bumps 12 of the semiconductor package are overlaid on the conductive bump mounting portions 6 of the other semiconductor package, and the conductive bumps are melted and fused to form a semiconductor package. Were laminated. Further, after repeating the same steps and stacking the semiconductor packages in four stages as shown in FIG. 1 (l), as shown in FIG. A fill material was supplied and heat-cured to obtain a semiconductor package laminate.

A temperature cycle test (-65 to 150 ° C., 100 ° C.) of the semiconductor package laminate manufactured in this way
0 cyc) was performed. The results are shown in Table 1.

Example 2 The device hole 7 of the semiconductor package substrate was laser-processed, the insulating coating 5 was formed by laminating an epoxy photosensitive film, and the material of the base film (thickness 100 μm) of the adhesive tape 8 was changed. Same as Example 1 except that polyethylene naphthalate was subjected to heat treatment after being sequentially stretched by a biaxial stretching method, the adhesive was a silicone-based adhesive, and the sealing resin 11 was formed by transfer molding of a compound. Then, a semiconductor package laminate was manufactured and a temperature cycle test was conducted. The results are shown in Table 1.
The heat shrinkage rate of this base film after resin sealing is 0.05.
%Met.

Example 3 A copper foil 2 was cast with a polyimide resin varnish serving as an insulating substrate 1 having a thickness of 50 μm, and the copper foil 2 was further adhered to form a laminated material 14, and the device hole 7 was punched with a mold. It is formed by processing and uses a polyimide-based solder resist as the insulating coating 5, and a base film (thickness 1
(50 μm) material is crepe paper and the adhesive is a rubber-based adhesive, and a semiconductor package laminate is manufactured in the same manner as in Example 1 except that the adhesive-attached tape 8 is attached by pressure bonding. A cycle test was conducted. The results are shown in Table 1
Shown in. The heat shrinkage of this base film after resin sealing is
It was small enough to ignore.

Example 4 A laminate 1 was prepared by casting a polyimide resin varnish serving as an insulating base material 1 on a copper foil 2 and further bonding the copper foil 2 thereto.
4, the insulating coating 5 is a fluorene-based solder resist, the device hole 7 of the semiconductor package substrate is etched, and the base film material of the adhesive tape 8 is aluminum with a thickness of 200 μm. A semiconductor package was manufactured in the same manner as in Example 1 except that the epoxy adhesive was used. The heat shrinkage of the base film after resin sealing was small enough to be ignored.

Next, four semiconductor packages are formed as shown in FIG.
One of the conductive bumps of the semiconductor package
12 was laminated so as to overlap the conductive bump mounting portion 6 of the other semiconductor package, and all the conductive bumps were melted / fused together. Further, as shown in FIG. 2 (l), an underfill material, which is the fixing resin 13, was supplied into the gaps between the semiconductor packages and heat-cured to form a four-stage semiconductor package laminated body. This semiconductor package laminated body was subjected to a temperature cycle test in the same manner as in Example 1. The results are shown in Table 1.

Comparative Example 1 Example except that the material of the base film of the adhesive tape was polyethylene terephthalate with a thickness of 50 μm without stretching and heat treatment, and the adhesive was a rubber adhesive.
A semiconductor package laminate was manufactured in the same manner as in 1. The heat shrinkage rate of the base film after resin sealing was 2.3%.

However, heating during wire bonding causes peeling between the semiconductor chip and the adhesive tape,
Further, after the liquid resin encapsulant is cured, a large amount of warpage occurs in the substrate, so that it is not possible to efficiently manufacture the semiconductor package and stack the semiconductor packages.

Comparative Example 2 The material of the base film of the adhesive tape is 50 μm thick
A semiconductor package laminate was manufactured in the same manner as in Example 1 except that the polyethylene was used and the adhesive was a rubber adhesive.

However, the polyethylene base film was melted by the heating during wire bonding, and wire bonding could not be performed.

Comparative Example 3 The material of the base film of the adhesive tape is 500 μm thick
A semiconductor package laminate was manufactured in the same manner as in Example 2 except that m was polyvinyl chloride and the adhesive was an acrylic adhesive.

However, after the liquid resin encapsulant was cured, a large amount of warpage occurred on the substrate, so that it was not possible to efficiently manufacture the semiconductor package and stack the semiconductor packages.

[0063]

【table 1】

As shown in Table 1, as a result of the temperature cycle test, defects such as cracks, chip warpage, and defective bonding did not occur in the semiconductor package laminate of the example.

[0065]

Therefore, according to the present invention, a semiconductor package substrate which is excellent in reliability and is suitable for thinning, weight reduction and high density, a semiconductor package using the same, a laminated body thereof, and the like. Can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in each process for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view in each process for explaining a fourth embodiment of the present invention.

[Explanation of symbols]

1 Insulating base material 2 copper foil 3 connection conductor (blind via) 4 wiring 5 Insulation coating 6 Conductive bump mounting part 7 device hole 8 Adhesive tape 9 Semiconductor chips 10 gold wire 11 Sealing resin 12 Conductive bump 13 Fixing resin 14 Laminated material

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Reiko Yamaguchi             48 Wadai, Tsukuba, Ibaraki Prefecture Hitachi Chemical Co., Ltd.             Company Research Institute (72) Inventor Yoshiaki Tsubomatsu             Hitachi Chemical, 1500 Ogawa, Shimodate City, Ibaraki Prefecture             Shimodate Office of Industry Co., Ltd. (72) Inventor Yu Kawakami             Hitachi Chemical, 1500 Ogawa, Shimodate City, Ibaraki Prefecture             Shimodate Office of Industry Co., Ltd.

Claims (29)

[Claims] 1. An insulating base material, a wiring supported by the insulating base material and electrically connected to a semiconductor chip, a conductive bump mounting portion formed on the wiring, and the insulation as a semiconductor chip mounting location. A semiconductor package substrate comprising at least a device hole formed through a base material and an adhesive tape attached to one surface of the insulating base material, the base of the adhesive tape being provided. A semiconductor package substrate in which the film is a resin film, metal foil, paper, cloth, glass cloth, or a combination thereof. 2. The material of the resin film is polyamide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene ether, polybutylene terephthalate, polyester, aramid, polyether ether ketone, polyether ketone, polysulfone, polyether sulfone, polyacrylate, The semiconductor package according to claim 1, which is any one of polyparaxylylene, polyparabanic acid, polycarbonate, acetate, polymethylpentene, nylon, cellophane, silicone, fluorine resin, epoxy resin, liquid crystal polymer, or a combination thereof. substrate. 3. The substrate for a semiconductor package according to claim 1, wherein the resin film is stretched and / or heat-treated in advance. 4. The substrate for a semiconductor package according to claim 1, wherein the metal foil is any one of aluminum, copper, lead, iron, chromium and nickel or an alloy containing them. 5. The substrate for a semiconductor package according to claim 1, wherein the adhesive of the adhesive tape includes a rubber-based, acrylic-based, silicone-based, epoxy-based, or polyimide-based resin material. 6. The substrate for a semiconductor package according to claim 1, wherein an insulating coating is formed on a necessary portion of the insulating base material and the wiring. 7. The substrate for a semiconductor package according to claim 6, wherein the insulating coating contains a material having photosensitivity. 8. The wiring comprises a first wiring formed on one surface of the insulating base material and a second wiring formed on the opposite surface thereof, and the first wiring and the second wiring are formed. The semiconductor package substrate according to claim 1, wherein the wiring is electrically connected by a connection conductor. 9. The conductive bump mounting portion is formed on both the first wiring and the second wiring.
The semiconductor package substrate according to. 10. A step of forming a wiring electrically connected to a semiconductor chip on an insulating base material, a step of forming a conductive bump mounting portion on the wiring, and a device penetrating the insulating base material. A method for manufacturing a semiconductor package substrate, comprising: forming a hole; and attaching an adhesive tape to one surface of the insulating base material, wherein a resin film is used as a base film of the adhesive tape. A method for manufacturing a semiconductor package substrate using any one of metal foil, paper, cloth, glass cloth, or a combination thereof. 11. The material of the resin film includes polyamide, polyethylene terephthalate, polyethylene naphthalate, polyphenylene ether, polybutylene terephthalate, polyester, aramid, polyether ether ketone, polyether ketone, polysulfone,
Use of any one of polyether sulfone, polyacrylate, polyparaxylylene, polyparabanic acid, polycarbonate, acetate, polymethylpentene, nylon, cellophane, silicone, fluorine resin, epoxy resin, liquid crystal polymer, or a combination thereof. 10. The method for manufacturing a semiconductor package substrate according to item 10. 12. The method for manufacturing a semiconductor package substrate according to claim 10, further comprising a step of subjecting the resin film to a stretching treatment and / or a heat treatment in advance. 13. The metal foil includes aluminum, copper, lead,
The method for manufacturing a semiconductor package substrate according to claim 10, wherein any one of iron, chromium, and nickel or an alloy containing them is used. 14. As an adhesive for the adhesive tape,
The method for manufacturing a semiconductor package substrate according to claim 10, wherein a rubber-based, acrylic-based, silicone-based, epoxy-based, or polyimide-based resin material is used. 15. The method according to claim 10, further comprising the step of forming an insulating coating on a necessary portion of the insulating base material and the wiring.
A method for manufacturing a semiconductor package substrate according to any one of 1. 16. The method of manufacturing a semiconductor package substrate according to claim 15, wherein the insulating coating is made of a material having photosensitivity, and the method includes a step of exposing and developing a necessary portion to open the substrate. 17. The wiring comprises a first wiring formed on one surface of the insulating base material and a second wiring formed on the opposite surface thereof, and the first wiring and the second wiring are formed. 11. The method according to claim 10, further comprising the step of electrically connecting the wiring with a connection conductor.
17. The method for manufacturing a semiconductor package substrate according to any one of 16. 18. The method of manufacturing a semiconductor package substrate according to claim 17, further comprising the step of forming conductive bump mounting portions on both the first wiring and the second wiring. 19. A semiconductor package substrate according to any one of claims 1 to 9 or a semiconductor package substrate according to the manufacturing method according to any one of claims 10 to 18,
The semiconductor chip mounted on the adhesive-attached tape in the device hole and electrically connected to the wiring, the sealing resin that seals a necessary portion of the semiconductor package substrate, and the external connection terminal that is the wiring. And a conductive bump formed on the conductive bump mounting portion formed above, wherein the tape with adhesive is peeled off after the semiconductor chip is sealed with the sealing resin. 20. The semiconductor package according to claim 19, wherein the sealing resin is formed by curing a liquid resin sealing material. 21. A semiconductor package substrate according to any one of claims 1 to 9 or a tape with an adhesive in a device hole of a semiconductor package substrate according to any one of claims 10 to 18. A step of mounting a semiconductor chip and electrically connecting the semiconductor chip and wiring, a step of resin-sealing necessary portions of the semiconductor package substrate, and a step of peeling the adhesive tape.
Forming a conductive bump as an external connection terminal on the conductive bump mounting portion formed on the wiring. 22. The method of manufacturing a semiconductor package according to claim 21, wherein a liquid resin sealing material is used for sealing in the resin sealing step. 23. The method of manufacturing a semiconductor package according to claim 22, wherein sealing with the liquid resin sealing material is performed by printing. 24. The semiconductor package according to claim 19 or 20 or the semiconductor package according to the manufacturing method according to any one of claims 21 to 23 is stacked in two or more stages, and the semiconductor packages are electrically connected and fixed by the conductive bumps. The semiconductor package stack that is being used. 25. The semiconductor package laminate according to claim 24, wherein the semiconductor packages are further fixed with a resin. 26. The semiconductor package according to claim 19 or 20, or the semiconductor package according to the manufacturing method according to any one of claims 21 to 23, is stacked in two or more steps, and the semiconductor packages are electrically connected and fixed by conductive bumps. A method for manufacturing a semiconductor package laminate including a step. 27. The method of manufacturing a semiconductor package laminate according to claim 26, further comprising a step of further fixing the semiconductor packages with a resin. 28. The method of manufacturing a semiconductor package laminate according to claim 26, wherein the semiconductor packages are stacked one by one and conductive and fixed up to a required number of layers. 29. The method of manufacturing a semiconductor package laminate according to claim 26, wherein the semiconductor packages are laminated in a required number of layers, and the semiconductor packages are electrically connected and fixed together.