JP2003234431A - Semiconductor chip mounting circuit board, its manufacturing method and multilayered circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the distance between semiconductor chips by burying the chips between adjacent circuit boards to eliminate troubles due to the resistance or the inductance of a wiring, thus transferring electric signals at high speeds, without delay. <P>SOLUTION: The semiconductor chip mounting circuit board comprises a conductor circuit on one surface of an insulating resin base. The conductor circuit has a semiconductor chip mounted on an approximately central surface portion through first conductor bumps and extends from the first bumps to a peripheral part of the insulating resin base having via holes extending to the conductor circuit on the other surface of the resin base. Second conductive bumps to be electrically connected to another circuit board are formed just on the via holes A manufacturing method of the invented circuit board and a multilayer circuit board with the invented board laminated with another one-side circuit board are provided. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board suitable for mounting a semiconductor chip such as an IC chip on a conductor circuit provided on an insulating resin substrate, a method for manufacturing the mounted circuit board, and a semiconductor chip. The present invention relates to a multilayer circuit board formed by stacking mounted circuit boards.

[0002]

2. Description of the Related Art Recently, a technique for embedding a semiconductor chip in a substrate has been proposed in order to meet the demand for higher density and higher functionality of a printed wiring board. For example, Japanese Patent Laid-Open No. 10-256
No. 429 discloses a package in which a semiconductor chip is embedded in a ceramic substrate. Such a package has a BGA structure in which a semiconductor chip is embedded in a recess formed in a ceramic substrate and the semiconductor chip is connected to a conductor circuit provided on the substrate by flip-chip mounting. It is described that it is possible to improve the heat dissipation from the semiconductor chip, and further to cope with narrow pitch wiring.

However, in the above-mentioned package substrate according to the prior art, since the wiring for electrically connecting the semiconductor chip to the outside is drawn only by the substrate, it is difficult to stack such substrates. .
Even if they are laminated, it is extremely difficult to connect the wirings drawn from the semiconductor chips to the substrate to be laminated because the structure of the substrate in which the semiconductor chips are embedded and the substrate to be laminated thereon are basically different.

In the first place, the above-mentioned ceramic substrate in which the semiconductor chip according to the prior art is embedded is used as a package substrate, and is for connecting the terminals on the semiconductor chip side formed at a fine pitch to the printed board. The drawn wiring is to be electrically connected to an external substrate via a solder ball (BGA) or a pin (PGA), and therefore, there is no recognition of stacking such substrates, and further, The structure is not such that the semiconductor chips can be stacked by stacking the substrates. Therefore, even if they are stacked, there is a problem that they cause peeling in the connection between the substrates and the electrical connectivity and reliability are deteriorated.

The present invention has been made in view of the above problems of the prior art, and its main purpose is to ensure reliable electrical connection with a semiconductor chip and to pull out from the semiconductor chip. It is an object of the present invention to provide a circuit board for mounting a semiconductor chip having a structure in which wiring can be further laminated. Another object of the present invention is to propose a method of manufacturing a circuit board for mounting a semiconductor chip. Still another object of the present invention is to provide a multi-layer circuit board in which circuit boards on which semiconductor chips are mounted are stacked and multilayered by hot pressing.

[0006]

Therefore, the present inventors have
As a result of earnest research to realize the above-mentioned purpose, a conductive circuit is provided on one surface of the insulating resin base material, and a via hole reaching the conductive circuit from the other surface of the insulating resin base material is formed.
In a multi-layer circuit board formed by laminating a plurality of circuit boards having conductive bumps formed directly on the via holes via an adhesive, and laminating the plurality of laminated circuit boards by heating press In some of the circuit boards, a semiconductor chip is mounted on the conductor circuit, and the semiconductor chip is embedded between the circuit board on which the semiconductor chip is mounted and another circuit board adjacent to the semiconductor circuit. The distance between chips can be shortened, and the defects caused by the resistance and inductance of wiring can be reduced. As a result, electrical signals can be transmitted at high speed without delay, so that the density of wiring boards can be increased and The present invention has been conceived of as having the following contents as a gist configuration, since it has been found that high functionality can be achieved. That is,

The circuit board for mounting a semiconductor chip of the present invention has a region for mounting a semiconductor chip in the substantially central portion on one surface side of the insulating resin base material, and the first conductive layer is provided in the mounting region. Conductive bumps are formed, and a conductor circuit is extended from the first conductive bump toward the peripheral portion of the insulating resin base material, and the conductor circuit is provided on the other surface side of the insulating resin base material. A via hole formed by filling a conductive material into the opening reaching to, and a second conductive bump electrically connected to another circuit board directly above the via hole. Is a circuit board characterized by

Further, the semiconductor chip mounted circuit board of the present invention includes a conductor circuit for mounting the semiconductor chip on the one surface side of the insulating resin base material in a substantially central portion thereof through the first conductive bumps. The conductor circuit extends from the first conductive bump toward the peripheral portion of the insulating resin base material, and the conductive circuit is provided in the opening reaching the conductor circuit on the other surface side of the insulating resin base material. And a second conductive bump electrically connected to another circuit board is formed directly above the via hole.

According to the above-mentioned configurations (1) and (2), the semiconductor chip can be directly mounted on the conductor circuit formed on one surface of the circuit board via the first conductive bump. Since it can be connected to another circuit board through the second conductive bumps provided on the other surface of the circuit board or in the vicinity of the connection portion with the via hole of the conductor circuit, the wiring board can be made high in density. It is possible to reduce the distance between the semiconductor chips,
Since it is possible to reduce defects caused by wiring resistance and inductance, it is possible to transmit an electric signal at high speed without delay.

In the circuit boards described in (1) and (2) above, the conductive bumps are made of Sn, Pb, Ag, Au,
It is desirable to be formed of at least one metal selected from Cu, Zn, In, Bi, solder or tin alloy. Such a metal is advantageous in that it is excellent in corrosion resistance, and when formed from a metal having a melting temperature lower than that of the resin substrate, it is advantageous in that it does not warp or deform.

The conductive bumps are preferably formed by electrolytic plating or electroless plating,
In particular, electrolytic plating is preferable, and electrolytic tin plating is more preferable among them.

In the circuit boards described in (1) and (2) above, it is desirable that the conductive material is formed by electrolytic copper plating and the conductive bumps are formed by electrolytic tin plating. According to such a configuration, the function of adhering the conductors to each other can be fulfilled, and the electrical connection can be surely made, which is advantageous in terms of connectivity and reliability.

Further, in the circuit boards described in (1) and (2) above, it is desirable that a roughening layer is formed on the surface of the conductor circuit, and the adhesion between the insulating resin layer and the conductor layer is improved. It is advantageous in terms of improvement.

In the method of manufacturing a circuit board for mounting a semiconductor chip according to the present invention, a semiconductor chip arranged in substantially the center of the base material is mounted on a conductor circuit formed on one surface of an insulating resin base material. A first conductive bump is formed, and a via hole formed by filling a conductive substance in the opening reaching the conductor circuit from the other surface of the insulating resin base is provided, and on the via hole. In manufacturing a circuit board having a second conductive bump to be connected to another circuit board, at least the following steps (1) to (2), ie, a copper foil was attached to one surface, during the manufacturing process. A step of forming an opening reaching the copper foil on the other surface side of the insulating resin base material, and filling a conductive substance in the opening to form a filled via hole, located directly above the filled via hole do it A step of forming a second conductive bump with a deplating film or a conductive paste; attaching a protective film to the other surface of the insulating resin base material, and mounting the protective film on substantially the center of one surface of the insulating resin base material Step of forming a plating resist layer having an opening corresponding to the terminal position of the semiconductor chip, electrolytic plating treatment is performed on the insulating resin base material obtained in the above step, and an electrolytic plating film is filled in the opening. And forming a first conductive bump corresponding to the terminal position of the mounted semiconductor chip, removing the plating resist layer, and then moving from the first conductive bump to the peripheral portion of the insulating resin base material. To form an etching resist layer corresponding to a predetermined circuit pattern that extends over the entire area, and to remove the copper foil part where the etching resist layer is not formed by etching. Therefore, the step of forming the predetermined circuit pattern,
A method of manufacturing a circuit board for mounting a semiconductor chip, comprising:

(4) Further, in the method for manufacturing a circuit board for mounting a semiconductor chip according to the present invention, the conductor circuit is formed on one surface of the insulating resin base material, and the circuit board is arranged substantially in the center of the base material. A first conductive bump for mounting a semiconductor chip is formed, and a via hole formed by filling a conductive substance is provided in an opening reaching the conductor circuit from the other surface of the insulating resin base material. In manufacturing a circuit board in which a second conductive bump to be connected to another circuit board is provided on the via hole, at least the following steps (1) to (2), that is, copper on one surface, is performed during the manufacturing process. A light-transmissive resin film is attached to the other surface of the insulating resin base material to which the foil is attached, and laser irradiation is performed from above the resin film to the other surface of the insulating resin base material, and the copper Form an opening that reaches the foil Together with the step of cleaning the residue left in the opening, in a state in which one surface of the insulating resin substrate is covered with a protective film, electrolytic copper plating treatment is performed to fill the opening with an electrolytic copper plating film. Forming a filled via hole by performing electrolytic tin plating treatment on the insulating resin base material obtained in the previous step, and forming a second conductive layer made of an electrolytic tin plating film directly above the filled via hole. A step of forming a conductive bump, after peeling off the protective film and the resin film from the insulating resin base material, respectively, affixing a protective film on the other surface of the insulating resin base material, the insulating resin base material Process of forming a plating resist layer having an opening corresponding to the terminal position of the mounted semiconductor chip on the substantially central part of one surface, electrolytic tin plating on the insulating resin substrate obtained in the above process To form a first conductive bump corresponding to the terminal position of the mounted semiconductor chip by filling the opening with an electrolytic tin-plated film, and after removing the plating resist layer, the first An etching resist layer corresponding to a predetermined circuit pattern extending from the conductive bump toward the peripheral portion of the insulating resin base material is formed, and the copper foil portion where the etching resist layer is not formed is removed by etching treatment. A step of forming the predetermined circuit pattern by
A method of manufacturing a circuit board for mounting a semiconductor chip, comprising:

(5) The multilayer circuit board of the present invention has a conductor circuit on one surface of the insulating resin base material, and a via hole is formed from the other surface of the insulating resin base material to reach the conductor circuit. In a multilayer circuit board in which a plurality of circuit boards having conductive bumps formed directly above the via holes are laminated with an adhesive, and the laminated circuit boards are integrated by a heat press. In some of the circuit boards, semiconductor chips are mounted on the conductor circuits, and the mounted semiconductor chips are embedded between the circuit board and another adjacent circuit board. It is a characteristic multilayer circuit board,

(6) In addition, the multilayer circuit board of the present invention has a conductor circuit on one surface of the insulating resin base material, and a via hole reaching from the other surface of the insulating resin base material to the conductor circuit is formed. A multilayer circuit in which a plurality of circuit boards having conductive bumps formed directly on the via holes are laminated with an adhesive and the laminated circuit boards are integrated by a heat press. In the board, some of the circuit boards have a semiconductor chip mounted on the conductor circuit in a substantially central portion thereof, and the conductor circuit has a peripheral portion of the circuit board from a terminal position of the mounted semiconductor chip. And a multilayer circuit board characterized in that it is configured to be connected to the via hole in its peripheral portion,

(7) The multilayer circuit board of the present invention has a conductor circuit on one surface of the insulating resin base material, and a via hole is formed from the other surface of the insulating resin base material to reach the conductor circuit. In a multilayer circuit board in which a plurality of circuit boards having conductive bumps formed directly above the via holes are laminated with an adhesive, and the laminated circuit boards are integrated by a heat press. In some of the circuit boards, a semiconductor chip is mounted on the conductor circuit in a substantially central portion thereof, and the conductor circuit extends from the terminal position of the mounted semiconductor chip toward the peripheral portion of the circuit board. Is provided, and is configured to be connected to the via hole in the peripheral portion thereof, while the other circuit board adjacent to the circuit board on which the semiconductor chip is mounted,
In the multilayer circuit board, an opening is formed so that the mounted semiconductor chip can pass therethrough.

In the multilayered circuit board described in (5) to (7) above, the conductive bumps are Sn, Pb, Ag, A.
It is desirable to be formed of at least one metal selected from u, Cu, Zn, In, Bi, solder or tin alloy. Such a metal is advantageous in that it is excellent in corrosion resistance, and when formed from a metal having a melting temperature lower than that of the resin substrate, it is advantageous in that it does not warp or deform.

The conductive bumps are preferably formed by electrolytic plating or electroless plating, and in particular,
Electrolytic plating is preferred, of which electrolytic tin plating is more preferred. In the most preferred embodiment, the via holes are formed by electrolytic copper plating, and the conductive bumps are formed by electrolytic tin plating.

In the multilayer circuit board described in (5) to (7) above, it is desirable that a roughening layer is formed on the surface of the conductor circuit.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor chip mounting circuit board according to the present invention is characterized in that a semiconductor chip such as an IC chip is mounted and stacked with another stacking circuit board having almost the same structure to form a semiconductor chip. It is suitable for use in the manufacture of a multilayer circuit board capable of promptly transmitting signals between chips.

That is, the circuit board for mounting a semiconductor chip according to the present invention has a region for mounting a semiconductor chip in substantially the center of one surface of an insulating resin substrate, and surrounds the mounting region to mount a large number of mounting substrates. Conductive bumps (below,
"First conductive bumps") are formed, and electrically connected to the first conductive bumps, and a conductor circuit is extended from the mounting region toward the peripheral portion of the substrate. On the other hand, an opening reaching the conductor circuit from the other surface of the insulating substrate is provided, and a filling via hole formed by filling the opening with a conductive substance is formed at the peripheral portion of the substrate and the via hole is formed. Directly above the hole is formed a conductive bump for connection (hereinafter, referred to as “second conductive bump”) that is electrically connected to another circuit board.

The circuit board on which such a semiconductor chip is mounted is laminated together with another circuit board on which a circuit is formed and having substantially the same structure, or a mounted circuit board on which another semiconductor chip is mounted, and is integrated by a heat press. As a result, a multi-layer circuit board having high density and high functionality is formed.

In the above multi-layering, for example, a circuit board on which a semiconductor chip mainly having an arithmetic function is mounted is arranged on the surface side thereof, and a circuit board on which a semiconductor chip mainly having a memory function is mounted is disposed on the inner layer side. Between the semiconductor chip mounting circuit boards, an opening corresponding to the semiconductor chip mounting area is provided in substantially the center of the insulating base material, and a conductor circuit is provided on one surface of the insulating base material. On the other surface, a filling via hole formed by filling a conductive material into the opening reaching the conductor circuit is formed, and a laminating circuit board formed by forming a conductive bump immediately above the via hole is arranged. In this state, the circuit boards are laminated and integrated by hot pressing.

In the multi-layered circuit board thus obtained, the semiconductor chip mounted on the circuit board faces the inside of the central opening of the adjacent laminating circuit board and is resin-sealed in the first state. Connected to the conductor circuit extending toward the outer peripheral portion of the substrate through the conductive bumps of, and further connected to the semiconductor chip on the mounting circuit board on the inner layer side through the via hole and the second conductive bump. Since the distance between the semiconductor chips is shortened and the defects caused by the wiring resistance and the inductance are reduced, as a result, the electric signals can be transmitted at high speed without delay.

The insulating resin base material used in the circuit board of the present invention may be any organic insulating base material, specifically, aramid nonwoven fabric-epoxy resin base material, glass cloth epoxy resin base material, From aramid non-woven fabric-polyimide base material, bismaleimide triazine resin base material, rigid (hard) laminated base material selected from FR-4 and FR-5, or films such as polyphenylene ether (PPE) film and polyimide (PI) It is desirable to be one kind selected from the following flexible base materials.

In particular, since the hard insulating resin base material is formed of a completely cured resin material, not a conventional prepreg in a semi-cured state, it is possible to use an insulating base material by using such a material. When the copper foil is pressure-bonded onto the material by hot pressing, the final thickness of the insulating base material does not change due to the pressing pressure, so that the displacement of the via hole can be minimized and the via land diameter can be reduced. Therefore, the wiring pitch can be reduced to improve the wiring density. Further, since the thickness of the base material can be kept substantially constant, when forming an opening for forming a filled via hole, which will be described later, by laser processing, it is easy to set the laser irradiation condition.

A copper foil is attached to one surface of the insulating resin base material with an appropriate resin adhesive, and a conductor circuit is formed by an etching treatment described later. Instead of sticking a copper foil on such an insulating base material, it is also possible to use a single-sided copper-clad laminate in which a copper foil is stuck on the insulating base material in advance. May be mat-treated. The use of a single sided copper clad laminate is the most preferred embodiment.

The above single-sided copper-clad laminate is prepared by impregnating a glass cloth with a thermosetting resin such as an epoxy resin base material, a phenol resin or a bismaleimide-triazine resin, and laminating a B stage prepreg and a copper foil, followed by heating. It is a substrate obtained by pressing under pressure. This single-sided copper-clad laminate is a rigid substrate, easy to handle, and most advantageous in terms of cost. Alternatively, the metal layer may be formed on the surface of the insulating resin substrate by vapor deposition of metal and then electrolytic plating.

The insulating resin base material has a thickness of 10 to 20.
0 μm, preferably 15 to 100 μm, 20 to 8
0 μm is optimal. If the thickness is less than these ranges, the strength is lowered and handling becomes difficult, and conversely, if it is too thick, it becomes difficult to form fine via holes and fill with a conductive material.

On the other hand, the thickness of the copper foil forming the conductor circuit is
5 to 36 μm, preferably 8 to 30 μm, 12 to
25 μm is more preferable. The reason for this is that when an opening for forming a via hole is provided by laser processing, as will be described later, it penetrates if it is too thin, and conversely, if it is too thick, it is difficult to form a fine pattern by etching. .

The opening for forming the via hole is formed by adhering a light-transmissive resin film to the surface of the insulating resin base material opposite to the surface on which the copper foil is adhered via a semi-cured resin adhesive layer in advance, It is formed by performing laser irradiation on the resin film.

The resin film provided with the openings by the laser irradiation functions as a printing mask when the openings reaching the copper foil from the surface of the insulating base material are filled with a conductive substance to form via holes. In addition, when a conductive bump is formed directly on the surface of the via hole after the conductive material is filled in the opening, it serves to adjust the protruding height of the bump. It has a pressure-sensitive adhesive layer that is peeled off from the adhesive layer after the passage.

In the above resin film, for example, the adhesive layer has a thickness of 1 to 20 μm, and the film itself has a thickness of 1
It is preferably formed from a polyethylene terephthalate resin film having a thickness of 0 to 50 μm (hereinafter referred to as “PET film”). The reason is that the amount of protrusion of the conductive bump from the surface of the insulating substrate is determined depending on the thickness of the PET film. Therefore, if the thickness is less than 10 μm, the amount of protrusion is too small and connection failure tends to occur. When the thickness is more than 50 μm, the fused conductive bumps spread too much at the connection interface, so that a fine pattern cannot be formed.

As the laser processing machine, a carbon dioxide laser processing machine, a UV laser processing machine, an excimer laser processing machine or the like can be used. In particular, the carbon dioxide laser processing machine is the most suitable laser processing machine for the present invention because it has a high processing speed and can be processed at low cost, and is therefore most suitable for industrial use.

The diameter of the opening formed in the insulating resin base material having the thickness in the above range by such a carbon dioxide laser is preferably in the range of 50 to 200 μm, and the laser irradiation conditions at that time are as follows: It is desirable that the pulse energy is 0.5 to 100 mJ, the pulse width is 1 to 100 μs, the pulse interval is 0.5 ms or more, and the number of shots is 3 to 50.

The reason for limiting the aperture diameter is 50 μm.
This is because if the thickness is less than m, it becomes difficult to fill the conductive paste in the opening and the connection reliability becomes low, and if it exceeds 200 μm, it becomes difficult to increase the density.

Before filling the opening with a conductive substance to form a via hole, a desmear treatment for removing resin residue remaining on the inner wall surface of the opening, for example, an oxidizing agent such as an acid, permanganic acid, or chromic acid. From the viewpoint of securing the connection reliability, it is preferable to perform the treatment by a chemical removal method of immersing in, or a physical removal method using plasma discharge or corona discharge.

In particular, when the adhesive layer or the protective film is attached to the insulating base material, it is desirable to perform dry desmear treatment using plasma discharge or corona discharge. Among the dry desmear processing, plasma cleaning using a plasma cleaning device is particularly preferable. In this embodiment, the opening for forming the via hole was formed by laser processing, but drilling,
It is also possible to make holes by a mechanical method such as punching.

As a method of forming a via hole by filling a conductive material into the opening subjected to the desmear treatment, there are a plating filling method by a plating treatment and a filling method by a conductive paste. In particular, when filling with plating, take measures to prevent contact with the plating solution by pasting a protective film in advance so that plating does not deposit on the copper foil on the insulating base material, and then place it in the opening. Fill the plating to form a via hole.

The filling of the via hole forming opening with the plating can be performed by either electrolytic plating or electroless plating, but electrolytic plating is preferable.

As the electrolytic plating, for example, Sn, P
Although b, Ag, Au, Cu, Zn, In, Bi, solder, tin alloy, or the like can be used, electrolytic copper plating is particularly suitable. In the case of filling by electrolytic plating treatment, electrolytic plating is performed using the copper foil formed on the insulating base material as a plating lead. Since this copper foil (metal layer) is formed over the entire area of one surface of the insulating base material, the current density becomes uniform, and the openings can be filled by electrolytic plating at a uniform height. . Here, the surface of the metal layer in the opening may be activated with an acid or the like before the electrolytic plating treatment.

After electrolytic plating, the electrolytic plating (metal) rising from the holes may be removed by polishing or the like to flatten the surface. For polishing, a belt sander or buffing can be used. The electrolytic plating may be left slightly higher than that of the insulating substrate.

Further, instead of the filling of the conductive material by the plating treatment, a method of filling the conductive paste, or a portion of the opening is filled by the electrolytic plating treatment or the electroless plating treatment, and the remaining portion is filled with the conductive paste. You can also do it.

As the conductive paste, silver, copper,
A conductive paste made of one or more kinds of metal particles selected from gold, nickel and various solders can be used.

As the above-mentioned metal particles, those obtained by coating the surface of the metal particles with a different metal can be used.
Specifically, metal particles in which the surface of copper particles is coated with a noble metal such as gold or silver can be used. In addition, as the conductive paste, thermosetting resin such as epoxy resin or polyphenylene sulfide (PPS) is used for the metal particles.
An organic conductive paste containing a resin is desirable.

On the other hand, in this embodiment, the opening formed by laser processing has a hole diameter of 50 to 200.
Since the pores have a size of μm, bubbles tend to remain when the conductive paste is filled, so that the filling by electrolytic plating is practical.

A second conductive layer formed on the exposed surface of the via hole on the side opposite to the copper foil sticking surface (metal layer) of the insulating resin base material for the purpose of ensuring electrical connection with another circuit board. The bumps are preferably formed by a plating process or by printing a conductive paste, and the openings formed in the protective film by laser irradiation are filled with plating having a height related to the thickness of the protective film. More preferably, it is formed by

The plating filling can be performed by either electrolytic plating treatment or electroless plating treatment, but electrolytic plating treatment is more preferable.

As electrolytic plating, for example, Sn, P
Although b, Ag, Au, Cu, Zn, In, Bi, solder or tin alloy can be used, in this embodiment,
Electrolytic tin plating is most suitable.

The height of the second conductive bump is as follows.
The range of 3 to 60 μm is desirable. The reason is that if the thickness is less than 3 μm, variations in bump height cannot be tolerated due to deformation of the bump, and if it exceeds 60 μm, the resistance value becomes high and the bumps spread laterally when formed. This can cause a short circuit.

The second conductive bumps can also be formed by filling a conductive paste into the openings formed in the protective film by laser irradiation instead of plating. In this case, the height variation of the electrolytic plating can be corrected by adjusting the amount of the conductive paste to be filled, and the height of many conductive bumps can be made uniform.

The bumps made of this conductive paste are preferably in a semi-cured state. This is because the conductive paste is hard even in a semi-cured state and can penetrate the softened organic adhesive layer during hot pressing. Further, it is because the contact area is increased due to deformation during hot pressing, which can reduce the conduction resistance and can correct the variation in the bump height.

In addition to this, for example, in addition to a method of screen-printing a conductive paste using a metal mask having openings at predetermined positions, a method of printing a solder paste which is a low melting point metal, and solder plating. The conductive bumps can be formed by a method or a method of dipping in a solder melt. As the low melting point metal, Pb-
Sn-based solder, Ag-Sn-based solder, indium solder or the like can be used.

On the other hand, the first conductive bumps for mounting a semiconductor chip such as an IC chip, which are formed on the copper foil sticking surface (metal layer) of the insulating resin base material, are plated with a conductive paste. It is desirable to print by. In particular, bumps for electrically connecting to a semiconductor chip by mask exposure and development processing after first sticking a photosensitive dry film or applying a liquid photosensitive resist on the copper foil sticking surface of the insulating resin base material. It is the most preferable embodiment to form a plating resist layer having an opening for forming a hole and form a bump in the opening by a plating process.

The bump formation by the above plating can be performed by either electrolytic plating treatment or electroless plating treatment, but the bump formation by electrolytic plating treatment is more preferable. As electrolytic plating, for example, Sn, P
Although b, Ag, Au, Cu, Zn, In, Bi, solder or tin alloy can be used, electrolytic tin plating is the most preferred embodiment.

The shape of the first conductive bump is as follows.
A cylinder, an elliptic cylinder, a rectangular parallelepiped, or a cube can be adopted, and its height is preferably in the range of 1 to 30 μm. The reason is that if the thickness is less than 1 μm, the conductive bumps cannot be uniformly formed.
This is because the occurrence of migration and whiskers will increase if the value exceeds. In particular, it is most preferable that the height is 5 μm.

When the first conductive bump is cylindrical or elliptic, the diameter is preferably in the range of 50 to 200 μm, and most preferably 80 μm.

After forming the first conductive bump, NaO
The plating resist layer is completely removed using an alkali such as H or KOH, an acid such as sulfuric acid, nitric acid, acetic acid, or a solvent such as alcohol.

The conductor circuit formed on the copper foil sticking surface of the insulating resin substrate is a mask having a predetermined wiring pattern after sticking a photosensitive dry film on the copper foil surface or applying a liquid photosensitive resist. Is formed, a plating resist layer is formed by exposure and development, and then a copper foil in a portion where an etching resist is not formed is etched.

The wiring pattern of the conductor circuit is provided with a large number of lands (pads) formed corresponding to the terminals of the semiconductor chip mounted in the substantially central portion of the substrate and extending from there to the outer peripheral portion of the substrate. It has an outer lead with a fine line width and a large number of lands (pads) formed near the end of the outer lead corresponding to the via hole position. For mounting the semiconductor chip on the former land. The conductive bumps of the other circuit board to be stacked are connected to the latter lands as described later.

The wiring pattern has a thickness of 5 to 30.
The thickness is preferably μm, and more preferably 12 μm. The ratio (L / D) of the line width to the line distance is 50
It is desirable that the thickness is μm / 50 μm to 100 μm / 100 μm. Further, the diameter of the land formed on the wiring pattern is preferably 150 to 500 μm, and particularly preferably 350 μm.

The etching for forming the pattern is
It is performed with at least one selected from an aqueous solution of sulfuric acid-hydrogen peroxide, persulfate, cupric chloride, and ferric chloride.
The roughening layer formed on the surface of the wiring pattern of the conductor circuit improves the adhesion with the adhesive layer that bonds the circuit boards to each other and prevents the occurrence of delamination.

The roughening treatment includes, for example, soft etching treatment, blackening (oxidation) -reduction treatment, formation of needle-like alloy plating made of copper-nickel-phosphorus (trade name Interplate manufactured by EBARA Eugelite), manufactured by MEC. Product name of "Mech
Surface roughening with an etchant called "etch bond" is desirable.

If necessary, a metal layer may be further coated on the wiring pattern on which the roughening layer is formed. The metals formed include titanium, aluminum, zinc,
It may be coated with any metal selected from iron, indium, thallium, cobalt, nickel, tin, lead and bismuth.

The thickness of the coating metal layer is 0.01 to 3 μm.
A range of m is desirable. The reason is that if it is less than 0.01 μm, the roughening layer cannot be completely covered, and if it exceeds 3 μm, the coating metal fills the concave portion of the formed roughening layer, and the roughening layer is offset. This is because it can happen. A particularly desirable range is between 0.03 and 1 μm. As an example, a tin substitution liquid containing tin borofluoride and thiourea may be used to coat the roughening layer.

The adhesive layer formed on the surface of the insulating resin base material opposite to the surface on which the copper foil is adhered is preferably an uncured state obtained by applying a resin to the surface of the substrate and drying it. . This is because, in this embodiment, it is not necessary to make a hole for conduction in the adhesive layer.

It is desirable that the adhesive layer is formed of an organic adhesive, and as the organic adhesive, an epoxy resin, a polyimide resin, a thermosetting polyphenylene ether (PPE: Polyphenylene ether) is used.
r), at least one resin selected from a composite resin of an epoxy resin and a thermoplastic resin, a composite resin of an epoxy resin and a silicone resin, and a BT resin.
Here, as the solvent of the organic adhesive, NMP, DM
F, acetone, ethanol can be used.

A curtain coater, a spin coater, a roll coater, a spray coater, screen printing or the like can be used as a method for applying the uncured resin as the organic adhesive. It is also possible to completely remove the bubbles at the interface between the roughening layer and the resin by applying pressure reduction and defoaming after applying the resin. The formation of the adhesive layer can also be performed by laminating an adhesive sheet. The thickness of the adhesive layer is preferably 5 to 50 μm. The adhesive layer is preferably pre-cured because it is easy to handle.

The semiconductor chip mounted on the circuit board is surface-mounted on the conductor circuit via the first conductive bump. As a method of connecting the bump and the chip, a method of reflowing in a state where the semiconductor chip and the circuit board are aligned, a method of joining the chip and the circuit board in a state where the bump is heated and melted in advance, and the like There is.

The temperature applied at that time is preferably in the range of 60 to 220 ° C. If the temperature is lower than 60 ° C., the conductive metal does not melt, and if the temperature exceeds 220 ° C., the conductive metal forming the bump causes a short circuit between the adjacent bumps.

Particularly in the embodiment in which tin is used as the conductive metal, the temperature in the range of 80 to 200 ° C. is more preferable. This is because if the temperature is within that temperature, the bumps can be maintained in shape-retaining property while being melted for connection.

The sealing resin filled in the gap between the semiconductor chip and the circuit board prevents a mismatch in the coefficient of thermal expansion between the chip and the resin substrate, and is a thermosetting resin, a thermoplastic resin, or an ultraviolet curing resin. Alternatively, a photosensitive resin or the like can be used.

Specifically, a liquid resin containing an epoxy resin, a silicone resin, a polyimide resin, a phenol resin, a fluororesin, or the like, or a non-conductive resin film (for example, NCF) formed by sheet-forming those resins. Etc. can be used.

The circuit board on which the semiconductor chip is mounted is stacked with another circuit board having a substantially similar board structure or a circuit board on which another semiconductor chip is mounted,
A multilayered circuit board is formed.

In the stacking circuit board, except for the circuit board to be stacked as the outermost layer, an opening having a size slightly larger than that of the mounted semiconductor chip is formed in the central portion of the board, and the semiconductor chip is arranged in the opening during stacking. Is configured to be.

That is, in the laminated circuit board, an opening for accommodating a mounted semiconductor chip is formed in the substantially central portion of the insulating resin base material, a conductor circuit is formed on one surface side thereof, and an opening is formed on the other surface side thereof. A via hole reaching the conductor circuit is formed, and a conductive bump electrically connected to an adjacent circuit board is formed immediately above the via hole.

When laminating the semiconductor chip mounting circuit board and the laminating circuit board, a plurality of semiconductor chip mounting circuit boards and the laminating circuit board are alternately arranged, and, for example, the semiconductor chip is disposed at the bottom layer. The mounting circuit board is arranged such that the stacking circuit board is located on the uppermost layer.

When such an arrangement is adopted, since the semiconductor chip is exposed from the central opening of the uppermost layer circuit board, the central portion is provided outside the circuit board of the uppermost layer at the time of lamination. Another stacking circuit board having no opening is arranged, and a copper foil is arranged on the outer side adjacent to the semiconductor chip mounting circuit board in the lowermost layer, and is heat-pressed to be integrated.

The superposition of such circuit boards is carried out while optically detecting the positioning holes previously provided on the respective boards with a CCD camera or the like and performing the positioning.

The above laminated body is pressed at a pressure of 0.5 to 5 MPa while being heated at a temperature of 50 to 250 ° C., and all the circuit boards are integrated by one-time press molding. The heating temperature range is 160 to 200 ° C.
Is preferred.

After being integrated, the copper foil surface of the semiconductor chip mounting circuit board of the lowermost layer is subjected to etching treatment in a state where the protective film is attached to the surface of the uppermost layer of the circuit board for lamination, and the copper foil surface of the lowermost layer is provided outside A conductor circuit having a predetermined wiring pattern is formed.

Then, for example, a nickel-gold layer is formed on the via hole land of the uppermost conductor circuit, a solder bump is provided on the gold-nickel layer, and a solder bump other than the semiconductor chip is provided on the solder bump. It is configured to mount other electronic components, and similarly, for example, a nickel-gold layer is formed also on the via hole band of the lowermost conductor circuit, and a solder ball or a T pin is formed on the gold-nickel layer. Can be joined to form a connection terminal to the motherboard.

Hereinafter, an example of a method of manufacturing a circuit board for mounting a semiconductor chip and a multilayer circuit board according to the present invention will be specifically described with reference to the accompanying drawings.

In manufacturing the circuit board for mounting a semiconductor chip according to the present invention, the one having the copper foil 12 attached to one surface of the insulating resin base material 10 is used as a starting material (see FIG. 1 (a)). This insulating resin base material 10 is, for example, a glass cloth epoxy resin base material, a glass cloth bismaleimide triazine resin base material, a glass cloth polyphenylene ether resin base material, an aramid nonwoven fabric-epoxy resin base material, an aramid nonwoven fabric-polyimide resin base material. Rigid (hard) laminated substrates selected from can be used, but glass cloth epoxy resin substrates are most preferred.

The insulating resin base material 10 has a thickness of 10 to 10.
200 μm is desirable. The reason for this is that if the thickness is less than 10 μm, the strength is reduced and handling becomes difficult, and the reliability of electrical insulation is reduced, and if the thickness exceeds 200 μm, formation of fine via holes and filling of conductive paste are performed. It becomes difficult and the substrate itself becomes thick.

The thickness of the copper foil 12 is preferably 5 to 36 μm. The reason is that, when forming an opening for forming a via hole in an insulating base material by using laser processing as described below, it penetrates if it is too thin, and conversely if it is too thick, it is fine by etching. This is because it is difficult to form a pattern.

As the insulating base material 10 and the copper foil 12, in particular, a glass cloth is impregnated with an epoxy resin to form B.
It is preferable to use a single-sided copper-clad laminate obtained by laminating a prepreg used as a stage and a copper foil and hot pressing. The reason is that the positions of the wiring patterns and the via holes do not shift during handling after the copper foil 12 is etched as described later, and the positional accuracy is excellent.

A protective film 14 is formed on the surface of the insulating substrate 10 opposite to the surface on which the copper foil 12 is attached.
Affix. The protective film 16 is used for adjusting the height of the conductive bump described later, and for example, a polyethylene terephthalate (PET) film having an adhesive layer on the surface can be used.

In the PET film 14, the pressure-sensitive adhesive layer has a thickness of 1 to 20 μm, and the film itself has a thickness of 10 to 50 μm.
Those that are m are used.

Then, laser irradiation is performed from above the PET film 14 attached on the insulating base material 10,
An opening 16 is formed through the PET film 14 to reach the copper foil 12 from the surface of the insulating base material 10 (see FIG. 1 (b)).

This laser processing is carried out by a pulse oscillation type carbon dioxide laser processing apparatus. The laser irradiation conditions are pulse energy of 0.5 to 100 mJ, pulse width of 1 to 100 μs, pulse interval of 0.5 ms or more, and shot. It is desirable that the number is within the range of 3 to 50. The diameter of the opening 16 that can be formed under such processing conditions is preferably 50 to 200 μm.

In order to remove the resin residue remaining on the inner wall surface of the opening 16 formed in the above process, desmear treatment is performed. This desmear treatment includes plasma discharge,
Dry desmear treatment using corona discharge or the like is desirable from the viewpoint of ensuring connection reliability.

Next, after the protective film 18 is attached to the surface of the insulating resin base material 10 to which the copper foil 12 is attached,
Desmeared opening 1 by electrolytic copper plating
A via hole 20 is formed by filling an electrolytic copper-plated film in 6 (see FIG. 1 (c)).

After that, electrolytic tin plating treatment is applied,
An electrolytic tin-plated film is filled in the opening formed in the PET film 14 by laser irradiation, and the second conductive bump 22 for connection to another circuit board is located directly above the via hole 20. Form.

Then, the PET film 14 and the protective film 18 attached to both surfaces of the insulating resin base material 10 are peeled off, and the protective film 26 is applied to the surface of the insulating resin base material opposite to the copper foil sticking surface. Plating resist layer having openings for forming bumps for electrical connection with semiconductor chips by affixing a photosensitive dry film on the copper foil affixing surface of the insulating resin base material and by mask exposure and development processing. 24
(See FIG. 1 (e)), the opening 28 is filled with an electrolytic tin plating film 30 by electrolytic tin plating, and the first conductive bumps for mounting a semiconductor chip on the copper foil 12 are formed. 32 is formed (see FIG. 1 (f)).

Next, an unnecessary portion of the copper foil 12 is removed by etching to form a conductor circuit. In this processing step, first, a photosensitive dry film resist 34 is applied so as to cover the first conductive bumps 32 for mounting semiconductor chips and the copper foil 12 (see FIG. 2 (b)), and then a predetermined circuit pattern is formed. 2) is exposed and developed to form an etching resist layer 38 (see FIG. 2 (c)), and the copper foil in the portion where the etching resist is not formed is etched to form a conductor circuit pattern 40 having a predetermined wiring pattern. (See Fig. 2 (d)).

The etching solution is preferably at least one aqueous solution selected from aqueous solutions of sulfuric acid monohydrogen peroxide, persulfate, cupric chloride and ferric chloride. The land as a part of the conductor circuit has an inner diameter substantially similar to the via hole diameter, but the outer diameter is preferably formed in the range of 150 to 500 μm.

Next, the surface of the conductor circuit 40 formed in the above step is roughened to form a roughened layer 41 (FIG. 2 (e)).
After that, the protective film 26 is peeled off from the surface of the insulating resin base material opposite to the copper foil sticking surface, and the adhesive layer 43 is formed on the surface. This roughening treatment improves the adhesiveness with the adhesive layer when it is made into multiple layers, and peels (delamination).
This is to prevent

As the roughening treatment method, for example, soft etching treatment, blackening (oxidation) -reduction treatment, formation of needle-like alloy plating made of copper-nickel-phosphorus (manufactured by EBARA Eugelite: trade name Interplate), There is surface roughening with an etching solution under the product name "Mech Etch Bond" manufactured by Mech.

In this embodiment, the roughening layer is preferably formed using an etching solution,
For example, it can be formed by etching the surface of the conductor circuit from a mixed aqueous solution of a cupric complex and an organic acid using an etching solution. Such an etching solution can dissolve the copper conductor circuit under oxygen coexisting conditions such as spraying and bubbling, and the reaction is presumed to proceed as follows.

Cu + Cu (II) An → 2Cu (I) An / 2 2Cu (I) An / 2 + n / 4O ₂ + nAH (aeration) → 2Cu (II) An + n / 2H ₂ O In the formula, A is a complexing agent. (Acts as a chelating agent), n represents a coordination number.

As shown in this formula, the generated cuprous complex is dissolved by the action of acid and is combined with oxygen to form a cupric complex, which again contributes to the oxidation of copper. The cupric complex used in the present invention is preferably a cupric complex of azoles. The etching solution containing the organic acid-cupric acid complex can be prepared by dissolving the cupric complex of an azole and the organic acid (halogen ion as necessary) in water.

The etching solution is formed from, for example, an aqueous solution obtained by mixing 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride.

The circuit board for mounting a semiconductor chip according to the present invention is manufactured in accordance with the above-mentioned steps (1) to (3) and further, as shown in FIG. 3, the first conductive bumps 32 of the circuit board and the semiconductor chip 42 are formed. By interposing a sheet-shaped sealing resin 46 between them and, for example, joining the terminal 44 of the semiconductor chip 42 to the first conductive bump 32 in a heating atmosphere, electrical connection between the terminal and the bump can be achieved. At the same time, the gap between the semiconductor chip and the circuit board is sealed with resin, the semiconductor chip is surface-mounted, and the semiconductor chip-mounted circuit board A is manufactured.

Next, a method of manufacturing the single-sided circuit board B laminated on the semiconductor chip mounting circuit board A will be described.
This will be described with reference to FIG.

(1) The insulating resin base material 50 is processed by the same steps as the processing steps (1) to (3) for processing the circuit board for mounting semiconductor chips.
In the state where the opening 56 is formed in the opening 56 and the protective film 58 is attached to the copper foil attachment surface of the insulating resin base material, an electrolytic copper plating film is filled in the opening 56 to form a via hole 60. A conductive bump 62 made of an electrolytic tin-plated film is formed on the hole 60 (see FIGS. 4A to 4D).

(2) Next, the protective film 58 is peeled off, and an etching protective film 64 is attached to the surface of the insulating resin base material opposite to the copper foil attaching surface.
After sticking the photosensitive dry film resist on the surface of
The etching resist layer 68 is formed by exposing and developing along a predetermined circuit pattern, and the copper foil 52 in the portion where the etching resist is not formed is etched to form the via hole 60.
Forming the conductor circuit pattern 70 including the land.

The etching solution is preferably at least one aqueous solution selected from aqueous solutions of sulfuric acid monohydrogen peroxide, persulfate, cupric chloride and ferric chloride. As a pretreatment for forming the conductor circuit 70 by etching the copper foil 52, the entire surface of the copper foil is previously etched to have a thickness of 1 to 1 in order to easily form a fine pattern.
The thickness can be reduced to 0 μm, more preferably 2 to 8 μm.

(3) After the conductor circuit 70 is formed on one surface of the insulating resin base material 50, the surface of the conductor circuit 70 is roughened by the same process as the process for the semiconductor chip mounting circuit board. To form a roughened layer 72, and then
The PET film 54 and the protective film 64 are separated from the surface of the insulating resin base material 50, and the insulating resin base material 5 is further removed.
An opening 74 having substantially the same size as the outer shape of the semiconductor chip is formed at the substantially central portion of 0, and finally, an adhesive layer 76 is formed on the surface of the insulating resin base material 50 on which the conductive bumps 62 are formed (FIG. 4 (e) to (f)).

(4) As described above, the laminated circuit board B manufactured by the steps (1) to (3) has the conductor circuit 70 on one surface of the insulating resin base material 50 and the other. Has a conductive bump 62 on the surface thereof and is alternately laminated with the semiconductor chip mounting circuit board to form a multilayer structure.

The superposition of the above-mentioned circuit boards is carried out while optically detecting a positioning hole previously provided in each board with a CCD camera or the like and performing the positioning. Such a laminate is heated at a temperature of 50 to 250 ° C.,
Pressed with a pressure of 0.5-5 MPa, all circuit boards are integrated by one-time press molding. The heating temperature range is preferably 160 to 200 ° C.

For example, in FIG. 5, four semiconductor chip mounting circuit boards A1 to A4 are connected to four stacking circuit boards B1 to B1.
Another stacking circuit board B5, which is stacked alternately with B4 and has no central opening, is arranged further outside the stacking circuit board B4 of the uppermost layer, and further outside of the semiconductor chip mounting circuit board A1 of the lowermost layer. Is laminated with the copper foil 52 arranged via an adhesive layer. At the time of such stacking, a gap between the substrates surrounding the mounted semiconductor chip is filled with a sealing resin.

FIG. 6 shows a laminated body thus laminated in 9 layers, which are integrated by one-time hot press molding.
By heating at the same time as applying pressure, the adhesive layer provided on each circuit board is cured, and the semiconductor chip mounting circuit boards A1 to A4
And strong adhesion is performed between the laminated circuit boards B1 to B5. It is preferable to use a vacuum hot press as the hot press.

(5) Then, the uppermost laminated circuit board B
After forming the etching resist layer 80 on the copper foil attached to the semiconductor chip mounting circuit board A1 on the surface of 5,
A conductor circuit 82 having a predetermined wiring pattern is formed by etching.

(6) Next, the etching protection film 7
After peeling off 8, the conductor circuit 70 of the laminating circuit board B5
And a nickel-gold layer (not shown) is formed on each via hole land of the conductor circuit 82 of the semiconductor chip mounting circuit board A1, and an electronic component is mounted and mounted on the nickel-gold layer of the conductor circuit 70. On the other hand, the solder bumps 84 are formed on the nickel-gold layer of the conductor circuit 82.
Solder balls 86 or T-shaped pins connected to the terminals on the motherboard side are provided.

In place of the adhesive layer 38 previously formed on the surface of the insulating resin base material, after the single-sided circuit board is manufactured, the second layer of the insulating resin base material is formed at the stage of multilayering.
It is also possible to apply an adhesive to the entire surface of the conductive bump side to form an adhesive layer made of an uncured resin in a dried state. Since this adhesive layer is easy to handle, it is preferably pre-cured, and its thickness is
The range of 5 to 50 μm is desirable.

In the above-described embodiment, four semiconductor chip mounting circuit boards and five stacking circuit boards are used to form a multi-layered structure of nine layers. However, the present invention is not limited to this, and the semiconductor chip to be mounted is not limited to this. Needless to say, it can be applied to the manufacture of a multilayer circuit board having 9 layers or less or 10 layers or more, depending on the size and quantity, the type of insulating resin base material, the thickness, and the like.

[0120]

EXAMPLES (Example 1) (1) A single-sided copper-clad laminate obtained by laminating a prepreg which is a B stage by impregnating a glass cloth with an epoxy resin and a copper foil and heat-pressing the substrate is used as a substrate. To use. The insulating resin substrate 10 has a thickness of 50 μm and a copper foil 12
Had a thickness of 18 μm.

(2) Copper foil 1 of such an insulating substrate 10
22 μm thick on the surface opposite to the surface on which 2 is pasted
Attach the PET film 14 of. This PET film 14 has an adhesive layer having a thickness of 10 μm and a thickness of 12 μm.
PET film base.

(3) Next, a pulsed carbon dioxide laser is irradiated from above the PET film 14 under the following laser processing conditions to form the opening 16 for forming a via hole, and then the inner wall of the opening 16 is formed. A plasma cleaning process was performed to remove the residual resin. [Laser processing conditions] Pulse energy 0.5 to 100 mJ Pulse width 1 to 100 μs Pulse interval 0.5 ms or more Number of shots 3 to 50

(4) Next, after attaching the protective film 18 to the surface of the insulating resin base material 10 on which the copper foil 12 is attached, electrolytic copper plating treatment is performed with an electrolytic plating aqueous solution having the following composition under the following plating conditions. Then, the inside of the opening 16 was filled with electrolytic copper plating to form a via hole 20 having a diameter of 150 μm and a distance between via holes of 500 μm.

[Electrolytic plating aqueous solution] Sulfuric acid 180g / l Copper sulfate 80g / l Additive 1ml / l (Made by Atotech Japan, product name: Kaparaside GL) [Electrolytic plating conditions] Current density 2A / dm^Two 30 minutes Temperature 25 ℃

(5) Next, electrolytic tin plating treatment was performed under the following plating conditions with an electrolytic plating aqueous solution having the following composition, and PE was added.
An electrolytic tin-plated film is filled in the opening formed in the T film 14, and the diameter is 150 μm on the via hole 20.
A second conductive bump 22 having a height of 5 μm and a distance between bumps of 500 μm was formed.

[Electrolytic plating aqueous solution] Sulfuric acid 105 ml / l Tin sulfate (SnSO4) 30g / l Additive 40ml / l [Electrolytic plating conditions] Current density 2A / dm^Two 20 minutes Temperature 25 ℃

(6) After the PET film 14 and the protective film 18 are peeled off, the protective film 26 is attached to the surface of the insulating resin base material opposite to the copper foil attachment surface, and the copper foil of the insulating resin base material is attached. A plating resist layer 24 is formed on the attachment surface, electrolytic tin plating treatment is performed under the following plating conditions with an electrolytic plating aqueous solution having the following composition, and the electrolytic tin plating film 3 is provided in the opening 28.
Filled with 0, and the diameter (bump diameter) is 80 on the copper foil 12.
μm, height 20 μm, distance between bumps (pitch) 14
The 0-micrometer 1st conductive bump 32 was formed.

[Electrolytic plating aqueous solution] Sulfuric acid 105 ml / l Tin sulfate (SnSO4) 30g / l Additive 40ml / l [Electrolytic plating conditions] Current density 4A / dm^Two 50 minutes Temperature 25 ℃

(7) After that, the etching resist layer 38
Is formed, and the copper foil in the portion where the etching resist is not formed is etched to have a diameter of 85 μm under the first conductive bump 32.
L / S (μm) with inner lands of 350 μm and outer lands of 350 μm in diameter at the positions corresponding to the via holes 20.
A conductor circuit pattern 40 having a thickness of 50/50 was formed.

(8) Next, the surface of the conductor circuit 40 is roughened with an etching solution to form a roughened layer 41. After that, the protective film 26 is peeled from the surface opposite to the copper foil sticking surface, and the roughened layer 41 is formed on the surface. The adhesive layer 43 was formed to manufacture a single-sided circuit board for mounting a semiconductor chip.

(9) With the sheet-shaped sealing resin 46 interposed between the one-sided circuit board obtained in (8) and the semiconductor chip 42, the first conductive material is formed by a method such as potting. The semiconductor chip 42 was surface-mounted on the conductive bumps 32 to produce a semiconductor chip mounting circuit board A.

(10) Next, via holes 60 are formed in the insulating resin base material 50 by the same steps as the processing steps for the semiconductor chip mounting circuit board, and the conductive bumps 62 are formed on the via holes 60. To form.

(11) Then, with the etching protection film 64 attached to the surface of the insulating resin base material opposite to the copper foil application surface, the etching resist layer 68 is applied to the surface of the copper foil 52.
Then, the copper foil 52 in the portion where the etching resist is not formed is etched to form the conductor circuit pattern 70 including the land of the via hole 60.

(12) A roughening layer 72 is formed on the surface of the conductor circuit 70 by an etching process, and then an opening 74 is formed at substantially the center of the insulating resin substrate 50. Finally, the conductive bump 62 is formed. An adhesive layer 76 was formed on the surface of the formed insulating resin base material 50 to produce a circuit board B for lamination.

(13) The four semiconductor chip mounting circuit boards A1 to A4 are alternately laminated with the four lamination circuit boards B1 to B4, and the central opening is provided outside the uppermost lamination circuit board B4. While arranging another laminating circuit board B5 in which parts are not formed, and arranging a copper foil on the outside of the semiconductor chip mounting circuit board A1 while injecting a filling resin into the gaps between the boards, While heating at 180 ℃,
All the circuit boards were integrated by one-time press molding by pressing at a pressure of 2 MPa.

(14) An etching protection film 78 is attached to the surface of the laminate circuit board B5, which is the uppermost layer of the laminate obtained in (13) above, and the copper foil surface of the semiconductor chip-mounted circuit board A1 is the lowest layer. After forming an etching resist layer 80 corresponding to a predetermined wiring pattern, a conductor circuit 82 is formed by etching.

(15) Next, a plating resist layer is formed on each of the surface of the uppermost laminated circuit board B5 and the lowermost surface of the semiconductor chip mounted circuit board A1. On each via hole land of circuit 70 and conductor circuit 82, nickel-
A gold layer (not shown) is formed, and a conductor circuit 7 is formed.
On the nickel-gold layer of No. 0, solder bumps 84 for mounting other electronic components are provided, while on the other hand, nickel-gold of the conductor circuit 82 is provided.
Solder balls 8 connected to the terminals of the motherboard on the gold layer
6 was arranged to manufacture a multilayer circuit board having a BGA structure.

(Example 2) Using a conductive paste made of tin-silver based solder which is a low melting point metal, the diameter (bump diameter) was 80 μm, the height was 20 μm, and the distance between bumps (pitch) was determined by printing. The first conductive bump 32 of 140 μm is formed, and the diameter is 150 μm and the height is 5 μm.
m, the second conductive bump 22 having a distance between bumps of 500 μm
A circuit board for mounting a semiconductor chip and a multi-layer circuit board were manufactured in the same manner as in Example 1 except that the above was formed.

The multilayer circuit boards manufactured in Examples 1 and 2 were subjected to a visual inspection and a continuity inspection to check the physical and electrical connectivity. As a result, in Examples 1 and 2, there was no problem in terms of connectivity and adhesiveness, and even under heat cycle conditions, peeling and cracks were not confirmed in the chip and the conductor connection portion up to 1000 cycles, and the resistance value No rise was confirmed.

[0140]

As described above, according to the present invention,
By shortening the distance between semiconductor chips, it is possible to reduce defects caused by wiring resistance and inductance,
As a result, an electric signal can be transmitted at high speed without delay, so that it is possible to achieve high density and high functionality of the wiring board.

[Brief description of drawings]

1A to 1F are views showing a part of a manufacturing process of a circuit board for mounting a semiconductor chip of the present invention.

2A to 2E are views showing a part of a manufacturing process of a semiconductor chip mounting circuit board of the present invention.

FIG. 3 is a diagram showing a part of the manufacturing process of the semiconductor chip mounted circuit board according to the present invention.

4 (a) to 4 (f) are views showing a part of a manufacturing process of a single-sided circuit board to be laminated with a semiconductor chip mounting circuit board according to the present invention.

FIG. 5 is a diagram showing a part of the manufacturing process of the multilayer circuit board in which the semiconductor chip mounting circuit board and the stacking circuit board according to the present invention are stacked.

FIG. 6 is a diagram showing a part of the manufacturing process of the multilayer circuit board in which the semiconductor chip mounting circuit board and the stacking circuit board according to the present invention are stacked.

FIG. 7 is a diagram showing a part of the manufacturing process of the multilayer circuit board in which the semiconductor chip mounting circuit board and the stacking circuit board according to the present invention are stacked.

FIG. 8 is a diagram showing an entire multilayer circuit board according to the present invention.

[Explanation of symbols]

10 Insulating resin base material 12 Copper foil 14 Light-transmissive film 16 openings 18 Protective film 20 Filled via holes 22 Second conductive bump 24 Plating resist layer 26 Protective film 30 Electrolytic tin plating 32 First conductive bump 34 Dry film 38 Plating resist layer 40 conductor circuit 41 Roughened layer 42 semiconductor chips 43 Adhesive layer 46 Sealing resin sheet 70, 82 Conductor circuit 84 Solder bump 86 solder balls A1-A4 Semiconductor chip mounting circuit board B1-B5 Single-sided circuit board for lamination

Claims (15)

[Claims] 1. An insulating resin base material has, on one surface side thereof, a region for mounting a semiconductor chip in a substantially central portion thereof, and a first conductive bump is formed in the mounting region and the first conductive bump is formed. A conductive circuit is extended from the conductive bump 1 toward the peripheral portion of the insulating resin base material, and a conductive substance is filled in the opening reaching the conductive circuit on the other surface side of the insulating resin base material. Circuit for mounting a semiconductor chip, characterized in that a via hole is formed and a second conductive bump electrically connected to another circuit board is provided directly above the via hole. substrate. 2. The insulating resin base material includes, on one surface side thereof, a conductor circuit for mounting a semiconductor chip at a substantially central portion thereof via a first conductive bump, and the conductor circuit comprises the first conductive material. From the conductive bump toward the peripheral portion of the insulating resin base material, and on the other surface side of the insulating resin base material, a via hole formed by filling a conductive material into the opening reaching the conductor circuit. A semiconductor chip-mounted circuit board provided with a second conductive bump formed directly above the via hole and electrically connected to another circuit board. 3. The conductive bumps are made of Sn, Pb, A.
The circuit board according to claim 1 or 2, wherein the circuit board is formed of at least one metal selected from g, Au, Cu, Zn, In, Bi, solder, and tin alloy. 4. The circuit board according to claim 3, wherein the conductive bumps are formed by electrolytic plating or electroless plating. 5. The circuit board according to claim 1, wherein the conductive material is formed of an electrolytic copper plated film, and the conductive bumps are formed of an electrolytic tin plated film. . 6. The circuit board according to claim 1, wherein a roughening layer is formed on a surface of the conductor circuit. 7. A first conductive bump for mounting a semiconductor chip arranged substantially in the center of the base material is formed on a conductor circuit formed on one surface of the insulating resin base material,
A via hole formed by filling a conductive material is provided in an opening reaching the conductor circuit from the other surface of the insulating resin base material, and a second via to be connected to another circuit board is provided on the via hole. In manufacturing a circuit board for mounting a semiconductor chip on which conductive bumps are provided, at least the following steps (1) to (2), that is, other than the insulating resin base material with a copper foil attached to one surface, during the manufacturing process. On the surface side, a step of forming an opening reaching the copper foil, and filling a conductive substance in the opening to form a filled via hole, an electrolytic plating film or a conductive layer located immediately above the filled via hole. Forming a second conductive bump with a conductive paste, a protective film is attached to the other surface of the insulating resin base material, and the semiconductor chip is mounted on substantially the center of one surface of the insulating resin base material. A step of forming a plating resist layer having openings corresponding to terminal positions, electrolytic plating treatment is performed on the insulating resin base material obtained in the above step, and an electrolytic plating film is filled into the openings for mounting. A step of forming a first conductive bump corresponding to a terminal position of a semiconductor chip; extending from the first conductive bump toward a peripheral portion of the insulating resin base material after removing the plating resist layer; Forming an etching resist layer corresponding to a predetermined circuit pattern, and removing the copper foil portion where the etching resist layer is not formed by an etching process to form the predetermined circuit pattern. Method for manufacturing a circuit board for mounting a semiconductor chip. 8. A first conductive bump for mounting a semiconductor chip arranged substantially in the center of the base material is formed on a conductor circuit formed on one surface of the insulating resin base material,
A via hole formed by filling a conductive material is provided in an opening reaching the conductor circuit from the other surface of the insulating resin base material, and a second via to be connected to another circuit board is provided on the via hole. In manufacturing a circuit board for mounting a semiconductor chip on which conductive bumps are provided, at least the following steps (1) to (2), that is, other than the insulating resin base material with a copper foil attached to one surface, during the manufacturing process. A transparent resin film is attached to the surface of the resin film, and laser irradiation is performed from above the resin film to the other surface of the insulating resin base material to form an opening reaching the copper foil, and within the opening. A step of cleaning the remaining residue on the surface of the insulating resin base material covered with a protective film, electrolytic copper plating treatment is performed, and an electrolytic copper plating film is filled in the opening to fill a via hole. Forming step, electrolytic tin plating treatment is performed on the insulating resin base material obtained in the above step to form a second conductive bump made of an electrolytic tin plating film directly above the filled via hole. Step, after peeling the protective film and the resin film from the insulating resin substrate, respectively, affix a protective film to the other surface of the insulating resin substrate, approximately the center of one surface of the insulating resin substrate A step of forming a plating resist layer having an opening corresponding to the terminal position of the mounted semiconductor chip in a portion, electrolytic tin plating treatment is performed on the insulating resin base material obtained in the above step, and an electrolytic tin is formed in the opening. A step of filling a tin-plated film to form a first conductive bump corresponding to a terminal position of a mounted semiconductor chip; removing the plating resist layer, and then removing the first conductive bump from the first conductive bump. RESIN substrate towards the peripheral portion to form an etching resist layer corresponding to a predetermined circuit pattern extending, the copper foil portion that is not the etching resist layer is formed is removed by etching,
A method of manufacturing a circuit board for mounting a semiconductor chip, comprising: forming the predetermined circuit pattern. 9. A conductive circuit is provided on one surface of an insulating resin base material, a via hole reaching the conductive circuit from the other surface of the insulating resin base material is formed, and a conductive bump is provided immediately above the via hole. In a multilayer circuit board manufactured by stacking a plurality of formed circuit boards via an adhesive and heating and pressing the stacked circuit boards, some of the circuit boards A semiconductor chip is mounted on the conductor circuit of the semiconductor chip, and the mounted semiconductor chips are embedded between the circuit board and another adjacent circuit board. 10. A conductive circuit is provided on one surface of an insulating resin base material, a via hole reaching the conductive circuit from the other surface of the insulating resin base material is formed, and a conductive bump is formed immediately above the via hole. In a multilayer circuit board manufactured by stacking a plurality of formed circuit boards via an adhesive and heating and pressing the stacked circuit boards, some of the circuit boards The semiconductor chip is mounted on the conductor circuit in the substantially central portion thereof, and the conductor circuit extends from the terminal position of the mounted semiconductor chip toward the peripheral portion of the circuit board, and the peripheral portion thereof. A multilayer circuit board configured to be connected to the via hole. 11. A conductive circuit is provided on one surface of an insulating resin base material, a via hole reaching the conductive circuit is formed from the other surface of the insulating resin base material, and a conductive bump is provided immediately above the via hole. In a multilayer circuit board manufactured by stacking a plurality of formed circuit boards via an adhesive and heating and pressing the stacked circuit boards, some of the circuit boards The semiconductor chip is mounted on the conductor circuit in the substantially central portion thereof, and the conductor circuit is extended from the terminal position of the mounted semiconductor chip toward the peripheral portion of the circuit board, and in the peripheral portion thereof. On the other hand, another circuit board adjacent to the circuit board on which the semiconductor chip is mounted is configured to be connected to the via hole, and an opening through which the mounted semiconductor chip can pass is formed. Multilayer circuit board, characterized in that There are formed. 12. The conductive bump is made of Sn, Pb, A.
The multilayer circuit board according to any one of claims 9 to 11, which is formed from at least one metal selected from g, Au, Cu, Zn, In, Bi, solder, and tin alloy. 13. The multilayered circuit board according to claim 12, wherein the conductive bumps are formed by electrolytic plating or electroless plating. 14. The via hole is formed by electrolytic copper plating, and the conductive bump is formed by electrolytic tin plating.
The multilayer circuit board according to any one of 1. 15. The multilayered circuit board according to claim 9, wherein a roughening layer is formed on the surface of the conductor circuit.