KR101072412B1 - 표시장치 및 그의 제조방법과, 텔레비젼 장치 - Google Patents
표시장치 및 그의 제조방법과, 텔레비젼 장치 Download PDFInfo
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- KR101072412B1 KR101072412B1 KR1020067013038A KR20067013038A KR101072412B1 KR 101072412 B1 KR101072412 B1 KR 101072412B1 KR 1020067013038 A KR1020067013038 A KR 1020067013038A KR 20067013038 A KR20067013038 A KR 20067013038A KR 101072412 B1 KR101072412 B1 KR 101072412B1
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- conductive layer
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Images
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Abstract
Description
Claims (37)
- 제 1 개구부를 갖는 절연층과,상기 제 1개구부에 설치된 제 1 도전층과,상기 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖는 것을 특징으로 하는 박막 트랜지스터.
- 제 1 개구부를 갖는 절연층과,상기 제 1 개구부에 설치된 제 1 도전층과,상기 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖고,상기 제 2 도전층은 도전성 재료를 사용하는 액적 토출법에 의해 형성되는 것을 특징으로 하는 박막 트랜지스터.
- 제 1 개구부를 갖는 제 1 절연층과,상기 제 1 개구부에 설치된 제 1 도전층과,상기 제 1 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층과,상기 제 2 도전층 위에 게이트 절연막을 개재하여 설치된 반도체층과,상기 반도체층 위에 설치된 제 3 도전층과,상기 제 3 도전층 위에 설치된, 제 2 개구부를 갖는 제 2 절연층과,상기 제 2 개구부에 설치된 제 4 도전층을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 제 1 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖고,상기 제 4 도전층은, 상기 제 3 도전층보다 두꺼운 것을 특징으로 하는 표시장치.
- 제 1 개구부를 갖는 제 1 절연층과,상기 제 1 개구부에 설치된 제 1 도전층과,상기 제 1 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층과,상기 제 2 도전층 위에 게이트 절연막을 개재하여 설치된 반도체층과,상기 반도체층 위에 설치된 제 3 도전층과,상기 제 3 도전층 위에 설치된, 제 2 개구부를 갖는 제 2 절연층과,상기 제 2 개구부에 설치된 제 4 도전층을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 제 1 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖고,상기 제 4 도전층은, 상기 제 3 도전층보다 두꺼우며,상기 제 2 도전층과 상기 제 3 도전층의 각각은 도전성 재료를 사용하는 액적 토출법에 의해 형성되는 것을 특징으로 하는 표시장치.
- 제 1 개구부를 갖는 제 1 절연층과,상기 제 1 개구부에 설치된 제 1 도전층과,상기 제 1 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층과,상기 제 2 도전층 위에 게이트 절연막을 개재하여 설치된 반도체층과,상기 반도체층 위에 설치된 한 쌍의 제 3 도전층과,상기 한 쌍의 제 3 도전층 중 한 개 위에 설치된 제 1 전극과,상기 제 1 전극 위에 설치된 전계 발광층과,상기 전계 발광층 위에 설치된 제 2 전극을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 제 1 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖는 것을 특징으로 하는 표시장치.
- 제 1 개구부를 갖는 제 1 절연층과,상기 제 1 개구부에 설치된 제 1 도전층과,상기 제 1 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층과,상기 제 2 도전층 위에 게이트 절연막을 개재하여 설치된 반도체층과,상기 반도체층 위에 설치된 한 쌍의 제 3 도전층과,상기 한 쌍의 제 3 도전층 중 한 개 위에 설치된 제 1 전극과,상기 제 1 전극 위에 설치된 전계 발광층과,상기 전계 발광층 위에 설치된 제 2 전극을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 제 1 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖고,상기 제 2 도전층은 도전성 재료를 사용하는 액적 토출법에 의해 형성되는 것을 특징으로 하는 표시장치.
- 제 1 개구부를 갖는 제 1 절연층과,상기 제 1 개구부에 설치된 제 1 도전층과,상기 제 1 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층과,상기 제 2 도전층 위에 게이트 절연막을 개재하여 설치된 반도체층과,상기 반도체층 위에 설치된 한 쌍의 제 3 도전층과,상기 한 쌍의 제 3 도전층 중 한 개 위에 설치된 제 1 전극과,상기 한 쌍의 제 3 도전층 중 다른 한 개 위에 설치된, 제 2 개구부를 갖는 제 2 절연층과,상기 제 2 개구부에 설치된 제 4 도전층과,상기 제 1 전극 위에 설치된 전계 발광층과,상기 전계 발광층 위에 설치된 제 2 전극을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 제 1 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖고,상기 제 4 도전층은, 상기 한 쌍의 제 3 도전층보다 두꺼운 것을 특징으로 하는 표시장치.
- 제 1 개구부를 갖는 제 1 절연층과,상기 제 1 개구부에 설치된 제 1 도전층과,상기 제 1 절연층과 상기 제 1 도전층 위에 접촉하여 설치된 제 2 도전층과,상기 제 2 도전층 위에 게이트 절연막을 개재하여 설치된 반도체층과,상기 반도체층 위에 설치된 한 쌍의 제 3 도전층과,상기 한 쌍의 제 3 도전층 중 한 개 위에 설치된 제 1 전극과,상기 한 쌍의 제 3 도전층 중 다른 한 개 위에 설치된, 제 2 개구부를 갖는 제 2 절연층과,상기 제 2 개구부에 설치된 제 4 도전층과,상기 제 1 전극 위에 설치된 전계 발광층과,상기 전계 발광층 위에 설치된 제 2 전극을 구비하고,상기 제 1 도전층은, 수직방향으로 상기 제 2 도전층보다 두꺼우며,상기 제 1 절연층과 상기 제 1 도전층의 표면은, 평탄화되어 균일한 표면을 갖고,상기 제 4 도전층은, 상기 한 쌍의 제 3 도전층보다 두꺼우며,상기 제 2 도전층과 상기 한 쌍의 제 3 도전층의 각각은 도전성 재료를 사용하는 액적 토출법에 의해 형성되는 것을 특징으로 하는 표시장치.
- 제 1항 또는 제 2항에 있어서,상기 박막 트랜지스터는 상기 제1 도전층의 아래에 산화티탄막을 더 구비한 것을 특징으로 하는 박막 트랜지스터.
- 제 1항 또는 제 2항에 있어서,상기 박막 트랜지스터는 상기 제1 도전층의 아래에 W(텅스텐), Al(알루미늄), Ta(탄탈), Zr(지르코늄), Hf(하프늄), Ir(이리듐), Nb(니오븀), Pd(납), Pt(백금), Mo(몰리브덴), Rh(로듐), Sc(스칸듐), Ti(티타늄), V (바나듐), Cr(크롬), Mn(망간), Fe(철), Co(코발트), Ni(니켈), Cu(구리) 및 Zn(아연)로 이루어진 그룹에서 선택된 적어도 한가지를 포함하는 막을 더 구비한 것을 특징으로 하는 박막 트랜지스터.
- 제 1항 또는 제 2항에 있어서,상기 제2 도전층은, 은, 금, 구리, 또는 인듐 주석 산화물 중에서 적어도 한가지를 포함하는 것을 특징으로 하는 박막 트랜지스터.
- 제 3항 또는 제 4항에 있어서,상기 제3 도전층은, 은, 금, 구리, 또는 인듐 주석 산화물 중 적어도 한가지를 포함하는 것을 특징으로 하는 표시장치.
- 제 1항 또는 제 2항에 있어서,상기 제 1 개구부의 폭은, 5㎛ 내지 100㎛인 것을 특징으로 하는 박막 트랜지스터.
- 제 3항 내지 제 8항 중 어느 한 항에 있어서,상기 반도체층은, 수소 및 할로겐 중 적어도 한가지를 포함하는 아모퍼스 반도체층인 것을 특징으로 하는 표시장치.
- 제 3항 내지 제 8항 중 어느 한 항에 있어서,상기 반도체층은, 수소 및 할로겐 중 적어도 한가지를 포함하는 세미아모퍼스 반도체층인 것을 특징으로 하는 표시장치.
- 제 3항 내지 제 8항 중 어느 한 항에 있어서,상기 반도체층이, 수소와 할로겐 중 적어도 한가지를 포함하는 다결정 반도체인 것을 특징으로 하는 표시장치.
- 제 3항 내지 제 8항 중 어느 한 항에 있어서,상기 반도체층의 채널의 길이는 5㎛ 내지 100㎛인 것을 특징으로 하는 표시장치.
- 제 3항 내지 제 8항 중 어느 한 항의 표시장치를 표시 화면으로 구비한 것을 특징으로 하는 텔레비젼 장치.
- 제 1항 또는 제 2항의 박막 트랜지스터를 갖는 표시장치를 표시 화면으로 구비한 것을 특징으로 하는 텔레비젼 장치.
- 제 1 개구부를 갖는 절연층을 형성하는 단계와,상기 제 1 개구부에 제 1 도전층을 형성하는 단계와,상기 절연층 및 상기 제 1 도전층 위에, 제 1 도전성 재료를 사용하는 액적 토출법에 의해, 제 2 도전층을 형성하는 단계와,상기 제 2 도전층 위에 게이트 절연막을 개재하여 반도체층을 형성하는 단계를 포함하고,상기 제 1 도전층이, 상기 제 2 도전층보다, 폭이 넓고 두꺼워지도록 형성하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 1 개구부를 가지는 제 1 절연층을 형성하는 단계와,상기 제 1 개구부에 제1 도전층을 형성하는 단계와,제 1 도전성 재료를 사용하는 액적 토출법에 의해, 상기 제 1 절연층 및 상기 제1 도전층 위에 제2 도전층을 형성하는 단계와,상기 제2 도전층 위에 게이트 절연막을 개재하여 반도체층을 형성하는 단계와,상기 반도체층 위에, 제 2 도전성 재료를 사용하는 액적 토출법에 의해 제3 도전층을 형성하는 단계와,상기 제3 도전층 위에 제2 절연층을 형성하는 단계와,상기 제3 도전층 위에 제4 절연층을 형성하는 단계를 포함하고,상기 제1 도전층은, 상기 제2 도전층보다, 폭이 넓고 두꺼우며,상기 제4 도전층은, 상기 제3 도전층보다, 폭이 넓고 두꺼워지도록 형성하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 1 개구부를 가지는 제 1 절연층을 형성하는 단계와,상기 제 1 개구부에 제1 도전층을 형성하는 단계와,제 1 도전성 재료를 사용하는 액적 토출법에 의해, 상기 제 1 절연층 및 상기 제1 도전층 위에 제2 도전층을 형성하는 단계와,상기 제2 도전층 위에 게이트 절연막을 개재하여 반도체층을 형성하는 단계와,상기 반도체층 위에, 제 2 도전성 재료를 사용하는 액적 토출법에 의해 제3 도전층을 형성하는 단계와,상기 제3 도전층 위에 제1 전극을 형성하는 단계와,상기 제1 전극 위에 전계 발광층을 형성하는 단계와,상기 발광층 위에 제2 전극을 형성하는 단계를 포함하고,상기 제1 도전층은, 상기 제2 도전층보다, 폭이 넓고 두꺼워지도록 형성하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 1 개구부를 가지는 제 1 절연층을 형성하는 단계와,상기 제 1 개구부에 제1 도전층을 형성하는 단계와,제 1 도전성 재료를 사용하는 액적 토출법에 의해, 상기 제 1 절연층 및 상기 제1 도전층 위에 제2 도전층을 형성하는 단계와,상기 제2 도전층 위에 게이트 절연막을 개재하여 반도체층을 형성하는 단계와,상기 반도체층 위에, 제 2 도전성 재료를 사용하는 액적 토출법에 의해 한 쌍의 제3 도전층을 형성하는 단계와,상기 한 쌍의 제3 도전층 중 한 개 위에 제1 전극을 형성하는 단계와,상기 한 쌍의 제3 도전층 중 다른 한 개 위에 제2 절연층을 형성하는 단계와,상기 한 쌍의 제3 도전층 중 상기 다른 한 개 위에 제4 도전층을 형성하는 단계와,상기 제1 전극 위에 전계 발광층을 형성하는 단계와,상기 전계 발광층 위에 제2 전극을 형성하는 단계를 포함하고,상기 제1 도전층은, 상기 제2 도전층보다, 폭이 넓고 두꺼워지도록 형성하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 20항 내지 제 23항 중 어느 한 항에 있어서,상기 제1 도전층의 아래에 산화티탄막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 20항 내지 제 23항 중 어느 한 항에 있어서,상기 제1 도전층의 아래에 W(텅스텐), Al(알루미늄), Ta(탄탈), Zr(지르코늄), Hf(하프늄), Ir(이리듐), Nb(니오븀), Pd(납), Pt(백금), Mo(몰리브덴), Rh(로듐), Sc(스칸듐), Ti(티타늄), V (바나듐), Cr(크롬), Mn(망간), Fe(철), Co(코발트), Ni(니켈), Cu(구리) 및 Zn(아연)으로 이루어진 그룹에서 선택된 적어도 한가지를 포함하는 막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 20항 내지 제 23항 중 어느 한 항에 있어서,상기 제 1 도전성 재료는, 은, 금, 구리, 및 인듐 주석 산화물로 이루어진 그룹에서 선택된 한가지인 것을 특징으로 하는 표시장치의 제조방법.
- 제 22항 또는 제 23항에 있어서,상기 제 2 도전성 재료는, 은, 금, 구리, 및 인듐 주석 산화물로 이루어진 그룹에서 선택된 한가지인 것을 특징으로 하는 표시장치의 제조방법.
- 제 20항 내지 제 23항 중 어느 한 항에 있어서,상기 제 1 개구부의 폭이, 5㎛ 내지 100㎛이 되도록 형성하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 21항 내지 제 23항 중 어느 한 항에 있어서,상기 반도체층은, 수소 및 할로겐 중에서 적어도 한가지를 포함하는 가스로부터 형성된 아모퍼스 반도체층인 것을 특징으로 하는 표시장치의 제조방법.
- 제 21항 내지 제 23항 중 어느 한 항에 있어서,상기 반도체층은, 수소 및 할로겐 중에서 적어도 한가지를 포함하는 가스로부터 형성된 세미아모퍼스 반도체층인 것을 특징으로 하는 표시장치의 제조방법.
- 제 21항 내지 제 23항 중 어느 한 항에 있어서,상기 반도체층은, 수소 및 할로겐 중에서 적어도 한가지를 포함하는 가스로부터 형성된 다결정 반도체층인 것을 특징으로 하는 표시장치의 제조방법.
- 제 21항 내지 제 23항 중 어느 한 항에 있어서,상기 반도체층의 채널의 길이가 5㎛ 내지 100㎛가 되도록 제2 도전층을 형성하는 것을 특징으로 하는 표시장치의 제조방법.
- 제 3항 내지 제 8항 중 어느 한 항에 있어서,상기 표시장치는 상기 제1 도전층의 아래에 산화티탄막을 더 구비한 것을 특징으로 하는 표시장치.
- 제3항 내지 제 8항 중 어느 한 항에 있어서,상기 표시장치는 상기 제1 도전층의 아래에 W(텅스텐), Al(알루미늄), Ta(탄탈), Zr(지르코늄), Hf(하프늄), Ir(이리듐), Nb(니오븀), Pd(납), Pt(백금), Mo(몰리브덴), Rh(로듐), Sc(스칸듐), Ti(티타늄), V (바나듐), Cr(크롬), Mn(망간), Fe(철), Co(코발트), Ni(니켈), Cu(구리) 및 Zn(아연)로 이루어진 그룹에서 선택된 적어도 한가지를 포함하는 막을 더 구비한 것을 특징으로 하는 표시장치.
- 제 3항 내지 제 8항 중 어느 한 항에 있어서,상기 제2 도전층은, 은, 금, 구리, 또는 인듐 주석 산화물 중에서 적어도 한가지를 포함하는 것을 특징으로 하는 표시장치.
- 제 3항 내지 제 8항 중 어느 한 항에 있어서,상기 제 1 개구부의 폭은, 5㎛ 내지 100㎛인 것을 특징으로 하는 표시장치.
- 제 5항 내지 제8항 중 어느 한 항에 있어서,상기 한 쌍의 제3 도전층은, 은, 금, 구리, 또는 인듐 주석 산화물 중에서 적어도 한가지를 포함하는 것을 특징으로 하는 표시장치.
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JP2003403850 | 2003-12-02 | ||
PCT/JP2004/018073 WO2005055178A1 (en) | 2003-12-02 | 2004-11-29 | Display device, method for manufacturing the same, and television apparatus |
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KR (1) | KR101072412B1 (ko) |
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TWI356213B (en) | 2012-01-11 |
CN1890698A (zh) | 2007-01-03 |
KR20060113745A (ko) | 2006-11-02 |
US8742421B2 (en) | 2014-06-03 |
US20070085938A1 (en) | 2007-04-19 |
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TW200521527A (en) | 2005-07-01 |
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