KR101014601B1 - Soi웨이퍼 및 그 제조방법 - Google Patents
Soi웨이퍼 및 그 제조방법 Download PDFInfo
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- KR101014601B1 KR101014601B1 KR1020057021412A KR20057021412A KR101014601B1 KR 101014601 B1 KR101014601 B1 KR 101014601B1 KR 1020057021412 A KR1020057021412 A KR 1020057021412A KR 20057021412 A KR20057021412 A KR 20057021412A KR 101014601 B1 KR101014601 B1 KR 101014601B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S65/00—Glass manufacturing
- Y10S65/08—Quartz
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
- Y10T117/10—Apparatus
Abstract
Description
시료종 |
오프앵글 설정 | 러프네스 측정 결과 | ||
방향 | 각도 | P-V값[nm] | RMS값[nm] | |
비교예1 | [110]만 | 1° | 3.7 | 0.51 |
비교예2 | [110]만 | 3° | 3.0 | 0.44 |
비교예3 | [112]만 | 1° | 3.1 | 0.53 |
비교예4 | [112]만 | 3° | 4.8 | 0.93 |
비교예5 | [111]만 | 1° | 3.1 | 0.57 |
비교예6 | [111]만 | 3° | 4.0 | 0.74 |
실시예 | [001]만 | 1° | 0.99 | 0.11 |
비교예7 | [001]만 | 3° | 5.7 | 0.93 |
비교예8 | [001]만 | 4° | 8.0 | 0.97 |
비교예9 | JUST | +2' 이내 | 2.3 | 0.37 |
Claims (9)
- 적어도 SOI층을 구비하는 SOI웨이퍼에 있어서, 이 SOI층의 면방위가{110}에서 <100>방위만으로 오프앵글된 것이고, 또한 오프앵글 각도가 5분이상 2도이하인 것을 특징으로 하는 SOI웨이퍼.
- 제1항에 있어서,상기 오프앵글 각도가 30분 이상 1도 30분 이하인 것을 특징으로 하는 SOI웨이퍼.
- 적어도, 베이스 웨이퍼와 실리콘 단결정으로 이루어진 본드 웨이퍼를 접합하고, 이 본드 웨이퍼를 박막화하여 SOI층을 형성하는 SOI웨이퍼의 제조 방법에 있어서, 상기 본드 웨이퍼로서 면방위가{110}에서 <100>방향만으로 오프앵글된 것이고, 또한 오프앵글 각도가 5분이상 2도이하인 것을 이용하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제3항에 있어서,상기 얻어진 SOI웨이퍼에 추가로 비산화성 분위기하에서 1000℃이상 1350℃이하의 온도에서 열처리하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제3항에 있어서,상기 본드 웨이퍼는 표면에서 수소이온 또는 희가스 이온 중 적어도 1종류를 주입하여 표면 근방에 이온 주입층이 형성된 것이고, 이 본드 웨이퍼와 상기 베이스 웨이퍼를 접합한 후, 상기 이온 주입층으로 박리하는 것에 의해 상기 본드 웨이퍼의 박막화를 행하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제4항에 있어서,상기 본드 웨이퍼는 표면에서 수소이온 또는 희가스 이온 중 적어도 1종류를 주입하여 표면 근방에 이온 주입층이 형성된 것이고, 이 본드 웨이퍼와 상기 베이스 웨이퍼를 접합한 후, 상기 이온 주입층으로 박리하는 것에 의해 상기 본드 웨이퍼의 박막화를 행하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제3항 내지 제6항 중 어느 한 항에 있어서,상기 본드 웨이퍼와 상기 베이스 웨이퍼를 절연막을 매개로 접합하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제3항 내지 제6항 중 어느 한 항에 있어서,상기 오프앵글 각도가 30분 이상 1도 30분 이하인 것을 이용하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제7항에 있어서,상기 오프앵글 각도가 30분 이상 1도 30분 이하인 것을 이용하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JPJP-P-2003-00137939 | 2003-05-15 | ||
JP2003137939A JP4239676B2 (ja) | 2003-05-15 | 2003-05-15 | Soiウェーハおよびその製造方法 |
Publications (2)
Publication Number | Publication Date |
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KR20060015599A KR20060015599A (ko) | 2006-02-17 |
KR101014601B1 true KR101014601B1 (ko) | 2011-02-16 |
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Application Number | Title | Priority Date | Filing Date |
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KR1020057021412A KR101014601B1 (ko) | 2003-05-15 | 2004-05-07 | Soi웨이퍼 및 그 제조방법 |
Country Status (7)
Country | Link |
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US (1) | US7357839B2 (ko) |
EP (1) | EP1624488B1 (ko) |
JP (1) | JP4239676B2 (ko) |
KR (1) | KR101014601B1 (ko) |
CN (1) | CN100361307C (ko) |
TW (1) | TW200503056A (ko) |
WO (1) | WO2004102668A1 (ko) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US7700488B2 (en) * | 2007-01-16 | 2010-04-20 | International Business Machines Corporation | Recycling of ion implantation monitor wafers |
CN102623304B (zh) * | 2011-01-30 | 2015-03-25 | 陈柏颖 | 适用于纳米工艺的晶圆及其制造方法 |
CN104937433B (zh) | 2012-12-20 | 2018-12-11 | 皇家飞利浦有限公司 | 具有轴向通道的共振陷阱 |
JP6686962B2 (ja) * | 2017-04-25 | 2020-04-22 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
KR20200015086A (ko) | 2018-08-02 | 2020-02-12 | 삼성전자주식회사 | 기판과 이를 포함하는 집적회로 소자 및 그 제조 방법 |
JP7318580B2 (ja) * | 2020-03-30 | 2023-08-01 | 信越半導体株式会社 | Soiウェーハの製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150905A (ja) | 1998-09-04 | 2000-05-30 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2002289819A (ja) | 2001-03-23 | 2002-10-04 | Nippon Steel Corp | Simox基板 |
WO2003032399A1 (fr) | 2001-10-03 | 2003-04-17 | Tokyo Electron Limited | Dispositif semi-conducteur fabrique a la surface de silicium ayant un plan cristallin de direction <110> et procede de production correspondant |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS57112074A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Semiconductor device |
JPS6050970A (ja) | 1983-08-31 | 1985-03-22 | Toshiba Corp | 半導体圧力変換器 |
JPH0775244B2 (ja) * | 1990-11-16 | 1995-08-09 | 信越半導体株式会社 | 誘電体分離基板及びその製造方法 |
JP2653282B2 (ja) | 1991-08-09 | 1997-09-17 | 日産自動車株式会社 | 車両用道路情報表示装置 |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JPH0590117A (ja) * | 1991-09-27 | 1993-04-09 | Toshiba Corp | 単結晶薄膜半導体装置 |
JPH11307747A (ja) | 1998-04-17 | 1999-11-05 | Nec Corp | Soi基板およびその製造方法 |
JPH11307472A (ja) | 1998-04-23 | 1999-11-05 | Shin Etsu Handotai Co Ltd | 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
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- 2003-05-15 JP JP2003137939A patent/JP4239676B2/ja not_active Expired - Fee Related
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2004
- 2004-05-07 CN CNB2004800132274A patent/CN100361307C/zh active Active
- 2004-05-07 US US10/554,960 patent/US7357839B2/en active Active
- 2004-05-07 EP EP04731765.6A patent/EP1624488B1/en active Active
- 2004-05-07 WO PCT/JP2004/006514 patent/WO2004102668A1/ja active Application Filing
- 2004-05-07 KR KR1020057021412A patent/KR101014601B1/ko active IP Right Grant
- 2004-05-13 TW TW093113479A patent/TW200503056A/zh unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000150905A (ja) | 1998-09-04 | 2000-05-30 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
JP2002289819A (ja) | 2001-03-23 | 2002-10-04 | Nippon Steel Corp | Simox基板 |
WO2003032399A1 (fr) | 2001-10-03 | 2003-04-17 | Tokyo Electron Limited | Dispositif semi-conducteur fabrique a la surface de silicium ayant un plan cristallin de direction <110> et procede de production correspondant |
Also Published As
Publication number | Publication date |
---|---|
EP1624488A4 (en) | 2009-10-28 |
KR20060015599A (ko) | 2006-02-17 |
US7357839B2 (en) | 2008-04-15 |
TW200503056A (en) | 2005-01-16 |
TWI327337B (ko) | 2010-07-11 |
CN100361307C (zh) | 2008-01-09 |
CN1791982A (zh) | 2006-06-21 |
EP1624488B1 (en) | 2016-04-06 |
US20060246689A1 (en) | 2006-11-02 |
EP1624488A1 (en) | 2006-02-08 |
JP2004342858A (ja) | 2004-12-02 |
JP4239676B2 (ja) | 2009-03-18 |
WO2004102668A1 (ja) | 2004-11-25 |
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