KR100945952B1 - 기판 판넬 - Google Patents
기판 판넬 Download PDFInfo
- Publication number
- KR100945952B1 KR100945952B1 KR1020070123934A KR20070123934A KR100945952B1 KR 100945952 B1 KR100945952 B1 KR 100945952B1 KR 1020070123934 A KR1020070123934 A KR 1020070123934A KR 20070123934 A KR20070123934 A KR 20070123934A KR 100945952 B1 KR100945952 B1 KR 100945952B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- clamp
- current
- bus line
- bus lines
- Prior art date
Links
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
Claims (2)
- 한 쌍의 클램프 접점과;상기 한 쌍의 클램프 접점의 사이에 위치하는 복수의 버스 라인과;상기 복수의 버스 라인을 통로로 전류를 공급받는 복수의 기판 유닛을 포함하는 기판 판넬에 있어서,상기 복수의 버스 라인에서 각각의 버스 라인 간의 간격은 인접한 클램프 접점으로 갈수록 커지는 것을 특징으로 하는 기판 판넬.
- 제1항에 있어서,상기 클램프 접점과 상기 버스 라인 사이에는 절연부가 형성된 것을 특징으로 하는 기판 판넬.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070123934A KR100945952B1 (ko) | 2007-11-30 | 2007-11-30 | 기판 판넬 |
US12/213,793 US7947909B2 (en) | 2007-11-30 | 2008-06-24 | Substrate panel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020070123934A KR100945952B1 (ko) | 2007-11-30 | 2007-11-30 | 기판 판넬 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20090056683A KR20090056683A (ko) | 2009-06-03 |
KR100945952B1 true KR100945952B1 (ko) | 2010-03-05 |
Family
ID=40674581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020070123934A KR100945952B1 (ko) | 2007-11-30 | 2007-11-30 | 기판 판넬 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7947909B2 (ko) |
KR (1) | KR100945952B1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100986830B1 (ko) * | 2007-11-30 | 2010-10-12 | 삼성전기주식회사 | 기판 판넬 |
US8053676B2 (en) * | 2008-08-14 | 2011-11-08 | Powertech Technology Inc. | Substrate panel having a plurality of substrate strips for semiconductor packages |
AU2009310362A1 (en) * | 2008-11-03 | 2010-05-06 | Cross Match Technologies, Inc. | Apparatus and method for the identification of fake fingerprints |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05315730A (ja) * | 1992-05-13 | 1993-11-26 | Ibiden Co Ltd | プリント配線板 |
JP2000165004A (ja) | 1998-11-27 | 2000-06-16 | Kyocera Corp | 多数個取り配線基板 |
JP2004103811A (ja) | 2002-09-09 | 2004-04-02 | Kyocera Corp | 多数個取り配線基板 |
JP2005209761A (ja) | 2004-01-21 | 2005-08-04 | Sumitomo Metal Electronics Devices Inc | 多数個取り配線基板 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5523921A (en) * | 1994-12-22 | 1996-06-04 | Hewlett-Packard Company | Printed circuit assembly having improved reference plane isolation |
US5629839A (en) * | 1995-09-12 | 1997-05-13 | Allen-Bradley Company, Inc. | Module interconnect adapter for reduced parasitic inductance |
US5973914A (en) * | 1997-03-27 | 1999-10-26 | Siemens Energy & Automation, Inc. | Circuit breaker hold-down |
JPH11163501A (ja) * | 1997-12-02 | 1999-06-18 | Rohm Co Ltd | 電子部品の実装方法、およびその方法によって製造された電子回路装置 |
DE10126734B4 (de) * | 2001-05-31 | 2009-02-26 | Qimonda Ag | Umverdrahtungsverfahren und damit hergestelltes Bauelement |
DE102005051497B3 (de) * | 2005-10-26 | 2006-12-07 | Infineon Technologies Ag | Speichermodul mit einer elektronischen Leiterplatte und einer Mehrzahl von gleichartigen Halbleiterchips |
US7511945B2 (en) * | 2006-05-23 | 2009-03-31 | Robert Peter Bernard Scott | Electrical distribution system |
US7810063B1 (en) * | 2007-02-01 | 2010-10-05 | Cadence Design Systems, Inc. | Graphical user interface for prototyping early instance density |
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2007
- 2007-11-30 KR KR1020070123934A patent/KR100945952B1/ko active IP Right Grant
-
2008
- 2008-06-24 US US12/213,793 patent/US7947909B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05315730A (ja) * | 1992-05-13 | 1993-11-26 | Ibiden Co Ltd | プリント配線板 |
JP2000165004A (ja) | 1998-11-27 | 2000-06-16 | Kyocera Corp | 多数個取り配線基板 |
JP2004103811A (ja) | 2002-09-09 | 2004-04-02 | Kyocera Corp | 多数個取り配線基板 |
JP2005209761A (ja) | 2004-01-21 | 2005-08-04 | Sumitomo Metal Electronics Devices Inc | 多数個取り配線基板 |
Also Published As
Publication number | Publication date |
---|---|
US7947909B2 (en) | 2011-05-24 |
US20090139747A1 (en) | 2009-06-04 |
KR20090056683A (ko) | 2009-06-03 |
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