KR100861650B1 - Semiconductor device with recess gate and method for manufacturing the same - Google Patents

Semiconductor device with recess gate and method for manufacturing the same Download PDF

Info

Publication number
KR100861650B1
KR100861650B1 KR1020070036793A KR20070036793A KR100861650B1 KR 100861650 B1 KR100861650 B1 KR 100861650B1 KR 1020070036793 A KR1020070036793 A KR 1020070036793A KR 20070036793 A KR20070036793 A KR 20070036793A KR 100861650 B1 KR100861650 B1 KR 100861650B1
Authority
KR
South Korea
Prior art keywords
gate
trench
pattern
layer
forming
Prior art date
Application number
KR1020070036793A
Other languages
Korean (ko)
Inventor
김세현
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070036793A priority Critical patent/KR100861650B1/en
Application granted granted Critical
Publication of KR100861650B1 publication Critical patent/KR100861650B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor device having a recess gate and a manufacturing method thereof are provided to prevent an etching effect of a recess gate caused by mis-alignment of the recess gate and a gate pattern. A trench(101) is formed within a semiconductor substrate(100). A recess gate is formed in the inside of the trench. A gate pattern is formed on an upper part of the recess gate. An etch strop layer(105) is formed on a sidewall of an upper end of the recess gate and a sidewall of a lower end of the gate pattern. A silicon growth layer is formed on the semiconductor adjacent to the recess gate. The recess gate includes a gate insulating layer(102) formed on a sidewall and a bottom surface of the trench, and a gate conductive layer(103) formed on the gate insulating layer.

Description

Semiconductor device with recess gate and method for manufacturing thereof {Semiconductor device with recess gate and method for manufacturing the same}

1 is a cross-sectional view of a device for explaining a method of manufacturing a semiconductor device having a recess gate according to the prior art.

2 to 7 are cross-sectional views of devices for describing a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 101 trench

102 gate insulating film 103 first gate conductive film

104: photoresist pattern 105: etching prevention film

106: second gate conductive film 107: metal layer

108: hard mask film 109: spacer

110: substrate growth layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a recess gate and a manufacturing method thereof, and more particularly, to a semiconductor device having a recess gate capable of preventing etching damage due to misalignment and a method of manufacturing the same.

As the degree of integration of integrated circuit semiconductor devices increases and design rules rapidly decrease, the difficulty in securing stable operation of transistors is increasing. For example, as the design rule of the integrated circuit device is reduced, the width of the gate decreases, and thus the channel length of the transistor decreases rapidly. Accordingly, a short channel effect frequently occurs.

Due to this short channel effect, punch-through occurs seriously between the source and the drain of the transistor, which is recognized as a major cause of malfunction of the transistor device. In order to overcome this short channel effect, various methods have been studied to secure the channel length even though the design rule is reduced. In particular, the structure extends the channel length while maintaining the limited gate line width. The recess recesses the semiconductor substrate and the recess region is adopted as the gate structure to further extend the effective channel length. A semiconductor device having a gate has been proposed.

1 is a cross-sectional view of a device for explaining a method of manufacturing a semiconductor device having a recess gate according to the prior art.

Referring to FIG. 1, a portion of the gate region of the semiconductor substrate 10 is etched to form the trench 11. Thereafter, the gate insulating layer 12 is deposited on the entire structure including the trench 11. After the gate conductive film 13, the metal layer 14, and the hard mask film 15 are sequentially stacked on the entire structure including the gate insulating film 12, the hard mask film 15 is patterned. Thereafter, the metal layer 14 and the gate conductive layer 13 are etched by an etching process using the patterned hard mask layer 15 to form a gate pattern. Thereafter, spacers 16 are formed on the sidewalls of the gate patterns. Thereafter, the exposed gate insulating layer 12 is etched to expose the semiconductor substrate 10, and then the exposed semiconductor substrate 10 is grown to form the silicon growth layer 17.

In the semiconductor device according to the related art described above, when misalignment occurs between the gate pattern and the recess gate due to the decrease in the thickness of the spacer due to the integration, the separator of the recess gate and the silicon growth layer formed subsequently is weak and electrically connected. Occurs.

The technical problem to be achieved by the present invention is to form a trench by etching a semiconductor substrate, and then partially fill the trench with a conductive material, and then form an etch stop layer at a corner of the trench opening and subsequently fill the gate with a conductive material. By forming a conductive layer, the recess gate and the gate pattern are prevented from being etched even when misalignment occurs in the recess gate and the gate pattern during the subsequent gate pattern etching process, so that the silicon growth layer and the recess gate that are subsequently formed are electrically separated from each other. A semiconductor device having a recess gate capable of improving characteristics, and a method of manufacturing the same.

In example embodiments, a semiconductor device including a recess gate may include a trench formed in a semiconductor substrate, a recess gate formed in the trench, a gate pattern formed on the recess gate, and a recess gate formed on the recess gate. An etch stop layer formed on a sidewall of an upper end and a sidewall of a lower end of the gate pattern, and a silicon growth layer formed on the semiconductor substrate adjacent to the recess gate.

The recess gate may include a gate insulating layer formed on the trench sidewalls and a bottom surface and a gate conductive layer formed on the gate insulating layer. The gate pattern includes a gate insulating layer, a metal layer, and a hard mask layer sequentially formed on the recess gate. The semiconductor device may further include a spacer formed on the sidewall of the gate pattern. The etch stop layer is formed of a nitride layer.

According to one or more exemplary embodiments, a method of manufacturing a semiconductor device having a recess gate may include forming a trench for a recess gate by etching a predetermined region of the semiconductor substrate, and forming a trench for a recess gate, the bottom surface of the trench and the semiconductor substrate adjacent to the trench. Forming a first gate conductive layer on the top surface, forming an etch stop layer on the sidewall of the upper end portion of the trench and the sidewall of the first gate conductive layer formed on the semiconductor substrate, and forming the first gate conductive layer on the entire structure including the etch stop layer A second gate conductive layer, a metal layer, and a hard mask layer are sequentially stacked to form a gate pattern. The hard mask layer, the metal layer, the second gate conductive layer, and the first gate conductive layer are etched to form a gate pattern. And growing the exposed semiconductor substrate to form a silicon growth layer, wherein the semiconductor substrate is grown with the silicon growth layer. Wherein the film is insulated by the second gate conductive film is formed in the etched trench.

After forming the trench, and before forming the first gate conductive layer, forming a gate insulating layer on the entire structure of the semiconductor substrate including the trench. The gate insulating film is formed of an oxide film.

The forming of the first gate conductive film may include forming a conductive film on the semiconductor substrate, forming a photoresist pattern exposing the trench region on the semiconductor substrate including the conductive film, and the photoresist pattern. And removing the conductive film formed on the trench to form the first gate conductive film on the bottom surface of the trench and the semiconductor substrate adjacent to the trench.

The forming of the etch stop layer may include forming an insulating layer on the entire structure including the first gate conductive layer, and performing a dry etching process having a directivity to form sidewalls of the trench upper end portion and the first substrate formed on the semiconductor substrate. And forming the etch stop layer by remaining the insulating layer formed on a sidewall of the gate conductive layer.

The etch stop layer is formed of a nitride film, the etch stop layer is formed to a thickness of 50 ~ 100Å. The first gate conductive film and the second gate conductive film are formed of a polysilicon film.

The forming of the silicon growth layer may include etching the exposed gate insulating layer to expose the semiconductor substrate, and growing the exposed semiconductor substrate using an SEG method to form the silicon growth layer.

The thickness of the first gate conductive layer formed on the bottom of the trench is 300 to 400 kW.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 to 7 are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2, the trench 101 is formed by etching the gate formation region of the semiconductor substrate 100. The trench 101 is preferably formed at a depth of 3000 Pa to 3400 Pa. Thereafter, the gate insulating film 102 is formed over the entire structure including the trench 101. The gate insulating film 102 is preferably formed of an oxide film.

Referring to FIG. 3, the trench 101 is filled by forming the first gate conductive layer 103 on the entire structure including the gate insulating layer 102. The first gate conductive film 103 is preferably formed of a polysilicon film. Thereafter, after coating the photoresist material, an exposure and a shape process are performed to form a photoresist pattern 104 in which the region where the recess gate is formed is opened.

Referring to FIG. 4, an etching process using a photoresist pattern is performed such that the first gate conductive layer 103 remains on the bottom surface of the trench 101. The thickness of the remaining first gate conductive film 103 is preferably 300 kPa to 400 kPa.

Thereafter, an etch stop layer 105 is formed on the entire structure of the semiconductor substrate including the first gate conductive layer 103. The etch stop layer 105 is preferably formed of a nitride film. The etch stop layer 105 may be formed to a thickness of 50 kPa to 100 kPa.

Referring to FIG. 5, a dry etching process having a directivity is performed to leave an etch stop layer 105 on the upper sidewall of the trench 101 and the sidewall of the first gate conductive layer 103, and then on the bottom surface of the trench 101. The formed first gate conductive layer 103 exposes the upper portion. Thereafter, the second gate conductive film 106, the metal layer 107, and the hard mask film 108 are sequentially stacked on the entire structure including the etch stop film 105. The second gate conductive film 106 is preferably formed of a polysilicon film.

Referring to FIG. 6, the hard mask film 108 is patterned by performing a patterning process. Thereafter, an etching process using the patterned hard mask layer 108 is performed to sequentially etch the metal layer 107, the second gate conductive layer 106, and the first gate conductive layer 103 to form a gate pattern. Form. Thereafter, an insulating film is formed on the entire structure including the gate pattern, and then etched to remain on the sidewall of the gate pattern to form the spacer 109.

Referring to FIG. 7, the exposed gate insulating layer 102 is etched to expose the semiconductor substrate 100. Thereafter, the exposed semiconductor substrate 100 is grown in a manner called Selective Epitaxial Growth (SEG) to form the silicon growth layer 110. At this time, even if misalignment occurs between the recess gate and the mask for etching the gate pattern during the etching process to form the gate pattern during the gate insulating layer etching process, the etching is formed on the lower sidewall portion of the gate pattern and the sidewall portion above the recess gate. Since the recess gate is not exposed by the barrier layer 105, electrical contact with the silicon growth layer 110 may be prevented to improve electrical characteristics of the device.

According to an embodiment of the present invention, after the trench is formed by etching the semiconductor substrate, the trench is partially filled with a conductive material, and then an etch stop layer is formed in the corner portion of the trench opening, and the conductive material is subsequently buried. By forming the gate conductive layer, the recess gate and the gate pattern are prevented from being etched even when misalignment occurs in the recess gate and the gate pattern during the subsequent gate pattern etching process, so that the silicon growth layer and the recess gate formed subsequently are electrically separated from each other. Improve the electrical properties.

Claims (17)

Trenches formed in the semiconductor substrate; A recess gate formed in the trench; A gate pattern formed on the recess gate; An etch stop layer formed on a sidewall of an upper end of the recess gate and a sidewall of a lower end of the gate pattern; And And a silicon growth layer formed on said semiconductor substrate adjacent said recess gate. The method of claim 1, The recess gate may include a gate insulating layer formed on sidewalls and a bottom of the trench; And A semiconductor device comprising a gate conductive film formed on the gate insulating film. The method of claim 1, The gate pattern includes a gate insulating layer, a metal layer, and a hard mask layer sequentially formed on the recess gate. The method of claim 1, The semiconductor device further comprises a spacer formed on the sidewall of the gate pattern. The method of claim 1, The etch stop layer is a semiconductor device formed of a nitride film. The method of claim 1, The etch stop layer is a semiconductor device formed to a thickness of 50 to 100Å. Etching the gate formation region of the semiconductor substrate to form a trench for a recess gate; Forming a first gate conductive layer pattern on a bottom surface of the trench and the semiconductor substrate adjacent to the trench; Forming an etch stop layer on an upper sidewall of the trench and a sidewall of the first gate conductive layer pattern formed on the semiconductor substrate; Etching the second gate conductive layer pattern and the first gate conductive layer pattern on the entire structure including the etch stop layer to form a gate pattern; Forming a silicon growth layer on the semiconductor substrate exposed by the gate pattern. The method of claim 7, wherein Forming a gate insulating film on the entire structure of the semiconductor substrate including the trench after forming the trench and before forming the first gate conductive film. The method of claim 8, And the gate insulating film is formed of an oxide film. The method of claim 7, wherein Forming the first gate conductive layer pattern Forming a conductive film on the semiconductor substrate; And And forming the first gate conductive layer pattern on the bottom surface of the trench and the semiconductor substrate adjacent to the trench using a pattern in which the trench region is exposed. The method of claim 7, wherein Forming the etch stop layer is Forming an insulating film on the entire structure including the first gate conductive film pattern; Forming an etch stop layer by performing an etching process such that the insulating layer remains on the inner sidewall of the trench where the first gate conductive layer pattern is formed and the outer sidewall of the first gate conductive layer pattern formed on the substrate; Method of preparation. The method of claim 11, The etching process is a method of manufacturing a semiconductor device using a dry etching process having a direction. According to claim 7, The etching prevention film is a semiconductor device manufacturing method of forming a nitride film. The method of claim 7, wherein The etch stop layer is a semiconductor device manufacturing method to form a thickness of 50 to 100Å. The method of claim 7, wherein The first gate conductive film pattern and the second gate conductive film are formed of a polysilicon film. The method of claim 7, wherein In the forming of the silicon growth layer, the exposed semiconductor substrate is grown by using an SEG method. The method of claim 7, wherein The thickness of the said 1st gate conductive film formed in the bottom surface of the said trench is 300-400 micrometers, The manufacturing method of the semiconductor element.
KR1020070036793A 2007-04-16 2007-04-16 Semiconductor device with recess gate and method for manufacturing the same KR100861650B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070036793A KR100861650B1 (en) 2007-04-16 2007-04-16 Semiconductor device with recess gate and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070036793A KR100861650B1 (en) 2007-04-16 2007-04-16 Semiconductor device with recess gate and method for manufacturing the same

Publications (1)

Publication Number Publication Date
KR100861650B1 true KR100861650B1 (en) 2008-10-02

Family

ID=40152732

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070036793A KR100861650B1 (en) 2007-04-16 2007-04-16 Semiconductor device with recess gate and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR100861650B1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060066507A (en) * 2004-12-13 2006-06-16 주식회사 하이닉스반도체 Method for forming gate of semiconductor device
KR20070001590A (en) * 2005-06-29 2007-01-04 주식회사 하이닉스반도체 Method for forming recessed gate of semiconductor device
KR20070003136A (en) * 2005-06-30 2007-01-05 주식회사 하이닉스반도체 Semiconductor device with recess gate and method for manufacturing the same
KR20070036977A (en) * 2005-09-30 2007-04-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060066507A (en) * 2004-12-13 2006-06-16 주식회사 하이닉스반도체 Method for forming gate of semiconductor device
KR20070001590A (en) * 2005-06-29 2007-01-04 주식회사 하이닉스반도체 Method for forming recessed gate of semiconductor device
KR20070003136A (en) * 2005-06-30 2007-01-05 주식회사 하이닉스반도체 Semiconductor device with recess gate and method for manufacturing the same
KR20070036977A (en) * 2005-09-30 2007-04-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
KR100745917B1 (en) Method for fabricating semiconductor device
KR100673133B1 (en) Method for fabricating semiconductor device
US8592284B2 (en) Semiconductor device and manufacturing method thereof
KR100924194B1 (en) Semiconductor device and method for fabricating the same
KR20070014610A (en) Method for fabricating semiconductor device
KR100861650B1 (en) Semiconductor device with recess gate and method for manufacturing the same
KR101087918B1 (en) Semiconductor device and method for fabricating the same
KR20090040989A (en) Semiconductor device and method of manufacturing a semiconductor device
KR100275484B1 (en) Method for manufacturing a power device having a trench gate electrode
KR101088818B1 (en) Method for fabricating the semiconductor device
KR100680451B1 (en) Method of forming a contact plug in a semiconductor device
KR20020055147A (en) Method for manufacturing semiconductor device
KR100905463B1 (en) Semiconductor device and method of manufacturing semiconductor device
KR100745924B1 (en) Method for manufacturing semiconductor device
KR100670749B1 (en) Method for manufacturing saddle type transistor
US7374975B2 (en) Method of fabricating a transistor
KR20080029266A (en) Method of manufacturing semiconductor device
KR101169684B1 (en) Transister of semiconductor device and method of manufacturing the same
KR101024754B1 (en) Semiconductor device and method for forming the same
KR100762231B1 (en) Method of fabricating the semiconductor device having recessed channel
KR100939429B1 (en) Semiconductor device and manufacturing method thereof
KR100876833B1 (en) Semiconductor device and method for manufacturing the same
KR100485172B1 (en) Semiconductor device and method for the same
KR101194742B1 (en) Method for forming semiconductor device
KR20060062525A (en) Method of manufacturing semiconducter with gate of recess gate

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee