KR100810203B1 - 반도체 디바이스에서 피처를 패터닝하기 위한 기술 - Google Patents

반도체 디바이스에서 피처를 패터닝하기 위한 기술 Download PDF

Info

Publication number
KR100810203B1
KR100810203B1 KR1020067003310A KR20067003310A KR100810203B1 KR 100810203 B1 KR100810203 B1 KR 100810203B1 KR 1020067003310 A KR1020067003310 A KR 1020067003310A KR 20067003310 A KR20067003310 A KR 20067003310A KR 100810203 B1 KR100810203 B1 KR 100810203B1
Authority
KR
South Korea
Prior art keywords
antireflective material
substrate
feature
features
antireflective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020067003310A
Other languages
English (en)
Korean (ko)
Other versions
KR20060064650A (ko
Inventor
스콧 디. 알렌
캐서리나 이. 바비치
스티븐 제이. 홈즈
아르판 피. 마호로월러
더크 파이퍼
리차드 스테판 와이즈
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR20060064650A publication Critical patent/KR20060064650A/ko
Application granted granted Critical
Publication of KR100810203B1 publication Critical patent/KR100810203B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020067003310A 2003-09-12 2004-05-13 반도체 디바이스에서 피처를 패터닝하기 위한 기술 Expired - Fee Related KR100810203B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/661,041 2003-09-12
US10/661,041 US7030008B2 (en) 2003-09-12 2003-09-12 Techniques for patterning features in semiconductor devices

Publications (2)

Publication Number Publication Date
KR20060064650A KR20060064650A (ko) 2006-06-13
KR100810203B1 true KR100810203B1 (ko) 2008-03-07

Family

ID=34273788

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067003310A Expired - Fee Related KR100810203B1 (ko) 2003-09-12 2004-05-13 반도체 디바이스에서 피처를 패터닝하기 위한 기술

Country Status (7)

Country Link
US (3) US7030008B2 (enExample)
EP (1) EP1665347A1 (enExample)
JP (1) JP4755592B2 (enExample)
KR (1) KR100810203B1 (enExample)
CN (1) CN1849698B (enExample)
TW (1) TWI345803B (enExample)
WO (1) WO2005036625A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010123528A3 (en) * 2008-12-30 2011-01-06 3M Innovative Properties Company Nanostructured articles and methods of making nanostructured articles
US9435916B2 (en) 2008-12-30 2016-09-06 3M Innovative Properties Company Antireflective articles and methods of making the same

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462371B1 (en) * 1998-11-24 2002-10-08 Micron Technology Inc. Films doped with carbon for use in integrated circuit technology
US20040013971A1 (en) * 2001-11-21 2004-01-22 Berger Larry L Antireflective layer for use in microlithography
KR100615583B1 (ko) * 2004-08-11 2006-08-25 삼성전자주식회사 노드 절연막 패턴에 구속된 상전이막 패턴을 갖는 피이.램의 형성방법들
DE102004052611A1 (de) 2004-10-29 2006-05-04 Infineon Technologies Ag Verfahren zur Herstellung einer mit einem Füllmaterial mindestens teilweise gefüllten Öffnung, Verfahren zur Herstellung einer Speicherzelle und Speicherzelle
US7361588B2 (en) * 2005-04-04 2008-04-22 Advanced Micro Devices, Inc. Etch process for CD reduction of arc material
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
US7863150B2 (en) * 2006-09-11 2011-01-04 International Business Machines Corporation Method to generate airgaps with a template first scheme and a self aligned blockout mask
US8026180B2 (en) * 2007-07-12 2011-09-27 Micron Technology, Inc. Methods of modifying oxide spacers
US7888267B2 (en) 2008-02-01 2011-02-15 Tokyo Electron Limited Method for etching silicon-containing ARC layer with reduced CD bias
US7989307B2 (en) * 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
US8409457B2 (en) * 2008-08-29 2013-04-02 Micron Technology, Inc. Methods of forming a photoresist-comprising pattern on a substrate
US8039399B2 (en) * 2008-10-09 2011-10-18 Micron Technology, Inc. Methods of forming patterns utilizing lithography and spacers
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8273634B2 (en) * 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
KR101615787B1 (ko) 2008-12-30 2016-04-26 쓰리엠 이노베이티브 프로퍼티즈 컴파니 나노구조화 표면의 제조 방법
US8268543B2 (en) * 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
US20110129991A1 (en) * 2009-12-02 2011-06-02 Kyle Armstrong Methods Of Patterning Materials, And Methods Of Forming Memory Cells
US8323871B2 (en) * 2010-02-24 2012-12-04 International Business Machines Corporation Antireflective hardmask composition and a method of preparing a patterned material using same
CN102222640B (zh) * 2010-04-16 2013-08-14 中芯国际集成电路制造(上海)有限公司 通孔形成方法
US20110253670A1 (en) * 2010-04-19 2011-10-20 Applied Materials, Inc. Methods for etching silicon-based antireflective layers
US8232198B2 (en) 2010-08-05 2012-07-31 International Business Machines Corporation Self-aligned permanent on-chip interconnect structure formed by pitch splitting
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
US9054160B2 (en) 2011-04-15 2015-06-09 International Business Machines Corporation Interconnect structure and method for fabricating on-chip interconnect structures by image reversal
US8900988B2 (en) 2011-04-15 2014-12-02 International Business Machines Corporation Method for forming self-aligned airgap interconnect structures
US8890318B2 (en) 2011-04-15 2014-11-18 International Business Machines Corporation Middle of line structures
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8822137B2 (en) 2011-08-03 2014-09-02 International Business Machines Corporation Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication
US20130062732A1 (en) 2011-09-08 2013-03-14 International Business Machines Corporation Interconnect structures with functional components and methods for fabrication
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
US9087753B2 (en) 2012-05-10 2015-07-21 International Business Machines Corporation Printed transistor and fabrication method
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9159581B2 (en) * 2012-11-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a semiconductor device using a bottom antireflective coating (BARC) layer
US9153455B2 (en) * 2013-06-19 2015-10-06 Micron Technology, Inc. Methods of forming semiconductor device structures, memory cells, and arrays
US9917027B2 (en) * 2015-12-30 2018-03-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with aluminum via structures and methods for fabricating the same
US10157773B1 (en) * 2017-11-28 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure having layer with re-entrant profile and method of forming the same
US10867842B2 (en) * 2018-10-31 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for shrinking openings in forming integrated circuits
US11398377B2 (en) * 2020-01-14 2022-07-26 International Business Machines Corporation Bilayer hardmask for direct print lithography

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0626205B2 (ja) * 1986-10-08 1994-04-06 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション 複合絶縁層に傾斜のついた開口を形成する方法
US5753418A (en) * 1996-09-03 1998-05-19 Taiwan Semiconductor Manufacturing Company Ltd 0.3 Micron aperture width patterning process
KR100256137B1 (ko) 1996-03-26 2000-05-15 아사무라 타카싯 반도체장치및그제조방법
JP2001242630A (ja) * 2000-01-10 2001-09-07 Internatl Business Mach Corp <Ibm> リソグラフィ構造
US6514867B1 (en) 2001-03-26 2003-02-04 Advanced Micro Devices, Inc. Method of creating narrow trench lines using hard mask

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814406A (en) 1986-02-28 1989-03-21 Katayama Chemical Works Ltd. Scale inhibitor
JP3002033B2 (ja) * 1991-09-27 2000-01-24 株式会社東芝 ドライエッチング方法
JPH0941161A (ja) * 1995-07-26 1997-02-10 Dainippon Printing Co Ltd エッチングを用いた加工方法
US5854503A (en) * 1996-11-19 1998-12-29 Integrated Device Technology, Inc. Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit
KR100280622B1 (ko) * 1998-04-02 2001-03-02 윤종용 반도체 장치의 콘택 형성 방법
US6009888A (en) * 1998-05-07 2000-01-04 Chartered Semiconductor Manufacturing Company, Ltd. Photoresist and polymer removal by UV laser aqueous oxidant
DE19844102C2 (de) * 1998-09-25 2000-07-20 Siemens Ag Herstellverfahren für eine Halbleiterstruktur
JP2000164701A (ja) * 1998-11-25 2000-06-16 Mitsubishi Electric Corp 半導体装置の製造方法
US6159863A (en) * 1999-01-22 2000-12-12 Advanced Micro Devices, Inc. Insitu hardmask and metal etch in a single etcher
US6828259B2 (en) * 2001-03-28 2004-12-07 Advanced Micro Devices, Inc. Enhanced transistor gate using E-beam radiation
US6387798B1 (en) * 2001-06-25 2002-05-14 Institute Of Microelectronics Method of etching trenches for metallization of integrated circuit devices with a narrower width than the design mask profile
KR100415088B1 (ko) * 2001-10-15 2004-01-13 주식회사 하이닉스반도체 반도체장치의 제조방법
JP2003209037A (ja) * 2002-01-11 2003-07-25 Sony Corp アライメントマーク及び半導体装置の製造方法
TW550695B (en) 2002-02-26 2003-09-01 Taiwan Semiconductor Mfg Method to remove bottom anti-reflection coating layer
US6743712B2 (en) * 2002-07-12 2004-06-01 Intel Corporation Method of making a semiconductor device by forming a masking layer with a tapered etch profile
US6853043B2 (en) * 2002-11-04 2005-02-08 Applied Materials, Inc. Nitrogen-free antireflective coating for use with photolithographic patterning
US6774032B1 (en) * 2003-05-30 2004-08-10 Intel Corporation Method of making a semiconductor device by forming a masking layer with a tapered etch profile
US6765254B1 (en) * 2003-06-12 2004-07-20 Advanced Micro Devices, Inc. Structure and method for preventing UV radiation damage and increasing data retention in memory cells

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0626205B2 (ja) * 1986-10-08 1994-04-06 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション 複合絶縁層に傾斜のついた開口を形成する方法
KR100256137B1 (ko) 1996-03-26 2000-05-15 아사무라 타카싯 반도체장치및그제조방법
US5753418A (en) * 1996-09-03 1998-05-19 Taiwan Semiconductor Manufacturing Company Ltd 0.3 Micron aperture width patterning process
JP2001242630A (ja) * 2000-01-10 2001-09-07 Internatl Business Mach Corp <Ibm> リソグラフィ構造
US6514867B1 (en) 2001-03-26 2003-02-04 Advanced Micro Devices, Inc. Method of creating narrow trench lines using hard mask

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010123528A3 (en) * 2008-12-30 2011-01-06 3M Innovative Properties Company Nanostructured articles and methods of making nanostructured articles
US9435916B2 (en) 2008-12-30 2016-09-06 3M Innovative Properties Company Antireflective articles and methods of making the same
US9908772B2 (en) 2008-12-30 2018-03-06 3M Innovative Properties Company Nanostructured articles and methods of making nanostructured articles
US9939557B2 (en) 2008-12-30 2018-04-10 3M Innovative Properties Company Antireflective articles and methods of making the same

Also Published As

Publication number Publication date
CN1849698A (zh) 2006-10-18
EP1665347A1 (en) 2006-06-07
JP2007505492A (ja) 2007-03-08
KR20060064650A (ko) 2006-06-13
JP4755592B2 (ja) 2011-08-24
WO2005036625A1 (en) 2005-04-21
US7030008B2 (en) 2006-04-18
CN1849698B (zh) 2012-07-11
TWI345803B (en) 2011-07-21
TW200523998A (en) 2005-07-16
US20080187731A1 (en) 2008-08-07
US20050056823A1 (en) 2005-03-17
US20060118785A1 (en) 2006-06-08
US7545041B2 (en) 2009-06-09

Similar Documents

Publication Publication Date Title
KR100810203B1 (ko) 반도체 디바이스에서 피처를 패터닝하기 위한 기술
US6316169B1 (en) Methods for reducing profile variation in photoresist trimming
KR100880131B1 (ko) 유기질 저유전율 재료의 에칭 방법
US6007733A (en) Hard masking method for forming oxygen containing plasma etchable layer
US6426300B2 (en) Method for fabricating semiconductor device by using etching polymer
US6019906A (en) Hard masking method for forming patterned oxygen containing plasma etchable layer
CN101266943B (zh) 制造半导体器件的方法及控制系统
US4472237A (en) Reactive ion etching of tantalum and silicon
JP2003506866A (ja) エッチングプロセス用側壁ポリマー形成ガス添加物
US7105442B2 (en) Ashable layers for reducing critical dimensions of integrated circuit features
US20010012592A1 (en) Process for depositing and developing a plasma polymerized organosilicon photoresist film
WO2022100070A1 (zh) 光刻胶的处理方法及自对准双图案化方法
US6913868B2 (en) Conductive bi-layer e-beam resist with amorphous carbon
US6830877B2 (en) Method for forming via and contact holes with deep UV photoresist
TW201025418A (en) Methods of forming a photoresist-comprising pattern on a substrate
US7550390B2 (en) Method and apparatus for dielectric etching during integrated circuit fabrication
JPH11194499A (ja) 半導体装置の製造方法
US20060011578A1 (en) Low-k dielectric etch
KR100281866B1 (ko) 플라즈마 에칭 및 플라즈마 중합을 사용하여 집적 회로를제조함에 있어서의 임계 치수 제어 방법
US20220148879A1 (en) Method for treating photoresist and self-aligned double patterning method
CN114695086A (zh) 形成半导体器件结构的刻蚀方法及半导体器件结构
EP0251566B1 (en) Process for fabricating integrated-circuit devices utilizing multilevel resist structure
KR0172856B1 (ko) 미세패턴 형성방법
JP2001160548A (ja) 半導体装置製造方法および半導体装置製造システム
JP2001210618A (ja) ドライエッチング方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

G170 Re-publication after modification of scope of protection [patent]
PG1701 Publication of correction

St.27 status event code: A-5-5-P10-P19-oth-PG1701

Patent document republication publication date: 20080410

Republication note text: Request for Correction Notice (Document Request)

Gazette number: 1008102030000

Gazette reference publication date: 20080307

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20110110

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

L13-X000 Limitation or reissue of ip right requested

St.27 status event code: A-2-3-L10-L13-lim-X000

U15-X000 Partial renewal or maintenance fee paid modifying the ip right scope

St.27 status event code: A-4-4-U10-U15-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20120228

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20120228