KR100788011B1 - 플립 칩 접속부를 신뢰성 있게 하기 위해 솔더를 사용한유기 패키지 - Google Patents
플립 칩 접속부를 신뢰성 있게 하기 위해 솔더를 사용한유기 패키지 Download PDFInfo
- Publication number
- KR100788011B1 KR100788011B1 KR1020027008119A KR20027008119A KR100788011B1 KR 100788011 B1 KR100788011 B1 KR 100788011B1 KR 1020027008119 A KR1020027008119 A KR 1020027008119A KR 20027008119 A KR20027008119 A KR 20027008119A KR 100788011 B1 KR100788011 B1 KR 100788011B1
- Authority
- KR
- South Korea
- Prior art keywords
- solder
- organic substrate
- carrier member
- tin
- less
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Abstract
Description
EP-A-0 560 276에서는 반도체 소자를 장착하기 위한 캐리어가 개시되어 있는데, 여기에서 캐리어 기판은 유기 유전체 재료이며, 칩의 I/O 패드를 캐리어 상부의 접합 패드에 접속시키는데 사용되는 반도체 소자 상의 솔더는 한 가지 예로 90 %의 납과 10 %의 주석으로 된 납과 주석을 포함한다. 접합 패드 상의 솔더 볼은 63 %의 주석과 37 %의 납을 사용한다.
EP-A-0 446 666에서는 다양한 조성으로 된 유기 기판 상의 솔더 상호 접속부 구조를 개시하였다.
초고집적 반도체 기술과 관련하여 고밀도 및 고효율에 대한 점증하는 필요성으로 인해서 회로 성분과 외부 전기 회로 사이에서의 전기적인 접속에서의 설계 및 구현에 심각한 도전이 되고 있다.
합 금 (wt%) | 고상선 (℃) | 액상선 (℃) | |
대 | 소 | ||
95 Sn / 5 Sb (종래 기술의 합금) | 237 | 243 | --- |
83 Pb / 10 Sb / 5 Sn / 2 Ag | 237 | 239 | 248 |
85 Pb / 11.5 Sb / 3.5 Sn | 240 | 245 | 248 |
85 Pb / 10 Sb / 5 Sn | 240 | 245 | 253 |
82 Pb / 10 Sb / 8 Sn | 244 | 245 | 257 |
Claims (18)
- 소자를 장착하는 캐리어 부재(20)에 있어서,상부면(24)과 하부면(26)을 구비하는 유기 기판(22)과;주석을 포함하되 20 wt% 이하로 포함하고, 재유동 온도가 유기 기판(22)의 분해 온도 이하이며, 장착할 상기 소자를 수용하는 상기 유기 기판(22) 상부면(24)의 다수의 솔더 패드(28)와;유기 기판(22) 상부면(24)의 솔더 패드(28)와 전기적으로 연결되어 있는, 유기 기판(22) 하부면(26)의 다수의 전기적인 접속부(30)를 포함하는 것을 특징으로 하는 캐리어 부재.
- 삭제
- 제 1 항에 있어서,솔더 패드(28)는 주석을 10 wt% 이하 포함하는 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,솔더 패드(28)는 납을 85 wt% 내지 82 wt%, 안티몬을 12 wt% 내지 8 wt%, 주석을 10 wt% 내지 3 wt%, 은을 최대 5 wt%를 포함하는 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,솔더 패드(28)의 재유동 온도는 270 ℃ 이하인 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,솔더 패드(28)의 재유동 온도는 260 ℃ 이하인 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,솔더 패드(28)는 주석을 20 wt% 이하 포함하고, 재유동 온도가 270 ℃ 이하인 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,유기 기판(22)은 라미네이트구조를 포함하는 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,유기 기판(22)은 폴리페닐렌 설파이드, 폴리술폰, 폴리에테르술폰, 폴리아리술폰, 페놀, 폴리아미드, 비스말레이미드-트리아진, 에폭시 또는 이들의 혼합물을 포함하는 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,유기 기판(22)은 비스말레이미드-트리아진 에폭시 라미네이트를 포함하는 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,유기 기판(22)은 성형 플라스틱을 포함하는 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,전기적인 접속부(30)는 금속화 접점, 솔더 볼 또는 핀의 형태인 것을 특징으로 하는 캐리어 부재.
- 제 1 항에 있어서,유기 기판(22)은 비스말레이미드-트리아진 에폭시 라미네이트를 포함하며,솔더 패드(28)는 주석을 20 wt% 이하 포함하고 재유동 온도가 270 ℃ 이하인 것을 특징으로 하는 캐리어 부재.
- 소자 조립체에 있어서,제 1 항의 캐리어 부재(20)와,유기 기판(22)의 솔더 패드(28)를 통해서 캐리어 부재와 전기적으로 연결되고, 표면에 다수의 납땜 가능한 도전성 접점을 구비하는 소자를 포함하는 것을 특징으로 하는 소자 조립체.
- 제 14 항에 있어서,납땜 가능한 접점은 솔더 범프와 전기적으로 연결되어 있는 크롬, 구리 및 금으로 형성된 층 또는 합금을 포함하는 것을 특징으로 하는 소자 조립체.
- 제 15 항에 있어서,소자는 집적 회로 다이인 것을 특징으로 하는 소자 조립체.
- 소자 조립체의 제조 방법에 있어서,제 1 항의 캐리어 부재(20)와 함께 표면에 다수의 납땜 가능한 도전성 접점을 구비한 소자를 정렬하여 소자의 납땜 가능한 도전성 접점이 유기 기판(22) 상부면의 솔더 패드(28)와 정렬되도록 하는 단계와,소자의 납땜 가능한 도전성 접점과 캐리어 부재(20) 사이에 전기적인 접속부를 형성하여 소자 조립체를 형성하는 단계를 포함하는 것을 특징으로 하는 소자 조립체의 제조 방법.
- 제 17 항에 있어서,캐리어 부재(20)를 250 ℃까지 가열하여 캐리어 부재 상의 솔더 패드(28)를 재유동시키는 단계를 추가적으로 포함하는 것을 특징으로 하는 소자 조립체의 제조 방법.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17129999P | 1999-12-21 | 1999-12-21 | |
US60/171,299 | 1999-12-21 | ||
US09/482,102 US20020170746A1 (en) | 2000-01-13 | 2000-01-13 | Organic packages with solders for reliable flip chip connections |
US09/482,102 | 2000-01-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020065601A KR20020065601A (ko) | 2002-08-13 |
KR100788011B1 true KR100788011B1 (ko) | 2007-12-21 |
Family
ID=26866932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020027008119A KR100788011B1 (ko) | 1999-12-21 | 2000-06-15 | 플립 칩 접속부를 신뢰성 있게 하기 위해 솔더를 사용한유기 패키지 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6812570B2 (ko) |
EP (1) | EP1243026A1 (ko) |
JP (1) | JP2003518743A (ko) |
KR (1) | KR100788011B1 (ko) |
WO (1) | WO2001047013A1 (ko) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7531417B2 (en) * | 1998-12-21 | 2009-05-12 | Megica Corporation | High performance system-on-chip passive device using post passivation process |
US6869870B2 (en) * | 1998-12-21 | 2005-03-22 | Megic Corporation | High performance system-on-chip discrete components using post passivation process |
US8421158B2 (en) * | 1998-12-21 | 2013-04-16 | Megica Corporation | Chip structure with a passive device and method for forming the same |
US6303423B1 (en) * | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US8178435B2 (en) | 1998-12-21 | 2012-05-15 | Megica Corporation | High performance system-on-chip inductor using post passivation process |
US6674291B1 (en) * | 2000-10-30 | 2004-01-06 | Agere Systems Guardian Corp. | Method and apparatus for determining and/or improving high power reliability in thin film resonator devices, and a thin film resonator device resultant therefrom |
US6759275B1 (en) * | 2001-09-04 | 2004-07-06 | Megic Corporation | Method for making high-performance RF integrated circuits |
JP3687610B2 (ja) * | 2002-01-18 | 2005-08-24 | セイコーエプソン株式会社 | 半導体装置、回路基板及び電子機器 |
TW550800B (en) * | 2002-05-27 | 2003-09-01 | Via Tech Inc | Integrated circuit package without solder mask and method for the same |
DE10301934A1 (de) * | 2003-01-20 | 2004-07-29 | Epcos Ag | Elektrisches Bauelement mit verringerter Substratfläche |
US8368150B2 (en) * | 2003-03-17 | 2013-02-05 | Megica Corporation | High performance IC chip having discrete decoupling capacitors attached to its IC surface |
US7696611B2 (en) * | 2004-01-13 | 2010-04-13 | Halliburton Energy Services, Inc. | Conductive material compositions, apparatus, systems, and methods |
US7355282B2 (en) | 2004-09-09 | 2008-04-08 | Megica Corporation | Post passivation interconnection process and structures |
US8008775B2 (en) | 2004-09-09 | 2011-08-30 | Megica Corporation | Post passivation interconnection structures |
US8384189B2 (en) * | 2005-03-29 | 2013-02-26 | Megica Corporation | High performance system-on-chip using post passivation process |
CN102157494B (zh) * | 2005-07-22 | 2013-05-01 | 米辑电子股份有限公司 | 线路组件 |
US9711926B2 (en) * | 2013-11-19 | 2017-07-18 | Lear Corporation | Method of forming an interface for an electrical terminal |
CN112338387B (zh) * | 2015-09-17 | 2022-12-02 | 富士电机株式会社 | 半导体装置用软钎焊材料 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0560276A2 (en) * | 1992-03-09 | 1993-09-15 | International Business Machines Corporation | IC chip attachment |
KR19980068190A (ko) * | 1997-02-17 | 1998-10-15 | 김광호 | 자동 적층 및 솔더링 장치 및 3차원 적층형 패키지 소자 제조 방법 |
KR20010004528A (ko) * | 1999-06-29 | 2001-01-15 | 김영환 | 웨이퍼 레벨 패키지 및 그의 제조 방법 |
KR20020009087A (ko) * | 2000-07-24 | 2002-02-01 | 한신혁 | 반도체 패키지 및 그 패키지 방법 |
Family Cites Families (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1483574A (ko) * | 1965-06-24 | 1967-09-06 | ||
US4170472A (en) * | 1977-04-19 | 1979-10-09 | Motorola, Inc. | Solder system |
US4290079A (en) * | 1979-06-29 | 1981-09-15 | International Business Machines Corporation | Improved solder interconnection between a semiconductor device and a supporting substrate |
US4824009A (en) * | 1981-12-31 | 1989-04-25 | International Business Machines Corporation | Process for braze attachment of electronic package members |
CA1302947C (en) * | 1985-09-13 | 1992-06-09 | Jerome S. Sallo | Copper-chromium-polyimide composite |
US5074947A (en) * | 1989-12-18 | 1991-12-24 | Epoxy Technology, Inc. | Flip chip technology using electrically conductive polymers and dielectrics |
JP2891432B2 (ja) * | 1989-12-27 | 1999-05-17 | 田中電子工業株式会社 | 半導体材料の接続方法,それに用いる接続材料及び半導体装置 |
US5948533A (en) * | 1990-02-09 | 1999-09-07 | Ormet Corporation | Vertically interconnected electronic assemblies and compositions useful therefor |
US5121190A (en) * | 1990-03-14 | 1992-06-09 | International Business Machines Corp. | Solder interconnection structure on organic substrates |
GB9014491D0 (en) * | 1990-06-29 | 1990-08-22 | Digital Equipment Int | Mounting silicon chips |
US5154341A (en) * | 1990-12-06 | 1992-10-13 | Motorola Inc. | Noncollapsing multisolder interconnection |
JPH04241443A (ja) * | 1991-01-16 | 1992-08-28 | Hitachi Chem Co Ltd | 半導体装置及びその製造法 |
US5102829A (en) * | 1991-07-22 | 1992-04-07 | At&T Bell Laboratories | Plastic pin grid array package |
US5288944A (en) * | 1992-02-18 | 1994-02-22 | International Business Machines, Inc. | Pinned ceramic chip carrier |
US5535101A (en) * | 1992-11-03 | 1996-07-09 | Motorola, Inc. | Leadless integrated circuit package |
US5479319A (en) * | 1992-12-30 | 1995-12-26 | Interconnect Systems, Inc. | Multi-level assemblies for interconnecting integrated circuits |
US5303862A (en) * | 1992-12-31 | 1994-04-19 | International Business Machines Corporation | Single step electrical/mechanical connection process for connecting I/O pins and creating multilayer structures |
JP3356840B2 (ja) * | 1993-10-14 | 2002-12-16 | 富士通株式会社 | 電気的接続装置及びその形成方法 |
EP0652072A1 (en) * | 1993-11-09 | 1995-05-10 | Matsushita Electric Industrial Co., Ltd. | Solder |
US5521440A (en) * | 1994-05-25 | 1996-05-28 | Crosspoint Solutions, Inc. | Low-capacitance, plugged antifuse and method of manufacture therefor |
US5468995A (en) * | 1994-07-05 | 1995-11-21 | Motorola, Inc. | Semiconductor device having compliant columnar electrical connections |
US5907187A (en) * | 1994-07-18 | 1999-05-25 | Kabushiki Kaisha Toshiba | Electronic component and electronic component connecting structure |
AU3415095A (en) * | 1994-09-06 | 1996-03-27 | Sheldahl, Inc. | Printed circuit substrate having unpackaged integrated circuit chips directly mounted thereto and method of manufacture |
US5542174A (en) * | 1994-09-15 | 1996-08-06 | Intel Corporation | Method and apparatus for forming solder balls and solder columns |
US5468655A (en) * | 1994-10-31 | 1995-11-21 | Motorola, Inc. | Method for forming a temporary attachment between a semiconductor die and a substrate using a metal paste comprising spherical modules |
US5625166A (en) * | 1994-11-01 | 1997-04-29 | Intel Corporation | Structure of a thermally and electrically enhanced plastic pin grid array (PPGA) package for high performance devices with wire bond interconnect |
US5541450A (en) * | 1994-11-02 | 1996-07-30 | Motorola, Inc. | Low-profile ball-grid array semiconductor package |
US5655703A (en) * | 1995-05-25 | 1997-08-12 | International Business Machines Corporation | Solder hierarchy for chip attachment to substrates |
US5598036A (en) * | 1995-06-15 | 1997-01-28 | Industrial Technology Research Institute | Ball grid array having reduced mechanical stress |
JP3123638B2 (ja) * | 1995-09-25 | 2001-01-15 | 株式会社三井ハイテック | 半導体装置 |
JP3311215B2 (ja) * | 1995-09-28 | 2002-08-05 | 株式会社東芝 | 半導体装置 |
US6224690B1 (en) * | 1995-12-22 | 2001-05-01 | International Business Machines Corporation | Flip-Chip interconnections using lead-free solders |
US5847929A (en) * | 1996-06-28 | 1998-12-08 | International Business Machines Corporation | Attaching heat sinks directly to flip chips and ceramic chip carriers |
US5868304A (en) * | 1996-07-02 | 1999-02-09 | International Business Machines Corporation | Socketable bump grid array shaped-solder on copper spheres |
JPH1041621A (ja) * | 1996-07-18 | 1998-02-13 | Fujitsu Ltd | 錫−ビスマスはんだの接合方法 |
US5831336A (en) * | 1996-07-25 | 1998-11-03 | International Business Machines Corporation | Ternary solder for the enhancement of C-4 fatigue life |
US5804771A (en) * | 1996-09-26 | 1998-09-08 | Intel Corporation | Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces |
JPH10209618A (ja) * | 1997-01-16 | 1998-08-07 | Sanken Electric Co Ltd | 回路基板装置及びその製造方法 |
US5798563A (en) * | 1997-01-28 | 1998-08-25 | International Business Machines Corporation | Polytetrafluoroethylene thin film chip carrier |
FI970822A (fi) * | 1997-02-27 | 1998-08-28 | Nokia Mobile Phones Ltd | Menetelmä ja järjestely komponentin liittämiseksi |
US5834839A (en) * | 1997-05-22 | 1998-11-10 | Lsi Logic Corporation | Preserving clearance between encapsulant and PCB for cavity-down single-tier package assembly |
US5990564A (en) * | 1997-05-30 | 1999-11-23 | Lucent Technologies Inc. | Flip chip packaging of memory chips |
US5847936A (en) * | 1997-06-20 | 1998-12-08 | Sun Microsystems, Inc. | Optimized routing scheme for an integrated circuit/printed circuit board |
US5959348A (en) * | 1997-08-18 | 1999-09-28 | International Business Machines Corporation | Construction of PBGA substrate for flip chip packing |
JPH1174649A (ja) * | 1997-08-28 | 1999-03-16 | Kyocera Corp | 配線基板およびその製造方法 |
US6369451B2 (en) * | 1998-01-13 | 2002-04-09 | Paul T. Lin | Solder balls and columns with stratified underfills on substrate for flip chip joining |
US6080650A (en) * | 1998-02-04 | 2000-06-27 | Texas Instruments Incorporated | Method and apparatus for attaching particles to a substrate |
US6013877A (en) * | 1998-03-12 | 2000-01-11 | Lucent Technologies Inc. | Solder bonding printed circuit boards |
US6337445B1 (en) * | 1998-03-16 | 2002-01-08 | Texas Instruments Incorporated | Composite connection structure and method of manufacturing |
JP3876953B2 (ja) * | 1998-03-27 | 2007-02-07 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US5938862A (en) * | 1998-04-03 | 1999-08-17 | Delco Electronics Corporation | Fatigue-resistant lead-free alloy |
US6108212A (en) * | 1998-06-05 | 2000-08-22 | Motorola, Inc. | Surface-mount device package having an integral passive component |
JP3975569B2 (ja) * | 1998-09-01 | 2007-09-12 | ソニー株式会社 | 実装基板及びその製造方法 |
US6127731A (en) * | 1999-03-11 | 2000-10-03 | International Business Machines Corporation | Capped solder bumps which form an interconnection with a tailored reflow melting point |
US6225687B1 (en) * | 1999-09-02 | 2001-05-01 | Intel Corporation | Chip package with degassing holes |
US6229207B1 (en) * | 2000-01-13 | 2001-05-08 | Advanced Micro Devices, Inc. | Organic pin grid array flip chip carrier package |
AU2001271290A1 (en) * | 2000-06-09 | 2001-12-24 | International Rectifier Corporation | Dynamic motor drive torque control based on power switching device temperature feedback |
US6527563B2 (en) * | 2000-10-04 | 2003-03-04 | Gary A. Clayton | Grid interposer |
-
2000
- 2000-06-15 KR KR1020027008119A patent/KR100788011B1/ko active IP Right Grant
- 2000-06-15 WO PCT/US2000/016787 patent/WO2001047013A1/en active Application Filing
- 2000-06-15 JP JP2001547649A patent/JP2003518743A/ja active Pending
- 2000-06-15 EP EP00942923A patent/EP1243026A1/en not_active Ceased
-
2002
- 2002-06-28 US US10/184,061 patent/US6812570B2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0560276A2 (en) * | 1992-03-09 | 1993-09-15 | International Business Machines Corporation | IC chip attachment |
KR19980068190A (ko) * | 1997-02-17 | 1998-10-15 | 김광호 | 자동 적층 및 솔더링 장치 및 3차원 적층형 패키지 소자 제조 방법 |
KR20010004528A (ko) * | 1999-06-29 | 2001-01-15 | 김영환 | 웨이퍼 레벨 패키지 및 그의 제조 방법 |
KR20020009087A (ko) * | 2000-07-24 | 2002-02-01 | 한신혁 | 반도체 패키지 및 그 패키지 방법 |
Also Published As
Publication number | Publication date |
---|---|
US20030037959A1 (en) | 2003-02-27 |
WO2001047013A1 (en) | 2001-06-28 |
KR20020065601A (ko) | 2002-08-13 |
US6812570B2 (en) | 2004-11-02 |
EP1243026A1 (en) | 2002-09-25 |
JP2003518743A (ja) | 2003-06-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100788011B1 (ko) | 플립 칩 접속부를 신뢰성 있게 하기 위해 솔더를 사용한유기 패키지 | |
US6583515B1 (en) | Ball grid array package for enhanced stress tolerance | |
US6994243B2 (en) | Low temperature solder chip attach structure and process to produce a high temperature interconnection | |
US5956606A (en) | Method for bumping and packaging semiconductor die | |
US7759240B2 (en) | Use of palladium in IC manufacturing with conductive polymer bump | |
US6414849B1 (en) | Low stress and low profile cavity down flip chip and wire bond BGA package | |
US20020114143A1 (en) | Chip-scale packages stacked on folded interconnector for vertical assembly on substrates | |
US6163462A (en) | Stress relief substrate for solder ball grid array mounted circuits and method of packaging | |
US20020047216A1 (en) | Ball grid array | |
US6683387B1 (en) | Flip chip carrier package with adapted landing pads | |
US6229207B1 (en) | Organic pin grid array flip chip carrier package | |
EP1457098A1 (en) | Ball grid array package | |
US6984792B2 (en) | Dielectric interposer for chip to substrate soldering | |
US7545028B2 (en) | Solder ball assembly for a semiconductor device and method of fabricating same | |
JPH08288291A (ja) | 半導体装置 | |
US20020170746A1 (en) | Organic packages with solders for reliable flip chip connections | |
JP3838530B2 (ja) | 半導体装置の製造方法 | |
KR20020065602A (ko) | 스루 홀 핀이 배열된 유기 플립 칩 패키지 | |
JP2858760B2 (ja) | 有機無機複合多層基板 | |
JP3469093B2 (ja) | 印刷回路基板および実装回路基板の製造方法 | |
KR20020053422A (ko) | 반도체칩의 도전성범프 구조 및 그 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121129 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20131119 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20141124 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20151118 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20161123 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20171117 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20181115 Year of fee payment: 12 |