KR100727794B1 - 이중 다마신 구조 및 캐패시터를 포함하는 집적회로의 제조 공정 - Google Patents

이중 다마신 구조 및 캐패시터를 포함하는 집적회로의 제조 공정 Download PDF

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Publication number
KR100727794B1
KR100727794B1 KR1020010034116A KR20010034116A KR100727794B1 KR 100727794 B1 KR100727794 B1 KR 100727794B1 KR 1020010034116 A KR1020010034116 A KR 1020010034116A KR 20010034116 A KR20010034116 A KR 20010034116A KR 100727794 B1 KR100727794 B1 KR 100727794B1
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KR
South Korea
Prior art keywords
capacitor
layer
openings
dual damascene
damascene structure
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KR1020010034116A
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English (en)
Korean (ko)
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KR20010113520A (ko
Inventor
사일레스치티페디
Original Assignee
에이저 시스템즈 가디언 코포레이션
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Publication of KR20010113520A publication Critical patent/KR20010113520A/ko
Application granted granted Critical
Publication of KR100727794B1 publication Critical patent/KR100727794B1/ko
Assigned to 에이저 시스템즈 엘엘시 reassignment 에이저 시스템즈 엘엘시 권리의 전부이전등록 Assignors: 에이저 시스템즈 가디언 코포레이션
Assigned to 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 reassignment 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 권리의 전부이전등록 Assignors: 에이저 시스템즈 엘엘시
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020010034116A 2000-06-16 2001-06-16 이중 다마신 구조 및 캐패시터를 포함하는 집적회로의 제조 공정 Expired - Lifetime KR100727794B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/596,382 US6762087B1 (en) 2000-06-16 2000-06-16 Process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor
US09/596,382 2000-06-16

Publications (2)

Publication Number Publication Date
KR20010113520A KR20010113520A (ko) 2001-12-28
KR100727794B1 true KR100727794B1 (ko) 2007-06-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010034116A Expired - Lifetime KR100727794B1 (ko) 2000-06-16 2001-06-16 이중 다마신 구조 및 캐패시터를 포함하는 집적회로의 제조 공정

Country Status (5)

Country Link
US (1) US6762087B1 (https=)
JP (1) JP2002043433A (https=)
KR (1) KR100727794B1 (https=)
GB (1) GB2368722B (https=)
TW (1) TWI256683B (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120223413A1 (en) 2011-03-04 2012-09-06 Nick Lindert Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer
JP2013026599A (ja) * 2011-07-26 2013-02-04 Elpida Memory Inc 半導体装置の製造方法
WO2016182782A1 (en) 2015-05-08 2016-11-17 Cirrus Logic International Semiconductor Ltd. High denstiy capacitors formed from thin vertical semiconductor structures such as finfets

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000159698A (ja) * 1998-11-30 2000-06-13 Matsushita Electric Ind Co Ltd 芳香族メチリデン化合物、それを製造するための芳香族アルデヒド化合物、及びそれらの製造方法
US6664185B1 (en) * 2002-04-25 2003-12-16 Advanced Micro Devices, Inc. Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633781A (en) 1995-12-22 1997-05-27 International Business Machines Corporation Isolated sidewall capacitor having a compound plate electrode
US6025226A (en) * 1998-01-15 2000-02-15 International Business Machines Corporation Method of forming a capacitor and a capacitor formed using the method
US6251740B1 (en) * 1998-12-23 2001-06-26 Lsi Logic Corporation Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit
US6156640A (en) 1998-07-14 2000-12-05 United Microelectronics Corp. Damascene process with anti-reflection coating
TW374948B (en) 1998-07-28 1999-11-21 United Microelectronics Corp Method of prevention of poisoning trenches in dual damascene process structures and dielectric layer windows
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6037216A (en) 1998-11-02 2000-03-14 Vanguard International Semiconductor Corporation Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process
TW389993B (en) 1998-11-18 2000-05-11 United Microelectronics Corp Method for producing thin film resistance of dual damascene interconnect
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6320244B1 (en) 1999-01-12 2001-11-20 Agere Systems Guardian Corp. Integrated circuit device having dual damascene capacitor
US6346454B1 (en) * 1999-01-12 2002-02-12 Agere Systems Guardian Corp. Method of making dual damascene interconnect structure and metal electrode capacitor
US6365327B1 (en) 1999-08-30 2002-04-02 Agere Systems Guardian Corp. Process for manufacturing in integrated circuit including a dual-damascene structure and an integrated circuit
US6313025B1 (en) 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
US6281134B1 (en) 1999-10-22 2001-08-28 United Microelectronics Corp. Method for combining logic circuit and capacitor
US6228711B1 (en) * 1999-11-30 2001-05-08 United Microelectronics Corp. Method of fabricating dynamic random access memory
US6383858B1 (en) * 2000-02-16 2002-05-07 Agere Systems Guardian Corp. Interdigitated capacitor structure for use in an integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000159698A (ja) * 1998-11-30 2000-06-13 Matsushita Electric Ind Co Ltd 芳香族メチリデン化合物、それを製造するための芳香族アルデヒド化合物、及びそれらの製造方法
US6664185B1 (en) * 2002-04-25 2003-12-16 Advanced Micro Devices, Inc. Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect

Also Published As

Publication number Publication date
GB2368722B (en) 2004-12-01
GB2368722A (en) 2002-05-08
KR20010113520A (ko) 2001-12-28
GB0114308D0 (en) 2001-08-01
US6762087B1 (en) 2004-07-13
TWI256683B (en) 2006-06-11
JP2002043433A (ja) 2002-02-08

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