KR100726762B1 - 반도체 리드프레임과 이를 채용한 반도체 패키지 - Google Patents
반도체 리드프레임과 이를 채용한 반도체 패키지 Download PDFInfo
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- KR100726762B1 KR100726762B1 KR1020000079731A KR20000079731A KR100726762B1 KR 100726762 B1 KR100726762 B1 KR 100726762B1 KR 1020000079731 A KR1020000079731 A KR 1020000079731A KR 20000079731 A KR20000079731 A KR 20000079731A KR 100726762 B1 KR100726762 B1 KR 100726762B1
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- lead
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- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (4)
- 다수개의 리이드;와,상기 리이드의 상하면중 적어도 어느 한면 이상에 형성되는 제1 몰딩재;와,다이패드상에 접착제를 매개로 하여 장착되는 반도체 칩;과,상기 리이드와 반도체 칩을 와이어본딩시키는 와이어;와,상기 리이드의 일부에 연결되어서, 외부기판의 단자와 전기적으로 접속되는 솔더 볼;과,상기 리이드와 반도체 칩을 감싸는 제2 몰딩재;를 포함하고,상기 제1 몰딩재는 상기 반도체 칩과 와이어본딩되는 리이드의 상면중 반도체 칩과 리이드가 본딩되는 부분을 제외한 영역과, 반도체 칩과 리이드 사이의 영역과, 상기 리이드의 하면중 상기 솔더볼과 접속되는 부분을 제외한 영역에 몰딩되고,상기 제2 몰딩재는 상기 리이드와 반도체 칩이 와이어본딩되는 부분에 몰딩된 것을 특징으로 하는 반도체 패키지.
- 삭제
- 다수개로 형성되어 일면이 반도체 칩과 와이어본딩되고, 다른 면이 외부기판의 단자와 전기적으로 접속되는 리이드;와,상기 리이드의 상하면중 적어도 어느 한면이상에 형성되는 몰딩재;를 포함하고,상기 몰딩재는 리이드중에서 반도체 칩과 와이어본딩되는 상면에는 와이어본딩되는 부분을 제외한 영역과, 반도체 칩과 리이드 사이의 영역과, 그 반대면에는 외부기판의 단자와 접속되는 부분을 제외하고 형성된 것을 특징으로 하는 반도체 리드프레임.
- 삭제
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020000079731A KR100726762B1 (ko) | 2000-12-21 | 2000-12-21 | 반도체 리드프레임과 이를 채용한 반도체 패키지 |
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KR1020000079731A KR100726762B1 (ko) | 2000-12-21 | 2000-12-21 | 반도체 리드프레임과 이를 채용한 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
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KR20020050556A KR20020050556A (ko) | 2002-06-27 |
KR100726762B1 true KR100726762B1 (ko) | 2007-06-11 |
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KR1020000079731A KR100726762B1 (ko) | 2000-12-21 | 2000-12-21 | 반도체 리드프레임과 이를 채용한 반도체 패키지 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100891649B1 (ko) * | 2002-08-08 | 2009-04-02 | 삼성테크윈 주식회사 | 반도체 패키지 제조방법 |
US7759807B2 (en) | 2006-11-21 | 2010-07-20 | Hynix Semiconductor Inc. | Semiconductor package having structure for warpage prevention |
KR100762913B1 (ko) * | 2006-11-21 | 2007-10-08 | 주식회사 하이닉스반도체 | 반도체 패키지 |
TWI535346B (zh) * | 2014-12-10 | 2016-05-21 | 上海兆芯集成電路有限公司 | 線路基板和封裝結構 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5334873A (en) * | 1991-05-11 | 1994-08-02 | Goldstar Electron Co., Ltd. | Semiconductor packages with centrally located electrode pads |
JPH0883878A (ja) * | 1994-09-09 | 1996-03-26 | Kawasaki Steel Corp | 半導体icチップのパッケージ及びその製造方法並びにリード・フレーム |
JPH08148603A (ja) * | 1994-11-22 | 1996-06-07 | Nec Kyushu Ltd | ボールグリッドアレイ型半導体装置およびその製造方法 |
JPH10107075A (ja) * | 1996-09-27 | 1998-04-24 | Nec Kyushu Ltd | 半導体装置及びその製造方法 |
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- 2000-12-21 KR KR1020000079731A patent/KR100726762B1/ko active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5334873A (en) * | 1991-05-11 | 1994-08-02 | Goldstar Electron Co., Ltd. | Semiconductor packages with centrally located electrode pads |
JPH0883878A (ja) * | 1994-09-09 | 1996-03-26 | Kawasaki Steel Corp | 半導体icチップのパッケージ及びその製造方法並びにリード・フレーム |
JPH08148603A (ja) * | 1994-11-22 | 1996-06-07 | Nec Kyushu Ltd | ボールグリッドアレイ型半導体装置およびその製造方法 |
JPH10107075A (ja) * | 1996-09-27 | 1998-04-24 | Nec Kyushu Ltd | 半導体装置及びその製造方法 |
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KR20020050556A (ko) | 2002-06-27 |
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