KR100708422B1 - 단일 식각 장치에서 하드마스크 및 금속층을 인사이츄 식각하는 방법 - Google Patents

단일 식각 장치에서 하드마스크 및 금속층을 인사이츄 식각하는 방법 Download PDF

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KR100708422B1
KR100708422B1 KR1020017009245A KR20017009245A KR100708422B1 KR 100708422 B1 KR100708422 B1 KR 100708422B1 KR 1020017009245 A KR1020017009245 A KR 1020017009245A KR 20017009245 A KR20017009245 A KR 20017009245A KR 100708422 B1 KR100708422 B1 KR 100708422B1
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South Korea
Prior art keywords
layer
etching
metal layer
hardmask material
semiconductor device
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Expired - Fee Related
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KR1020017009245A
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English (en)
Korean (ko)
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KR20010101641A (ko
Inventor
첸수잔
리주토주디콴
센더퍼안네이.
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
KR1020017009245A 1999-01-22 2000-01-21 단일 식각 장치에서 하드마스크 및 금속층을 인사이츄 식각하는 방법 Expired - Fee Related KR100708422B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/236,025 US6159863A (en) 1999-01-22 1999-01-22 Insitu hardmask and metal etch in a single etcher
US09/236,025 1999-01-22

Publications (2)

Publication Number Publication Date
KR20010101641A KR20010101641A (ko) 2001-11-14
KR100708422B1 true KR100708422B1 (ko) 2007-04-18

Family

ID=22887811

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017009245A Expired - Fee Related KR100708422B1 (ko) 1999-01-22 2000-01-21 단일 식각 장치에서 하드마스크 및 금속층을 인사이츄 식각하는 방법

Country Status (5)

Country Link
US (1) US6159863A (enExample)
EP (1) EP1166344A1 (enExample)
JP (1) JP2002535847A (enExample)
KR (1) KR100708422B1 (enExample)
WO (1) WO2000044037A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420099B1 (en) * 1999-08-02 2002-07-16 Infineon Technologies Ag Tungsten hard mask for dry etching aluminum-containing layers
US6387820B1 (en) * 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
US6656643B2 (en) 2001-02-20 2003-12-02 Chartered Semiconductor Manufacturing Ltd. Method of extreme ultraviolet mask engineering
EP1235265A1 (en) * 2001-02-23 2002-08-28 Infineon Technologies AG Method for etching a hardmask layer and a metal layer
US6582861B2 (en) 2001-03-16 2003-06-24 Applied Materials, Inc. Method of reshaping a patterned organic photoresist surface
US6573189B1 (en) 2001-11-07 2003-06-03 Taiwan Semiconductor Manufacturing Company Manufacture method of metal bottom ARC
US6861177B2 (en) * 2002-02-21 2005-03-01 Hitachi Global Storage Technologies Netherlands B.V. Method of forming a read sensor using a lift-off mask having a hardmask layer and a release layer
US6815367B2 (en) 2002-04-03 2004-11-09 Infineon Technologies Ag Elimination of resist footing on tera hardmask
DE10219122B4 (de) * 2002-04-29 2005-01-05 Infineon Technologies Ag Verfahren zur Herstellung von Hartmasken
DE10312469A1 (de) * 2003-03-20 2004-10-07 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterstruktur
US20040192059A1 (en) * 2003-03-28 2004-09-30 Mosel Vitelic, Inc. Method for etching a titanium-containing layer prior to etching an aluminum layer in a metal stack
KR100549272B1 (ko) * 2003-04-08 2006-02-03 동부아남반도체 주식회사 미세선폭을 갖는 반도체 소자의 제조 방법
KR100548515B1 (ko) * 2003-07-09 2006-02-02 매그나칩 반도체 유한회사 반도체 소자의 금속 배선의 형성 방법
US6972255B2 (en) * 2003-07-28 2005-12-06 Freescale Semiconductor, Inc. Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
US7030008B2 (en) * 2003-09-12 2006-04-18 International Business Machines Corporation Techniques for patterning features in semiconductor devices
KR20050034887A (ko) * 2003-10-10 2005-04-15 삼성전자주식회사 전원전압 동기신호 생성 장치 및 방법
US20070037100A1 (en) * 2005-08-09 2007-02-15 International Business Machines Corporation High aspect ratio mask open without hardmask
US7972957B2 (en) * 2006-02-27 2011-07-05 Taiwan Semiconductor Manufacturing Company Method of making openings in a layer of a semiconductor device
US7435681B2 (en) * 2006-05-09 2008-10-14 Macronix International Co., Ltd. Methods of etching stacks having metal layers and hard mask layers
KR100785036B1 (ko) * 2006-12-12 2007-12-11 삼성전자주식회사 전기장 쉴드를 구비한 전기장 센서의 제조방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5369053A (en) * 1989-10-24 1994-11-29 Hewlett-Packard Company Method for patterning aluminum metallizations
US5605601A (en) * 1995-09-19 1997-02-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
US5665641A (en) * 1994-10-28 1997-09-09 Advanced Micro Devices, Inc. Method to prevent formation of defects during multilayer interconnect processing
EP0837497A2 (en) * 1996-10-01 1998-04-22 Applied Materials, Inc. Method for etching transistor gates using a hardmask
US5772906A (en) * 1996-05-30 1998-06-30 Lam Research Corporation Mechanism for uniform etching by minimizing effects of etch rate loading

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5772903A (en) * 1996-09-27 1998-06-30 Hirsch; Gregory Tapered capillary optics
US6013582A (en) * 1997-12-08 2000-01-11 Applied Materials, Inc. Method for etching silicon oxynitride and inorganic antireflection coatings
US5981398A (en) * 1998-04-10 1999-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask method for forming chlorine containing plasma etched layer
US6017826A (en) * 1998-10-05 2000-01-25 Chartered Semiconductor Manufacturing, Ltd. Chlorine containing plasma etch method with enhanced sidewall passivation and attenuated microloading effect

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5369053A (en) * 1989-10-24 1994-11-29 Hewlett-Packard Company Method for patterning aluminum metallizations
US5665641A (en) * 1994-10-28 1997-09-09 Advanced Micro Devices, Inc. Method to prevent formation of defects during multilayer interconnect processing
US5605601A (en) * 1995-09-19 1997-02-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
US5772906A (en) * 1996-05-30 1998-06-30 Lam Research Corporation Mechanism for uniform etching by minimizing effects of etch rate loading
EP0837497A2 (en) * 1996-10-01 1998-04-22 Applied Materials, Inc. Method for etching transistor gates using a hardmask

Also Published As

Publication number Publication date
JP2002535847A (ja) 2002-10-22
EP1166344A1 (en) 2002-01-02
US6159863A (en) 2000-12-12
KR20010101641A (ko) 2001-11-14
WO2000044037A1 (en) 2000-07-27

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