Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
  • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
  • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

• This invention relates generally to a method of manufacturing high density, high performance semiconductor devices having a hard mask layer formed on the metal stack to prevent DUV resist footings. Even more specifically, this invention relates to a method of manufacturing high density, high performance semiconductor devices using a single etcher to etch the hardmask and metal stack.
• the increased demand for high performance semiconductor devices has required the density of metallization lines to be increased.
• One of the major demands of end users of high performance semiconductor is an increase in raw processing speed.
• the speed and functionality of the semiconductor chip have the potential to be increased significantly.
• the transistors need to be closer together to reduce the distance that electrons have to travel from one transistor to another via metal lines.
• reactance between the metal wires One reactance problem is crosstalk caused by an inductive effect between the interconnections.
• Another reactance problem is related to an RC delay that is proportional to the operating frequency of the system.
• any factor that increases or decreases any dimension can cause the performance of the semiconductor device to be less than design specification.
• the criticality of control is becoming even more critical and will become even more critical as dimensions decrease to the sub-0.25 ⁇ m region.
• a layer of a hardmask material such as Si x O y N z requires that the wafer be subjected to two separate etch processes, one to etch the hardmask material and another to etch the metal stack. Each of the separate etch processes requires a different etcher. The use of separate etchers and separate etch processes decreases throughput and adds cost to the process.
• Figures 1A-1D show a method of manufacturing a semiconductor device without using an Si x O y N 2 layer.
• Figure 1A shows a partially completed portion 100 of a semiconductor device.
• the partially completed portion 100 of the semiconductor device shows an oxide layer 102 that could be a layer of interlayer dielectric.
• a barrier layer 104 is formed on the oxide layer 102.
• the barrier layer could be a layer of Ti/TiN.
• a metallization layer 106 is formed on the barrier layer 104.
• the metallization layer 106 is formed from a conductive material such as aluminum.
• a layer 108 of an anti- reflective coating material is formed on the metallization layer 106.
• the layer 108 of anti-reflective material is formed from a material such as Ti/TiN.
• Figure IB shows the partially completed prior art semiconductor device 100 as shown in Figure 1A with a layer 110 of photoresist formed on the layer 108 of anti-reflective material.
• Figure 1C shows the partially completed prior art semiconductor device 100 as shown in Figure IB with the layer 110 of photoresist patterned and etched down to the layer 108 of anti- reflective material.
• structures known as resist footings are formed at the interface between the layer 110 of photoresist and the layer 108 of anti-reflective material. It is theorized that the formation of the resist footings 112 is caused by the nitrogen in the layer 108 of anti-reflective material reacting with the layer 110 of photoresist.
• Figure ID shows the partially completed prior art semiconductor device 100 as shown in Figure 1C after a series of etch processes to etch the layer 108, the metal layer 106, and the barrier layer 104 down to the layer 102 of oxide.
• the dimension 114 indicates the desired dimension and the dimension 116 shows the resulting dimension and indicates that the resist footing results in a relatively large reduction from the desired dimension 114.
• the criticality of the decrease in dimension can be appreciated from the fact that the designed metal line width for a typical process is approximately 0.35 ⁇ m and the spaces between the metal lines are designed to be less than 0.30 ⁇ m. Other processes have similar dimensions and future processes will have smaller dimensions.
• FIG. 3 is a flow diagram showing a prior art method of manufacturing wafers.
• the manufacturing process starts at 300.
• the manufacturing process includes a series of processes 302 that form active devices in a substrate in the wafer.
• an initial layer of interlayer dielectric is formed on the surface of the substrate and a metal layer (stack), indicated at 304, including a hardmask layer is formed on the layer of interlayer dielectric.
• a layer of photoresist is formed on the hardmask layer, patterned and developed to expose portions of the hardmask layer, indicated at 306, and the wafer is placed in a first etcher to etch the hard mask layer, indicated at 308.
• the wafer is placed in a second etcher, indicated at 310, to etch the metal layer. After the process in the second etcher is finished, it is determined at 312 if the metal layer just etched is the last metal layer. If it is not, the wafer is further processed at 314 and the next metal layer is formed at 304. This process is continued until it is determined at 312 that the metal layer just completed is the last layer. When the last layer is finished, the wafer is finished 316. The requirement to use two etchers decreases throughput and increases the cost of the process.
• a layer of hardmask material is formed on the surface of a metal layer formed on a layer of interlayer dielectric formed on a semiconductor substrate on and in which active devices have been formed.
• a layer of photoresist is formed on the surface of the layer of hardmask material, patterned and developed exposing portions of the underlying layer of hardmask material.
• the semiconductor wafer is placed in an etcher and the layer of hardmask material is etched in a first process and the metal layer is etched in a second process.
• the layer of hardmask material and the metal layer is etched using a process utilizing a combination of a fluorine and chlorine chemistry.
• the described method provides a method of manufacturing semiconductor wafers that provides a reduction of resist footings and a method that allows the etching of the hardmask material and the metal layer without changing etchers.
• Figures 1A-1D show a prior art method of manufacturing a semiconductor device that forms resist footings; wherein Figure 1A shows a partially completed portion of a semiconductor device as manufactured in the prior art;
• Figure IB shows the partially completed portion of the semiconductor device as shown in Figure 1A with a layer of photoresist formed on the surface of the semiconductor device;
• Figure 1C shows the partially completed portion of the semiconductor device as shown in Figure IB with the layer of photoresist patterned and developed showing the formation of resist footings;
• Figure ID shows the partially completed portion of the semiconductor device as shown in Figure 1C after a series of etch processes showing the non-vertical etch profiles and reduced dimensions caused by the resist footings
• Figures 2A-2D show a method of manufacturing a semiconductor device in accordance with the present invention that prevents the formation of resist footing
• Figure 2A shows a partially completed portion of a semiconductor device as manufactured in accordance with the present invention
• Figure 2B shows the partially completed portion of the semiconductor device as shown in Figure 2A with a layer of photoresist formed on the surface of the semiconductor device;
• Figure 2C shows the partially completed portion of the semiconductor device as shown in Figure 2B with the layer of photoresist patterned and developed showing that resist footings are not formed;
• Figure 2D shows the partially completed portion of the semiconductor device as shown in Figure 2C after a series of etch processes showing the vertical etch profiles provided by the present invention
• Figure 3 is a flow diagram showing a prior art method of manufacturing wafers.
• Figure 4 is a flow diagram showing a method of manufacturing wafers in accordance with the present invention.
• Figures 2A-2D show a method of manufacturing a semiconductor device in accordance with the present invention that prevents the formation of resist footing.
• Figure 2A shows a partially completed portion of a semiconductor device 200.
• the partially completed portion 200 of the semiconductor device shows an oxide layer 202 that could be a layer of interlayer dielectric.
• the oxide layer is typically formed form silicon dioxide (Si0 2 ).
• a barrier layer 204 is formed on the oxide layer 202.
• the barrier layer is formed from a material such as Ti/TiN.
• a metallization layer 206 is formed on the barrier layer 204.
• the metallization layer 206 is formed of a conductive material such as aluminum. Other materials that could form the metallization layer could be tungsten or doped polysilicon.
• a layer 208 of an anti-reflective coating material is formed on the metallization layer 206. The layer 208 of anti-reflective material is formed from a material such as Ti/TiN.
• a hardmask layer 210 is formed on the layer 208 of anti-reflective material. The hardmask layer 210 is formed from a material such as TEOS (tetra-ethyl-ortho-silicate) or treated silicon oxynitride (Si x O y N z ).
• Figure 2B shows the partially completed semiconductor device 200 as shown in Figure 2A with a layer of photoresist formed on the hardmask layer 210.
• Figure 2C shows the partially completed semiconductor device 200 as shown in Figure 2B with the layer 212 of photoresist patterned and developed down to the hardmask layer 210. As indicated at 214, there are no structures (resist footings) formed at the interface between the layer 212 of photoresist and hardmask layer 210.
• Figure 2D shows the partially completed semiconductor device 200 as shown in Figure 2C after a series of etch processes to etch the hardmask layer 210, the layer 208 of anti-reflective coating material, the metal layer 206, and the barrier layer 204 down to the layer 202 of oxide.
• etch processes are completed it is noted that the desired width of the etched portion, indicated at 216, has not been reduced.
• the hard mask layer 210 and the metal layer 206 are etched in the same etched using similar chemistry to save process steps and process time.
• the hard mask layer 210 and the metal layer 206 including the Ti/TiN layer are etched using a combination fluorine and chlorine etch chemistry.
• FIG. 4 is a flow diagram showing a method of manufacturing wafers in accordance with the present invention.
• the manufacturing process starts at 400.
• the manufacturing process includes a series of processes, indicated at 402, that form active devices in a substrate in the wafer.
• an initial layer of interlayer dielectric is formed on the surface of the substrate and a metal layer (stack), indicated at 404, including a hardmask layer is formed on the layer of interlayer dielectric.
• a layer of photoresist is formed on the hardmask layer, patterned and developed to expose portions of the hardmask layer, indicated at 406, and the wafer is placed in an etcher, indicated at 408, to etch the hardmask layer and the metal layer.
• the hardmask layer and the metal layer are etched using a combination fluorine and chlorine etch chemistry.
• the described method provides a method of manufacturing a semiconductor device that prevents the formation of deep-UV resist footings that cause an undesired reduction in critical dimensions during subsequent etch processes in prior art semiconductor devices.
• the described method provides a method of manufacturing a semiconductor device that allows a single etcher to etch the hardmask layer and the metal layer.

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• 1999
  • 1999-01-22 US US09/236,025 patent/US6159863A/en not_active Expired - Lifetime
• 2000
  • 2000-01-21 WO PCT/US2000/001503 patent/WO2000044037A1/en not_active Ceased
  • 2000-01-21 JP JP2000595374A patent/JP2002535847A/ja active Pending
  • 2000-01-21 KR KR1020017009245A patent/KR100708422B1/ko not_active Expired - Fee Related
  • 2000-01-21 EP EP00911608A patent/EP1166344A1/en not_active Withdrawn

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