KR100686823B1 - Semiconductor package - Google Patents

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KR100686823B1
KR100686823B1 KR1020010046951A KR20010046951A KR100686823B1 KR 100686823 B1 KR100686823 B1 KR 100686823B1 KR 1020010046951 A KR1020010046951 A KR 1020010046951A KR 20010046951 A KR20010046951 A KR 20010046951A KR 100686823 B1 KR100686823 B1 KR 100686823B1
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substrate
semiconductor package
semiconductor chip
hole
circuit pattern
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KR1020010046951A
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Korean (ko)
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KR20030011472A (en
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유덕수
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 반도체패키지에 관한 것으로, 수동소자로 인한 딜라미네이션, 봉지재의 크랙 및 전기적 쇼트 현상을 제거할 수 있도록, 상,하면에 다수의 회로패턴이 형성되고, 중앙에는 적어도 하나 이상의 관통공이 형성된 섭스트레이트와; 상기 섭스트레이트의 상면에 접착수단으로 접착된 적어도 하나 이상의 반도체칩과; 상기 반도체칩과 섭스트레이트의 회로패턴을 전기적으로 연결하는 다수의 도전성와이어와; 상기 섭스트레이트 상면의 반도체칩 및 도전성와이어가 외부환경으로부터 보호되도록 봉합하는 봉지재와; 상기 관통공의 내측에 위치되어, 상기 섭스트레이트의 회로패턴에 접속수단으로 연결된 수동소자와; 상기 섭스트레이트의 하면에 형성된 회로패턴에 전기적으로 연결된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. A plurality of circuit patterns are formed on upper and lower surfaces, and at least one through hole is formed in the center to remove delamination, cracks in an encapsulant, and electrical short due to passive elements. Straight; At least one semiconductor chip adhered to the upper surface of the substrate by adhesive means; A plurality of conductive wires electrically connecting the semiconductor chip and the substrate pattern of the substrate; An encapsulant for encapsulating the semiconductor chip and the conductive wire on the suprate upper surface to be protected from an external environment; A passive element positioned inside the through hole and connected to the circuit pattern of the substrate by connection means; And a plurality of conductive balls electrically connected to a circuit pattern formed on the bottom of the substrate.

Description

반도체패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

도1a는 종래의 반도체패키지를 도시한 단면도이고, 도1b는 봉지재가 제거된 종래의 반도체패키지를 도시한 사시도이다.Figure 1a is a cross-sectional view showing a conventional semiconductor package, Figure 1b is a perspective view showing a conventional semiconductor package with the sealing material removed.

도2a는 본 발명에 의한 반도체패키지를 도시한 단면도이고, 도2b는 도2a의 저면도이다.Figure 2a is a cross-sectional view showing a semiconductor package according to the present invention, Figure 2b is a bottom view of Figure 2a.

도3은 본 발명에 의한 다른 반도체패키지를 도시한 단면도이다.3 is a cross-sectional view showing another semiconductor package according to the present invention.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

100; 본 발명에 의한 반도체패키지100; Semiconductor package according to the present invention

10; 섭스트레이트 11; 수지층10; Suprate 11; Resin layer

12; 회로패턴 12a; 본드핑거12; Circuit pattern 12a; Bondfinger

12b; 볼랜드 13; 도전성비아12b; Borland 13; Conductive Via

14; 커버코트 15; 관통공14; Covercoat 15; Through hole

20; 접착수단 30; 반도체칩20; Bonding means 30; Semiconductor chip

31; 입출력패드 40; 도전성와이어31; Input / output pad 40; Conductive Wire

50; 봉지재 60; 도전성볼50; Encapsulant 60; Conductive ball

70; 수동소자 71; 전극70; Passive element 71; electrode

80; 접속수단80; Connection

본 발명은 반도체패키지에 관한 것으로, 더욱 상세하게 설명하면 다수의 수동소자를 갖는 SIP(System In Package)형 반도체패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a SIP (System In Package) type semiconductor package having a plurality of passive elements.

통상 전자 부품은 능동소자와 수동소자로 나누어 볼 수 있는데, 상기 능동소자는 비선형 부분을 적극적으로 이용한 소자이고, 수동소자는 선형이거나, 비선형 부분이 있어도 그 비선형 특성을 이용하지 않는 것을 수동소자라 한다.Generally, electronic components can be divided into active elements and passive elements. The active elements are elements that actively use nonlinear portions, and passive elements are linear elements that do not use their nonlinear characteristics even if they are linear or nonlinear portions. .

상기 능동소자의 대표적인 것은 트랜지스터, IC 반도체칩 등이며, 상기 수동소자의 대표적인 것은 콘덴서, 저항, 인덕터 등이다. 이러한 수동소자는 능동소자인 반도체칩의 신호 처리 속도를 높이거나, 필터링 기능 등을 수행하며, 통상 반도체패키지가 실장된 마더보드의 임의 위치에 다수가 실장된다. 그러나, 상기와 같이 반도체패키지의 주변에 실장되는 수동소자는 마더보드의 면적을 증가시키고, 반도체패키지의 실장 밀도를 크게 저하시키는 단점이 있다.Typical examples of the active elements are transistors, IC semiconductor chips, and the like, and typical examples of the passive elements are capacitors, resistors, inductors, and the like. Such passive devices speed up the signal processing of the semiconductor chip, which is an active device, perform a filtering function, and the like, and a plurality of passive devices are usually mounted at arbitrary positions on the motherboard on which the semiconductor package is mounted. However, the passive element mounted around the semiconductor package as described above has the disadvantage of increasing the area of the motherboard and greatly lowering the mounting density of the semiconductor package.

이러한 단점을 해결하기 위해, 최근에는 상기 수동소자를 반도체패키지의 한 구성 요소인 섭스트레이트에 직접 실장한 구조(이를, System In Package라고 함) 및 방법이 제안되고 있으며, 이러한 상태가 도1a 및 도1b에 도시되어 있다.In order to solve this drawback, recently, a structure (method called System In Package) and a method in which the passive element is directly mounted on a substrate, which is a component of a semiconductor package, have been proposed. It is shown in 1b.

여기서, 도1a는 종래 수동소자를 갖는 반도체패키지(100')의 단면도이고, 도1b는 봉지재(60')가 제거된 상태의 반도체패키지를 도시한 사시도이다.1A is a cross-sectional view of a semiconductor package 100 'having a conventional passive element, and FIG. 1B is a perspective view showing a semiconductor package in a state in which an encapsulant 60' is removed.

도시된 바와 같이 종래에는 상,하면에 다수의 회로패턴(12')이 형성된 섭스 트레이트(10')가 구비되어 있고, 상기 섭스트레이트(10') 상면 중앙에는 반도체칩(41')이 접착되어 있으며, 그 외측의 회로패턴(12')에는 다수의 수동소자(20')가 실장되어 있다. 상기 반도체칩(41')의 입출력패드(43')는 도전성와이어(50')에 의해 상기 섭스트레이트(10') 상면의 회로패턴(12')에 접속되어 있고, 상기 섭스트레이트(10') 하면의 회로패턴(12')에는 다수의 도전성볼(71')이 융착되어 있다. 또한, 상기 섭스트레이트(10')의 상면 전체에는 봉지재(60')가 봉지되어 있음으로써, 상기 반도체칩(41'), 도전성와이어(50') 및 수동소자(20')가 외부 환경으로부터 보호되도록 되어 있다.As shown in the related art, a substrate 10 'having a plurality of circuit patterns 12' is formed on upper and lower surfaces, and a semiconductor chip 41 'is adhered to the center of the upper surface of the substrate 10'. A plurality of passive elements 20 'are mounted on the outer circuit pattern 12'. The input / output pad 43 'of the semiconductor chip 41' is connected to the circuit pattern 12 'on the upper surface of the substrate 10' by the conductive wire 50 ', and the substrate 10'. A plurality of conductive balls 71 'are fused to the circuit pattern 12' on the lower surface. In addition, the encapsulant 60 'is encapsulated in the entire upper surface of the substrate 10' so that the semiconductor chip 41 ', the conductive wire 50', and the passive element 20 'are removed from the external environment. It is supposed to be protected.

상기 섭스트레이트(10')는 통상 인쇄회로기판(Printed Circuit Board), 써킷필름(Circuit Film), 써킷테이프(Circuit Tape) 등 다양한 것이 존재하지만 여기서는 인쇄회로기판을 예로 설명한다.The substrate 10 ′ generally includes a printed circuit board, a circuit film, a circuit tape, and the like, but the printed circuit board will be described as an example.

즉, 상기 섭스트레이트(10')는 열경화성 수지층(11')을 중심으로 그 상,하면에 다수의 도전성 회로패턴(12')이 형성되어 있고, 상기 상,하면의 회로패턴(12')은 도전성 비아(13')에 의해 상호 전기적으로 연결된 구조를 한다. 또한, 상기 수지층(11') 상면의 회로패턴(12')은 도전성와이어(50')가 접속되는 본드핑거(12a')를 포함하고, 상기 수지층(11') 하면의 회로패턴(12')은 도전성볼(71')이 융착되는 랜드(12b')를 포함한다. 또한, 상기 본드핑거(12a') 및 랜드(12b')를 제외한 표면은 비전도성 커버코트(14')가 코팅되어 외부 환경으로부터 보호되도록 되어 있다. 물론, 상기 수동소자(20')가 실장되는 영역은 커버코트(14')가 코팅되어 있지 않다. That is, the conductive substrate 10 'has a plurality of conductive circuit patterns 12' formed on and under the thermosetting resin layer 11 ', and the circuit patterns 12' on the upper and lower surfaces. Silver has a structure electrically connected to each other by a conductive via (13 '). In addition, the circuit pattern 12 'on the upper surface of the resin layer 11' includes a bond finger 12a 'to which conductive wires 50' are connected, and the circuit pattern 12 on the lower surface of the resin layer 11 '. ') Includes a land 12b' to which the conductive ball 71 'is fused. In addition, the surfaces excluding the bond fingers 12a 'and the lands 12b' are coated with a non-conductive cover coat 14 'to be protected from the external environment. Of course, the cover coat 14 'is not coated in the area in which the passive element 20' is mounted.                         

여기서, 상기 수동소자(20')는 상기 섭스트레이트(10') 상면의 회로패턴(12')에 솔더(21')를 이용한 SMT(Surface Mount Technology) 방식으로 실장되어 있으나, THT(Through Hole Technology) 방식으로 실장될 수도 있다.Here, the passive element 20 'is mounted on the circuit pattern 12' on the upper surface 10 'by SMT (Surface Mount Technology) method using solder 21', but through hole technology May be implemented in a

그러나 이러한 종래의 반도체패키지도 다음과 같은 문제가 있다.However, such a conventional semiconductor package also has the following problems.

즉, 상기 수동소자를 섭스트레이트에 실장시키는 솔더로 인하여 딜라미네이션(Delamination) 발생 확률이 매우 높아지는 문제가 있다. 즉, 상기 솔더의 고유특성 그리고 상기 솔더의 표면에 남아 있는 플럭스 레진(Flux Resin)으로 인하여 그 솔더와 상기 봉지재와의 접착력이 매우 불량하고, 따라서 상기 솔더와 봉지재 사이에 딜라미네이션이 쉽게 발생하는 문제가 있다.That is, due to the solder that mounts the passive element on the substrate, there is a problem in that the probability of occurrence of delamination is very high. That is, due to the inherent properties of the solder and the flux resin remaining on the surface of the solder, the adhesion between the solder and the encapsulant is very poor, and thus a delamination easily occurs between the solder and the encapsulant. There is a problem.

더불어, 상기 수동소자를 섭스트레이트에 실장시키는 솔더는 상기 반도체패키지가 고온의 환경에 놓여졌을 때 재용융되고, 이에 따라 기포, 가스 등이 발생됨으로써, 봉지재의 크랙 및 섭스트레이트에 형성된 회로패턴의 전기적 쇼트 등을 유발하는 문제가 있다.In addition, the solder for mounting the passive element on the substrate is remelted when the semiconductor package is placed in a high temperature environment, thereby generating bubbles, gas, etc., thereby causing the electrical cracking of the circuit pattern formed on the crack and the substrate of the encapsulant. There is a problem that causes a short.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 수동소자로 인한 딜라미네이션, 봉지재의 크랙 및 전기적 쇼트 현상을 최소화할 수 있는 반도체패키지를 제공하는데 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, to provide a semiconductor package that can minimize the delamination due to the passive element, the crack of the encapsulant and the electrical short phenomenon.

상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상,하면에 다수의 회로패턴이 형성되고, 중앙에는 적어도 하나 이상의 관통공이 형성된 섭스트 레이트와; 상기 섭스트레이트의 상면에 접착수단으로 접착된 적어도 하나 이상의 반도체칩과; 상기 반도체칩과 섭스트레이트의 회로패턴을 전기적으로 연결하는 다수의 도전성와이어와; 상기 섭스트레이트 상면의 반도체칩 및 도전성와이어가 외부환경으로부터 보호되도록 봉합하는 봉지재와; 상기 관통공의 내측에 위치되어, 상기 섭스트레이트의 회로패턴에 접속수단으로 연결된 수동소자와; 상기 섭스트레이트의 하면에 형성된 회로패턴에 전기적으로 연결된 다수의 도전성볼을 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention includes a plurality of circuit patterns formed on upper and lower surfaces, and a center rate having at least one through hole formed in the center thereof; At least one semiconductor chip adhered to the upper surface of the substrate by adhesive means; A plurality of conductive wires electrically connecting the semiconductor chip and the substrate pattern of the substrate; An encapsulant for encapsulating the semiconductor chip and the conductive wire on the suprate upper surface to be protected from an external environment; A passive element positioned inside the through hole and connected to the circuit pattern of the substrate by connection means; It characterized in that it comprises a plurality of conductive balls electrically connected to the circuit pattern formed on the bottom of the substrate.

여기서, 상기 수동소자와 상기 섭스트레이트의 회로패턴을 연결하는 접속수단은 솔더페이스트 또는 실버페이스트중 어느 하나가 융용되어 형성될 수 있다.Here, the connection means for connecting the passive element and the substrate circuit pattern may be formed by melting any one of solder paste or silver paste.

또한, 상기 관통공 내측의 수동소자는 하면이 봉지재로 봉합될 수도 있다.In addition, the lower surface of the passive element inside the through hole may be sealed with an encapsulant.

상기와 같이 하여 본 발명에 의한 반도체패키지에 의하면, 수동소자가 섭스트레이트 상면의 봉지재 내측에 위치되지 않고, 섭스트레이트의 관통공에 위치됨으로써, 종래와 같은 봉지재와 수동소자 사이의 딜라미네이션 문제 및 봉지재의 크랙 문제를 원천적으로 해결할 수 있게 된다.As described above, according to the semiconductor package according to the present invention, the passive element is not located inside the encapsulant on the upper substrate, but is located in the through hole of the substrate. And it is possible to fundamentally solve the crack problem of the encapsulant.

또한, 상기 접속수단은 외부로 노출되어 있음으로써, 반도체패키지가 고온의 환경에 노출된다 해도, 표면장력에 의해 소정 영역에만 위치되고, 따라서 상기 솔더에 의해 다른 회로패턴을 전기적으로 쇼트시키는 현상도 제거된다.In addition, since the connection means is exposed to the outside, even if the semiconductor package is exposed to a high temperature environment, it is located only in a predetermined region due to surface tension, thereby eliminating the phenomenon of electrically shorting another circuit pattern by the solder. do.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.                     

도2a는 본 발명에 의한 반도체패키지(100)를 도시한 단면도이고, 도2b는 도2a의 저면도이다.Figure 2a is a cross-sectional view showing a semiconductor package 100 according to the present invention, Figure 2b is a bottom view of Figure 2a.

도시된 바와 같이 열경화성 수지층(11)을 중심으로 그 상,하면에는 다수의 도전성 회로패턴(12)이 형성된 섭스트레이트(10)가 구비되어 있다.As illustrated, the substrate 10 having a plurality of conductive circuit patterns 12 formed on and under the thermosetting resin layer 11 is provided.

상기 수지층(11) 상,하면의 회로패턴(12)은 도전성 비아(13)에 의해 상호 전기적으로 연결되어 있다. 또한 상기 수지층(11) 상면의 회로패턴(12)은 하기할 도전성와이어(40)와 연결되는 본드핑거(12a)를 포함한다. 또한, 상기 수지층(11) 하면의 회로패턴(12)은 하기할 도전성볼(60)과 연결되는 볼랜드(12b)를 포함한다. 또한, 상기 본드핑거(12a) 및 볼랜드(12b)를 제외한 회로패턴(12)은 절연성의 커버코트(14)로 코팅되어 있다.Circuit patterns 12 on the lower and upper surfaces of the resin layer 11 are electrically connected to each other by conductive vias 13. In addition, the circuit pattern 12 on the upper surface of the resin layer 11 includes a bond finger 12a connected to the conductive wire 40 to be described below. In addition, the circuit pattern 12 on the bottom surface of the resin layer 11 includes a ball land 12b connected to the conductive ball 60 to be described below. In addition, the circuit pattern 12 except for the bond finger 12a and the borland 12b is coated with an insulating cover coat 14.

이러한 섭스트레이트(10)는 통상의 인쇄회로기판, 써킷테이프, 써킷필름 등이 이용될 수 있으며, 본 발명에서 특정한 섭스트레이트를 한정하는 것은 아니다.The substrate 10 may be a conventional printed circuit board, a circuit tape, a circuit film, and the like, and the present invention is not limited to a specific substrate.

더불어, 상기 섭스트레이트(10)의 중앙부에는 적어도 하나 이상의 관통공(15)이 형성되어 있다. 상기 관통공(15)은 바람직하기로 하기할 반도체칩(30)의 하면과 대응되는 영역에 다수개가 형성됨이 바람직하다.In addition, at least one through hole 15 is formed at the central portion of the substrate 10. Preferably, the plurality of through holes 15 are formed in a region corresponding to the bottom surface of the semiconductor chip 30 to be described later.

상기 섭스트레이트(10)의 상면에는 접착수단(20)에 의해 적어도 하나 이상의 반도체칩(30)이 접착되어 있다. 즉, 상기 관통공(15)의 상면의 상면에는 접착수단(20) 및 반도체칩(30)이 위치되어 있다. 상기 접착수단(20)은 통상적인 액상의 에폭시 접착제, 접착필름 또는 이들의 등가물을 이용할 수 있다. 또한, 상기 반도체칩(30)은 상면에 다수의 입출력패드(31)가 형성되어 있다. At least one semiconductor chip 30 is bonded to the upper surface of the substrate 10 by the bonding means 20. That is, the adhesive means 20 and the semiconductor chip 30 are located on the upper surface of the through hole 15. The adhesive means 20 may use a conventional liquid epoxy adhesive, an adhesive film or an equivalent thereof. In addition, the semiconductor chip 30 has a plurality of input / output pads 31 formed on an upper surface thereof.                     

상기 반도체칩(30)의 입출력패드(31)와 상기 섭스트레이트(10)의 회로패턴(12)은 골드와이어(40), 알루미늄와이어(40) 또는 이들의 등가물에 의해 상호 연결되어 있다.The input / output pad 31 of the semiconductor chip 30 and the circuit pattern 12 of the substrate 10 are connected to each other by a gold wire 40, an aluminum wire 40, or an equivalent thereof.

계속해서, 상기 섭스트레이트(10) 상면의 반도체칩(30) 및 도전성와이어(40)는 외부환경으로부터 보호되도록 에폭시몰딩컴파운드(Epoxy Molding Compound), 인캡(??메)(액상으로서 공기중에 노출되면 딱딱하게 경화됨) 또는 이들의 등가물과 같은 봉지재(50)로 봉지되어 있다.Subsequently, when the semiconductor chip 30 and the conductive wire 40 on the upper substrate 10 are exposed to the air as an epoxy molding compound or an encap (liquid) so as to be protected from an external environment. Hardened) or an equivalent thereof, and is encapsulated with an encapsulant 50.

이어서, 상기 섭스트레이트(10)의 관통공(15) 내측에는 콘덴서, 저항, 인덕터 등과 같은 수동소자(70)가 위치되어 있으며, 이 수동소자(70)의 전극(71)은 상기 섭스트레이트(10)의 회로패턴(12)과 전기적 접속수단(80)에 의해 상호 연결되어 있다.Subsequently, a passive element 70 such as a condenser, a resistor, an inductor, etc. is positioned inside the through hole 15 of the substratum 10, and the electrode 71 of the passive element 70 is provided with the substrate 10. Are interconnected by a circuit pattern 12 and electrical connection means 80.

즉, 상기 수동소자(70)는 상기 섭스트레이트(10)의 하면에 형성된 소정의 회로패턴(12)과 전기적 접속수단(80)에 의해 연결되어 있다. 물론, 상기 회로패턴(12)은 소정의 볼랜드(12b)와 연결되어 있으며, 이는 반도체칩(30) 및 마더보드에 전기적으로 연결된다.That is, the passive element 70 is connected to the predetermined circuit pattern 12 formed on the lower surface of the substrate 10 by the electrical connection means 80. Of course, the circuit pattern 12 is connected to a predetermined borland 12b, which is electrically connected to the semiconductor chip 30 and the motherboard.

여기서, 상기 접속수단(80)은 솔더페이스트(Solder Paste), 실버페이스트(Silver Paste) 또는 이들의 등가물중 어느 하나가 융용되어 형성될 수 있다. 또한, 상기 수동소자(70)의 전극(71)과 회로패턴(12) 사이의 접속수단(80)은 융용되었을때 표면장력에 의해 상기 전극(71)과 회로패턴(12) 사이에만 형성됨으로써, 그 접속작업이 용이하게 이루어지는 장점이 있다. Here, the connection means 80 may be formed by melting any one of a solder paste, a silver paste, or an equivalent thereof. In addition, the connecting means 80 between the electrode 71 and the circuit pattern 12 of the passive element 70 is formed only between the electrode 71 and the circuit pattern 12 by surface tension when molten, There is an advantage that the connection work is made easily.                     

또한, 상기 관통공(15) 내측의 수동소자(70)는 하면이 봉지재(50)로 봉합될 수도 있으나, 이것으로 본 발명을 한정하는 것은 아니다.In addition, the lower surface of the passive element 70 inside the through hole 15 may be sealed with an encapsulant 50, but this is not a limitation of the present invention.

계속해서, 상기 섭스트레이트(10) 하면에 형성된 회로패턴(12)에는 솔더볼 또는 이것의 등가물과 같은 도전성볼(60)이 융착되어 있으며, 상기 도전성볼(60)은 차후 마더보드에 실장되는 영역이 된다.Subsequently, a conductive ball 60, such as a solder ball or an equivalent thereof, is fused to the circuit pattern 12 formed on the lower surface of the substrate 10, and the conductive ball 60 has a region to be mounted on the motherboard later. do.

도3은 본 발명에 의한 다른 반도체패키지(101)를 도시한 단면도이다. 여기서, 상기 반도체패키지(101)는 도2a의 반도체패키지(100)와 유사하므로 그 차이점을 중심으로 설명하기로 한다.3 is a cross-sectional view showing another semiconductor package 101 according to the present invention. Here, since the semiconductor package 101 is similar to the semiconductor package 100 of FIG. 2A, the difference will be described.

도시된 바와 같이, 일정크기의 관통공(15)이 섭스트레이트(10)중 반도체칩(30)이 접착된 영역의 외주연에 다수개가 형성되어 있다. 보다 구체적으로, 상기 관통공(15)은 반도체칩(30)의 입출력패드(31)에 도전성와이어(40)로 연결된 회로패턴(12)중 본드핑거(12a) 외주연에 형성되어 있다.As shown, a plurality of through holes 15 having a predetermined size are formed on the outer periphery of the region to which the semiconductor chip 30 is bonded in the substrate 10. More specifically, the through hole 15 is formed on the outer periphery of the bond finger 12a of the circuit pattern 12 connected to the input / output pad 31 of the semiconductor chip 30 by the conductive wire 40.

물론, 상기 관통공(15) 내측에는 수동소자(70)가 위치되어 있으며, 이는 섭스트레이트(10) 하면에 형성된 회로패턴(12)과 솔더와 같은 접속수단(80)에 의해 전기적으로 연결되어 있다. 여기서, 상기 접속수단(80)은 상기 관통공(15)의 내벽과 수동소자(70) 사이에 형성됨으로써, 상기 접속수단(80)과 봉지재(50)와의 직접적인 접촉면적은 상당히 줄어들게 된다. 따라서, 상기 반도체패키지(101)가 고온의 환경에 노출된다 해도, 상기 접속수단(80)과 봉지재(50)와의 접촉 영역이 작기 때문에, 종래와 같은 딜라미네이션 문제 및 봉지재의 크랙 현상을 억제할 수 있게 된다. Of course, the passive element 70 is located inside the through hole 15, which is electrically connected to the circuit pattern 12 formed on the lower surface of the substrate 10 by a connection means 80 such as solder. . Here, the connecting means 80 is formed between the inner wall of the through hole 15 and the passive element 70, so that the direct contact area between the connecting means 80 and the encapsulant 50 is significantly reduced. Therefore, even when the semiconductor package 101 is exposed to a high temperature environment, since the contact area between the connecting means 80 and the encapsulant 50 is small, it is possible to suppress the conventional delamination problem and crack phenomenon of the encapsulant. It becomes possible.                     

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서 본 발명에 의한 반도체패키지에 의하면, 수동소자가 섭스트레이트 상면의 봉지재 내측에 위치되지 않고, 섭스트레이트의 관통공에 위치됨으로써, 종래와 같은 봉지재와 수동소자 사이의 딜라미네이션 문제 및 봉지재의 크랙 문제를 원천적으로 해결할 수 있는 효과가 있다.Therefore, according to the semiconductor package according to the present invention, the passive element is not located inside the encapsulant on the upper surface of the substrate, but is located in the through hole of the substrate. It is effective to solve the crack problem at the source.

또한, 수동소자와 섭스트레이트의 회로패턴을 연결하는 접속수단은 반도체패키지의 외부로 노출되어 있음으로써, 반도체패키지가 고온의 환경에 노출된다 해도, 표면장력에 의해 소정 영역에만 위치되고, 따라서 상기 접속수단에 의해 다른 회로패턴을 전기적으로 쇼트시키는 현상도 제거할 수 있는 효과가 있다.In addition, the connecting means for connecting the passive element and the circuit pattern of the substrate is exposed to the outside of the semiconductor package, so that even if the semiconductor package is exposed to a high temperature environment, it is located only in a predetermined region by surface tension, and thus the connection The effect of electrically shorting other circuit patterns by means can also be eliminated.

Claims (5)

상,하면에 다수의 회로패턴이 형성되고, 적어도 하나 이상의 관통공이 형성된 섭스트레이트와;A plurality of circuit patterns formed on upper and lower surfaces and at least one through hole formed therein; 상기 섭스트레이트의 상면에 접착수단으로 접착된 적어도 하나 이상의 반도체칩과;At least one semiconductor chip adhered to the upper surface of the substrate by adhesive means; 상기 반도체칩과 섭스트레이트의 회로패턴을 전기적으로 연결하는 다수의 도전성와이어와;A plurality of conductive wires electrically connecting the semiconductor chip and the substrate pattern of the substrate; 상기 섭스트레이트 상면의 반도체칩 및 도전성와이어가 외부환경으로부터 보호되도록 봉합하는 봉지재와;An encapsulant for encapsulating the semiconductor chip and the conductive wire on the suprate upper surface to be protected from an external environment; 상기 관통공의 내측에 위치되어, 상기 섭스트레이트의 회로패턴에 접속수단으로 연결된 수동소자와;A passive element positioned inside the through hole and connected to the circuit pattern of the substrate by connection means; 상기 섭스트레이트의 하면에 형성된 회로패턴에 전기적으로 연결된 다수의 도전성볼을 포함하여 이루어진 반도체패키지.A semiconductor package comprising a plurality of conductive balls electrically connected to a circuit pattern formed on the bottom of the substrate. 제1항에 있어서, 상기 수동소자와 상기 섭스트레이트의 회로패턴을 연결하는 접속수단은 솔더페이스트 또는 실버페이스트중 어느 하나가 융용되어 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 1, wherein the connection means for connecting the passive element and the circuit pattern of the substrate is formed by melting one of solder paste and silver paste. 제1항 또는 제2항중 어느 한 항에 있어서, 상기 관통공 내측의 수동소자는 하면이 봉지재로 봉합된 것을 특징으로 하는 반도체패키지.The semiconductor package according to any one of claims 1 to 3, wherein the passive element inside the through hole has a bottom surface sealed with an encapsulant. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 관통공은 반도체칩이 접착되는 섭스트레이트에 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package according to any one of claims 1 to 3, wherein the through hole is formed in a substrate to which the semiconductor chip is bonded. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 관통공은 반도체칩이 접착되는 영역의 외주연인 섭스트레이트에 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package according to any one of claims 1 to 3, wherein the through hole is formed in a substrate having an outer circumference of a region to which the semiconductor chip is bonded.
KR1020010046951A 2001-08-03 2001-08-03 Semiconductor package KR100686823B1 (en)

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KR20000066197A (en) * 1999-04-14 2000-11-15 마이클 디. 오브라이언 semi-conduSSor package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000066197A (en) * 1999-04-14 2000-11-15 마이클 디. 오브라이언 semi-conduSSor package

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