KR100680939B1 - Manufacturing method for metal line in semiconductor device - Google Patents

Manufacturing method for metal line in semiconductor device Download PDF

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KR100680939B1
KR100680939B1 KR1020000059484A KR20000059484A KR100680939B1 KR 100680939 B1 KR100680939 B1 KR 100680939B1 KR 1020000059484 A KR1020000059484 A KR 1020000059484A KR 20000059484 A KR20000059484 A KR 20000059484A KR 100680939 B1 KR100680939 B1 KR 100680939B1
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South Korea
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wiring
substrate
insulating film
trench
forming
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KR1020000059484A
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Korean (ko)
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KR20020028461A (en
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임행삼
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 배선 형성방법에 관한 것으로, 종래 반도체 소자의 배선 형성방법은 메모리셀 등의 주변부와의 단차가 큰 영역에는 콘택홀의 형성이 용이하지 않고, 단차가 있는 영역간의 배선 형성시 단선될 우려가 있어 배선의 신뢰성이 저하되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 기판에 트랜치를 형성하고, 그 트랜치가 형성된 기판의 전면에 절연막을 증착한 후, 도전막을 상기 트랜치가 모두 채워지도록 증착하는 단계와; 상기 도전막의 상부일부를 식각하여 상기 트랜치 내에서 기판의 표면보다 낮은 위치에 도전막을 잔존시키는 단계와; 상기 구조의 상부전면에 절연막을 증착하는 단계와; 상기 증착한 절연막을 평탄화하여 그 절연막의 상부면이 기판의 상부면과 동일 평면상에 있도록 하는 단계로 구성되어 반도체 소자의 배선을 기판에 매립형으로 형성함으로써, 반도체 소자의 단차에 의한 배선의 단선을 방지하고, 깊은 콘택홀의 형성없이 배선을 형성하여 그 배선 형성의 신뢰성을 향상시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device. In the conventional method for forming a wiring of a semiconductor device, contact holes are not easily formed in a region having a large step difference with a peripheral portion of a memory cell, and the like. There is a fear that the reliability of the wiring is lowered. In view of the above problems, the present invention includes forming a trench in a substrate, depositing an insulating film on the entire surface of the substrate on which the trench is formed, and then depositing a conductive film so that the trench is completely filled; Etching a portion of the upper portion of the conductive layer so that the conductive layer remains at a position lower than the surface of the substrate in the trench; Depositing an insulating film on the upper surface of the structure; And planarizing the deposited insulating film so that the upper surface of the insulating film is flush with the upper surface of the substrate. The wiring of the semiconductor element is formed in the substrate in a buried type, thereby disconnecting the wiring by the step of the semiconductor element. There is an effect of preventing and forming a wiring without forming a deep contact hole, thereby improving the reliability of the wiring formation.

Description

반도체 소자의 배선 형성방법{MANUFACTURING METHOD FOR METAL LINE IN SEMICONDUCTOR DEVICE}WIRING METHOD OF SEMICONDUCTOR DEVICE {MANUFACTURING METHOD FOR METAL LINE IN SEMICONDUCTOR DEVICE}

도1a 내지 도1c는 종래 반도체 소자의 배선 제조공정 수순단면도.1A to 1C are cross-sectional views of a wiring manufacturing process of a conventional semiconductor device.

도2a 내지 도2d는 본 발명 반도체 소자의 배선 제조공정 수순단면도.Figures 2a to 2d is a cross-sectional view of the wiring manufacturing process step of the semiconductor device of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1:기판 2,4:절연막1: substrate 2, 4: insulation film

3:도전막3: conductive film

본 발명은 반도체 소자의 배선 형성방법에 관한 것으로, 특히 배선을 기판의 하부에 형성하여, 반도체 소자의 단차를 낮추고 배선형성시 콘택홀 등의 오형성으로 인한 문제점을 해결하는데 적당하도록 한 반도체 소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device, and more particularly, to form a wiring under a substrate to reduce the step height of the semiconductor device and to solve a problem caused by a misalignment such as a contact hole when forming the wiring. It relates to a wiring forming method.

도1a 내지 도1c는 종래 반도체 소자의 배선 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부전면에 절연막(2)을 증착하고, 그 절연막(2)에 콘택홀을 형성하여 상기 반도체 소자의 특정영역을 노출시키는 단계(도1a)와; 상기 구조의 상부전면에 도전성박막을 증착하고 평탄화하여 상기 콘택홀 내에서 상기 노출된 반도체 소자의 특정영역에 접하는 플러그(3)를 형성하는 단계(도1b)와; 상기 구조의 상부전면에 금속을 증착하고, 사진식각공정을 통해 플러그(3)에 접하며 소정의 패턴을 갖는 배선(4)을 형성하는 단계(도1c)로 구성된다.1A to 1C are schematic cross-sectional views of a wire fabrication process of a conventional semiconductor device. As shown therein, an insulating film 2 is deposited on an upper surface of a substrate 1 on which a semiconductor device is formed, and contact holes are formed on the insulating film 2. Forming a portion to expose a specific region of the semiconductor device (FIG. 1A); Depositing and planarizing a conductive thin film on the upper surface of the structure to form a plug (3) contacting a specific region of the exposed semiconductor device in the contact hole (FIG. 1B); And depositing a metal on the upper surface of the structure and forming a wiring 4 in contact with the plug 3 through a photolithography process and having a predetermined pattern (FIG. 1C).

이하, 상기와 같이 구성된 종래 반도체 소자의 배선 형성방법을 좀 더 상세히 설명한다.Hereinafter, a wiring forming method of a conventional semiconductor device configured as described above will be described in more detail.

먼저, 도1a에 도시한 바와 같이 기판(1)의 상부에 반도체 소자를 제조한 후, 그 상부전면에 상부면이 평탄한 절연막(2)을 증착한다.First, as shown in FIG. 1A, a semiconductor device is manufactured on the substrate 1, and then an insulating film 2 having a flat upper surface is deposited on the upper surface thereof.

그 다음, 상기 구조의 상부전면에 포토레지스트(도면 미도시)를 도포하고 노광 및 현상하여 상기 절연막(2)의 일부를 노출시키는 패턴을 형성한다. Then, a photoresist (not shown) is applied to the upper surface of the structure, and the pattern is exposed to light and developed to expose a portion of the insulating film 2.                         

그 다음, 상기 노출된 절연막(2)을 식각하여 상기 기판(1)에 형성한 반도체 소자의 특정영역을 노출시키는 콘택홀을 형성하고, 상기 포토레지스트 패턴을 제거한다.Next, the exposed insulating layer 2 is etched to form a contact hole for exposing a specific region of the semiconductor device formed on the substrate 1, and the photoresist pattern is removed.

그 다음, 도1b에 도시한 바와같이 상기 구조의 상부전면에 금속 등의 도전성물질을 증착하여, 상기 콘택홀이 모두 채워질수 있도록 한다.Next, as shown in FIG. 1B, a conductive material such as a metal is deposited on the upper surface of the structure so that the contact holes can be filled.

그 다음, 상기 증착된 도전성 물질을 평탄화하여 상기 콘택홀 내에서 노출된 반도체 소자의 특정영역에 접속되는 플러그(3)를 형성한다.Next, the deposited conductive material is planarized to form a plug 3 connected to a specific region of the semiconductor device exposed in the contact hole.

그 다음, 도1c에 도시한 바와 같이 상기 구조의 상부전면에 금속을 증착하고, 사진식각공정을 통해 패터닝함으로써, 상기 플러그(3)에 접속되는 배선(4)을 형성한다.Then, as shown in FIG. 1C, a metal is deposited on the upper front surface of the structure and patterned through a photolithography process to form a wiring 4 connected to the plug 3.

그러나, 상기와 같은 종래 반도체 소자의 배선 형성방법은 메모리셀 등의 주변부와의 단차가 큰 영역에는 콘택홀의 형성이 용이하지 않고, 단차가 있는 영역간의 배선 형성시 단선될 우려가 있어 배선의 신뢰성이 저하되는 문제점이 있었다.However, in the conventional method of forming a wiring of a semiconductor device as described above, contact holes are not easily formed in areas having large steps with peripheral parts such as memory cells. There was a problem of deterioration.

이와 같은 문제점을 감안한 본 발명은 반도체 소자의 단차에 관계없이 신뢰성있는 배선을 형성할 수 있는 반도체 소자의 배선 형성방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a method for forming a wiring of a semiconductor device capable of forming a reliable wiring regardless of the step of the semiconductor device.

상기와 같은 목적은 기판에 트랜치를 형성하고, 그 트랜치가 형성된 기판의 전면에 절연막을 증착한 후, 도전막을 상기 트랜치가 모두 채워지도록 증착하는 단 계와; 상기 도전막의 상부일부를 식각하여 상기 트랜치 내에서 기판의 표면보다 낮은 위치에 도전막을 잔존시키는 단계와; 상기 구조의 상부전면에 절연막을 증착하는 단계와; 상기 증착한 절연막을 평탄화하여 그 절연막의 상부면이 기판의 상부면과 동일 평면상에 있도록 하는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object includes forming a trench in a substrate, depositing an insulating film on the entire surface of the substrate on which the trench is formed, and then depositing a conductive film so that the trenches are completely filled; Etching a portion of the upper portion of the conductive layer so that the conductive layer remains at a position lower than the surface of the substrate in the trench; Depositing an insulating film on the upper surface of the structure; This is achieved by planarizing the deposited insulating film so that the upper surface of the insulating film is coplanar with the upper surface of the substrate, which will be described in detail with reference to the accompanying drawings.

도2a 내지 도2d는 본 발명 반도체 소자의 배선 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)에 트랜치를 형성하고, 그 트랜치가 형성된 기판(1)의 전면에 절연막(2)을 증착한 후, 도전막(3)을 상기 트랜치가 모두 채워지도록 증착하는 단계(도2a)와; 상기 도전막(3)의 상부일부를 식각하여 상기 트랜치 내에서 기판(1)의 표면보다 낮은 위치에 도전막(3)을 잔존시키는 단계(도2b)와; 상기 구조의 상부전면에 절연막(4)을 증착하는 단계(도2c)와; 상기 증착한 절연막(4)을 평탄화하여 그 절연막(4)의 상부면이 기판(1)의 상부면과 동일 평면상에 있도록 하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a wire fabrication process of the semiconductor device according to the present invention, in which a trench is formed in the substrate 1 and the insulating film 2 is deposited on the entire surface of the substrate 1 on which the trench is formed. Thereafter, depositing a conductive film (3) so that the trenches are all filled (FIG. 2A); Etching an upper portion of the conductive film 3 so that the conductive film 3 remains at a position lower than the surface of the substrate 1 in the trench (FIG. 2B); Depositing an insulating film 4 on the upper surface of the structure (FIG. 2C); The deposited insulating film 4 is planarized so that the upper surface of the insulating film 4 is coplanar with the upper surface of the substrate 1 (Fig. 2D).

이하, 상기와 같이 구성된 본 발명 반도체 소자의 배선 형성방법을 좀 더 상세히 설명한다.Hereinafter, the wiring forming method of the semiconductor device of the present invention configured as described above will be described in more detail.

먼저, 도2a에 도시한 바와 같이 기판(1)의 상부에 산화막과 질화막을 순차적으로 증착하고, 그 증착된 산화막과 질화막을 사진식각공정을 통해 패터닝하여 상기 기판(1)의 일부를 노출시킨다.First, as shown in FIG. 2A, an oxide film and a nitride film are sequentially deposited on the substrate 1, and the deposited oxide film and the nitride film are patterned through a photolithography process to expose a portion of the substrate 1.

그 다음, 포토레지스트를 제거하고, 상기 질화막 패턴을 식각마스크로 사용하는 식각공정으로 상기 노출된 기판(1)을 식각하여 트랜치를 형성한다. Then, the photoresist is removed and the exposed substrate 1 is etched by an etching process using the nitride layer pattern as an etching mask to form a trench.                     

그 다음, 상기 구조의 상부전면에 절연막(2)을 증착한다. 이때의 절연막(2)은 상기 트랜치를 채우지 않도록 얇게 형성한다.Next, an insulating film 2 is deposited on the upper surface of the structure. At this time, the insulating film 2 is formed thin so as not to fill the trench.

그 다음, 상기 절연막(2)의 상부전면에 상기 트랜치가 모두 채워지도록 두꺼운 도전막(3)을 증착한다.Then, a thick conductive film 3 is deposited on the entire upper surface of the insulating film 2 so as to fill the trench.

그 다음, 도2b에 도시한 바와 같이 상기 증착된 도전막(3)의 상부일부를 제거하여 상기 트랜치의 저면부에 그 도전막(3)을 잔존시킨다.Next, as shown in FIG. 2B, the upper part of the deposited conductive film 3 is removed, and the conductive film 3 remains on the bottom of the trench.

그 다음, 도2c에 도시한 바와 같이 상기 구조의 상부전면에 절연막(4)을 증착한다.Next, as shown in Fig. 2C, an insulating film 4 is deposited on the upper surface of the structure.

그 다음, 도2d에 도시한 바와 같이 상기 절연막(4)을 평탄화하여 상기 트랜치의 상부측을 절연막(4)으로 채우며, 기판(1)의 표면을 노출시킨다.Next, as shown in FIG. 2D, the insulating film 4 is planarized to fill the upper side of the trench with the insulating film 4, thereby exposing the surface of the substrate 1.

이와 같은 공정으로 기판(1) 내에 매립된 도전막(3)인 배선을 형성할 수 있으며, 이후의 공정에서 반도체 소자를 기판(1)에 형성하고, 그 반도체 소자의 특정영역과 상기 도전막(3)을 연결하는 패턴을 형성한다.In such a process, the wiring which is the conductive film 3 embedded in the substrate 1 can be formed, and in a subsequent process, the semiconductor element is formed on the substrate 1, and the specific region of the semiconductor element and the conductive film ( 3) form a pattern to connect.

상기한 바와 같이 본 발명은 반도체 소자의 배선을 기판에 매립형으로 형성함으로써, 반도체 소자의 단차에 의한 배선의 단선을 방지하고, 깊은 콘택홀의 형성없이 배선을 형성하여 그 배선 형성의 신뢰성을 향상시키는 효과가 있다.As described above, according to the present invention, the wiring of the semiconductor element is formed on the substrate, thereby preventing the disconnection of the wiring due to the step of the semiconductor element, and forming the wiring without forming the deep contact hole, thereby improving the reliability of the wiring formation. There is.

Claims (1)

기판에 트랜치를 형성하고, 그 트랜치가 형성된 기판의 전면에 절연막을 증착한 후, 도전막을 상기 트랜치가 모두 채워지도록 증착하는 단계와; 상기 도전막의 상부일부를 식각하여 상기 트랜치 내에서 기판의 표면보다 낮은 위치에 도전막을 잔존시키는 단계와; 상기 구조의 상부전면에 절연막을 증착하는 단계와; 상기 증착한 절연막을 평탄화하여 그 절연막의 상부면이 기판의 상부면과 동일 평면상에 있도록 하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 배선 형성방법.Forming a trench in the substrate, depositing an insulating film on the entire surface of the substrate on which the trench is formed, and then depositing a conductive film so that the trenches are completely filled; Etching a portion of the upper portion of the conductive layer so that the conductive layer remains at a position lower than the surface of the substrate in the trench; Depositing an insulating film on the upper surface of the structure; And planarizing the deposited insulating film so that the upper surface of the insulating film is flush with the upper surface of the substrate.
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