KR100675569B1 - 반도체 장치용 테이프 캐리어, 이를 사용한 반도체 장치및 이들의 제조방법 - Google Patents
반도체 장치용 테이프 캐리어, 이를 사용한 반도체 장치및 이들의 제조방법 Download PDFInfo
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Abstract
Description
구리링의 폭 (㎛) | 절목 | 도금 | 파괴되기 시작한 온도 싸이클수 (회) | |
비교예 1 비교예 2 | 10 | 없음 | 전해 무전해 | 2300 1800 |
실시예 1 실시예 2 | 10 | 있음 | 전해 무전해 | 2300 2300 |
비교예 3 비교예 4 | 20 | 없음 | 전해 무전해 | 1900 2100 |
실시예 3 실시예 4 | 20 | 있음 | 전해 무전해 | 2300 2300 |
비교예 5 비교예 6 | 30 | 없음 | 전해 무전해 | 1800 2300 |
실시예 5 실시예 6 | 30 | 있음 | 전해 무전해 | 2300 2300 |
비교예 7 비교예 8 | 0 | - | 전해 무전해 | 1000 1000 |
절입구(㎛) | 원주길이에 대한 비율(%) | 땜납볼 탑재상의 문제점 유무 | |
비교예 9 | 0 | 0.0 | 없음 |
실시예 7 | 20 | 1.4 | 없음 |
실시예 8 | 30 | 2.1 | 없음 |
실시예 9 | 50 | 3.5 | 없음 |
비교예 10 | 60 | 4.2 | 있음 |
가스발취용 통로폭의 합계 (%) | 파괴하기 시작한 온도 싸이클수 (회) | |
실시예 10 | 4 | 2300 |
실시예 11 | 20 | 2300 |
실시예 12 | 30 | 1800 |
실시예 13 | 40 | 1800 |
비교예 11 | 50 | 1100 |
Claims (16)
- 가요성을 갖는 절연테이프의 한쪽 면에 금속 배선층을 형성하고, 다른 쪽 면에 개구되는 땜납볼용 비어홀의 외주연에 링 모양의 금속지주를 형성한 반도체 장치용 테이프 캐리어로서, 상기 금속지주에는 그 원주 방향 길이에 대해 4%이하의 폭을 갖는 절입구를 형성함을 특징으로 하는 반도체 장치용 테이프 캐리어.
- 가요성을 갖는 절연테이프의 한쪽 면에 금속 배선층을 형성하고, 다른쪽 면에 개구되는 땜납볼용 비어홀에 금속지주를 형성한 반도체 장치용 테이프 캐리어로서, 상기 금속지주는 일정한 간극을 두고 대칭되게 배치된 두 개이상의 원호상 부분으로 이루어지고, 이 간극의 합계 원주방향 길이에 대해 40%이하인 것을 특징으로하는 반도체 장치용 테이프 캐리어.
- 청구항 1 또는 2에 있어서,상기 금속지주의 표면에 니켈도금을 하고, 이 니켈도금 위에 은도금을 한 것을 특징으로하는 반도체 장치용 테이프 캐리어.
- 청구항 1또는 2에 있어서,상기 금속지주의 표면에 은도금 한 것을 특징으로 하는 반도체 장치용 테이프 캐리어.
- 가요성을 갖는 절연테이프의 양면에 금속박을 형성하고, 보호막의 형성, 에칭가공 및 보호막의 제거에 의해 한쪽 면에 반도체 칩을 탑재하기 위한 금속 배선층을 형성하고, 다른 한쪽 면의 소망위치에는 절연테이프를 노출시켜 상기 금속 배선층을 포함하는 한쪽 면을 수지막으로 보호하고, 상기 절연테이프의 노출부분을 에칭가공하여 비어홀을 상기 소망위치에 형성하고, 이 비어홀과 비어홀의 외주연중 일부에 수지의 보호막을 형성하여 에칭가공함으로써, 보호막으로부터 노출된 부분의 금속박을 제거하며, 이때에 비어홀의 외주연에 있는 금속박의 제거 폭이 이 외주연의 원주방향 길이에 대하여 4%이하가 되도록 하고, 잔류된 금속박에 의해 비어홀의 외주연에 있는 링 모양의 금속지주를 형성하여, 절연테이프 양면에 형성된 보호막을 제거하는 것을 특징으로 하는 반도체 장치용 테이프 캐리어의 제조방법.
- 가요성을 갖는 절연 테이프의 양면에 금속박을 형성하고, 보호막의 형성, 에칭가공 및 보호막의 제거에 의해 한쪽 면에 반도체 칩을 탑재하기 위한 금속 배선층을 형성하고, 다른 한쪽 면의 소망위치에는 절연테이프를 노출시켜, 상기 금속 배선층을 포함하는 한쪽 면을 수지막으로 보호하고, 상기 절연테이프의 노출부분을 에칭가공하여 비어홀을 상기 소망위치에 형성하고, 이 비어홀과 비어홀의 외주연 중 복수의 개소에 수지의 보호막을 형성하여 에칭가공을 함으로써, 보호막으로부터 노출된 부분의 금속박을 제거하며, 잔류된 금속박에 의해 비어홀의 외주연에 있는 금속지주를 형성하여 절연테이프의 양면에 형성된 보호막을 제거하는 각각의 공정으로 이루어지고, 상기 금속지주는 대칭적으로 간극을 두고 배치된 두 개 이상의 원호상 부분으로 이루어지며, 이 간극의 합계가 원주 방향 길이에 대하여 40%이하가 되도록 하는 것을 특징으로 하는 반도체 장치용 테이프 캐리어의 제조방법.
- 청구항 5 또는 6에 기재된 반도체 장치용 테이프 캐리어의 제조방법에 추가하여 상기 금속지주의 표면에 니켈도금을 실시하고, 그 위에 은도금을 실시하는 것을 특징으로 하는 반도체 장치용 테이프 캐리어의 제조방법.
- 청구항 5또는 6에 기재된 반도체 장치용 테이프 캐리어의 제조방법에 추가하여 상기 금속지주의 표면에 은도금을 실시함을 특징으로 하는 반도체 장치용 테이프 캐리어의 제조방법.
- 청구항 1 내지 청구항 2중 어느 한 항에 기재된 반도체 장치용 테이프 캐리어를 사용하여, 상기 금속 배선층에 반도체 칩을 접속시키고, 상기 비어홀 및 금속지주를 덮을 수 있게 땜납볼을 탑재하고, 금속 배선층과 땜납볼을 전기적으로 접속시킨 것을 특징으로 하는 반도체 장치.
- 청구항 5 또는 청구항 6에 기재된 반도체 장치용 테이프 캐리어의 제조방법에 추가하여 상기 금속 배선층에 반도체 칩을 접속시키고, 상기 비어홀 및 이 비어홀에 인접한 금속박 부분을 덮을 수 있게 땜납볼을 탑재하고, 금속 배선층과 땜납볼을 전기적으로 접속시킨 것을 특징으로 하는 반도체 장치의 제조방법.
- 소정의 위치에 비어홀을 관통시키고, 반도체 칩을 탑재하기 위한 절연테이프와, 상기 반도체 칩에 전기적 접속이 되도록 절연테이프의 표면에 형성된 금속 배선층과, 이 절연테이프의 이면에 형성되고, 상기 비어홀에 의해서 금속 배선층에 접속되는 땜납볼과, 상기 절연테이프의 이면에서 땜납볼이 배열설치되는 위치에 상기 땜납볼과 접합하는 링 모양의 금속지주로 이루어지고, 이 금속지주에는 그 원주방향 길이에 대해 4%이하의 폭을 갖는 절입구를 형성한 것을 특징으로하는 반도체 장치용 테이프 캐리어.
- 소정의 위치에 비어홀을 관통시키고, 반도체 칩을 탑재하기 위한 절연테이프와, 상기 반도체 칩에 전기적 접속이 되도록 절연테이프의 표면에 형성된 금속 배선층과, 이 절연테이프의 이면에 형성되고, 상기 비어홀에 의해서 금속 배선층에 접속되는 땜납볼과, 상기 절연테이프의 이면에서 땜납볼이 배열설치되는 위치에 상기 땜납볼과 접합하는 금속지주로 이루어지고, 이 금속지주는 대칭적으로 간극을 두고 배치된 두 개 이상의 원호상 부분으로 이루어지고, 이 간극의 합계가 원주 방향 길이에 대해 40%이하인 것을 특징으로 하는 반도체 장치용 테이프 캐리어.
- 청구항 3에 기재된 반도체 장치용 테이프 캐리어를 사용하여, 상기 금속 배선층에 반도체 칩을 접속시키고, 상기 비어홀 및 금속지주를 덮을 수 있게 땜납볼을 탑재하고, 금속 배선층과 땜납볼을 전기적으로 접속시킨 것을 특징으로 하는 반도체 장치.
- 청구항 4에 기재된 반도체 장치용 테이프 캐리어를 사용하여, 상기 금속 배선층에 반도체 칩을 접속시키고, 상기 비어홀 및 금속지주를 덮을 수 있게 땜납볼을 탑재하고, 금속 배선층과 땜납볼을 전기적으로 접속시킨 것을 특징으로 하는 반도체 장치.
- 청구항 7에 기재된 반도체 장치용 테이프 캐리어의 제조방법에 추가하여 상기 금속 배선층에 반도체 칩을 접속시키고, 상기 비어홀 및 이 비어홀에 인접한 금속박 부분을 덮을 수 있게 땜납볼을 탑재하고, 금속 배선층과 땜납볼을 전기적으로 접속시킨 것을 특징으로 하는 반도체 장치의 제조방법.
- 청구항 8에 기재된 반도체 장치용 테이프 캐리어의 제조방법에 추가하여 상기 금속 배선층에 반도체 칩을 접속시키고, 상기 비어홀 및 이 비어홀에 인접한 금속박 부분을 덮을 수 있게 땜납볼을 탑재하고, 금속 배선층과 땜납볼을 전기적으로 접속시킨 것을 특징으로 하는 반도체 장치의 제조방법.
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US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
KR100541649B1 (ko) * | 2003-09-03 | 2006-01-11 | 삼성전자주식회사 | 테이프 배선 기판과 그를 이용한 반도체 칩 패키지 |
US8308922B2 (en) * | 2004-01-29 | 2012-11-13 | Siemens Aktiengesellschaft | Electrochemical transducer array and use thereof |
JP2006202991A (ja) * | 2005-01-20 | 2006-08-03 | Sony Corp | 回路基板及びその製造方法、並びに半導体パッケージ及びその製造方法 |
KR100837269B1 (ko) * | 2006-05-22 | 2008-06-11 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 및 그 제조 방법 |
JP5078500B2 (ja) * | 2006-08-30 | 2012-11-21 | 三洋電機株式会社 | 素子搭載用基板、半導体モジュールおよび携帯機器 |
US8030780B2 (en) * | 2008-10-16 | 2011-10-04 | Micron Technology, Inc. | Semiconductor substrates with unitary vias and via terminals, and associated systems and methods |
EP2405468A1 (en) | 2010-07-05 | 2012-01-11 | ATOTECH Deutschland GmbH | Method to form solder deposits on substrates |
CN102064135B (zh) * | 2010-10-21 | 2015-07-22 | 日月光半导体制造股份有限公司 | 具有金属柱的芯片及具有金属柱的芯片的封装结构 |
JP2012227328A (ja) * | 2011-04-19 | 2012-11-15 | Sony Corp | 半導体装置、半導体装置の製造方法、固体撮像装置及び電子機器 |
US9674955B2 (en) * | 2011-11-09 | 2017-06-06 | Lg Innotek Co., Ltd. | Tape carrier package, method of manufacturing the same and chip package |
TWI544593B (zh) * | 2013-09-09 | 2016-08-01 | 矽品精密工業股份有限公司 | 半導體裝置及其製法 |
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