KR100623587B1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
KR100623587B1
KR100623587B1 KR1020000036788A KR20000036788A KR100623587B1 KR 100623587 B1 KR100623587 B1 KR 100623587B1 KR 1020000036788 A KR1020000036788 A KR 1020000036788A KR 20000036788 A KR20000036788 A KR 20000036788A KR 100623587 B1 KR100623587 B1 KR 100623587B1
Authority
KR
South Korea
Prior art keywords
film
bit line
forming
spacer
vapor deposition
Prior art date
Application number
KR1020000036788A
Other languages
Korean (ko)
Other versions
KR20020002578A (en
Inventor
김태경
윤종윤
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020000036788A priority Critical patent/KR100623587B1/en
Publication of KR20020002578A publication Critical patent/KR20020002578A/en
Application granted granted Critical
Publication of KR100623587B1 publication Critical patent/KR100623587B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 후속 열공정시 발생하는 비트라인배선막의 산화 및 리프팅 현상을 방지하는데 적합한 반도체소자 및 그의 제조 방법에 관한 것으로, 본 발명의 반도체소자는 확산방지막, 텅스텐막, 하드마스크의 적층구조의 측벽에 접속되는 스페이서를 포함하는 반도체소자에 있어서, 후속 열공정시 상기 하드마스크와 스페이서의 산소확산경로에 의해 발생되는 상기 텅스텐막의 산화 및 리프팅현상을 방지하기 위해 상기 텅스텐막의 양측벽에 실리사이드막이 접속된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for preventing oxidation and lifting of a bit line wiring film generated during a subsequent thermal process, and to a method of manufacturing the semiconductor device. In a semiconductor device including a spacer to be connected, a silicide film is connected to both side walls of the tungsten film in order to prevent oxidation and lifting of the tungsten film caused by the oxygen diffusion path between the hard mask and the spacer during a subsequent thermal process.

비트라인, 리프팅현상, 텅스텐, 실리사이드, 산소확산Bit line, lifting phenomenon, tungsten, silicide, oxygen diffusion

Description

반도체소자 및 그의 제조 방법{SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME} Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}             

도 1a 내지 1c는 종래기술에 따른 비트라인의 형성 방법을 도시한 도면,1A to 1C illustrate a method of forming a bit line according to the prior art;

도 2 는 본 발명의 실시예에 따른 비트라인의 구조 단면도,2 is a structural cross-sectional view of a bit line according to an embodiment of the present invention;

도 3a 내지 3d는 본 발명의 실시예에 따른 비트라인의 형성 방법을 도시한 도면.
3A to 3D illustrate a method of forming a bit line according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체기판 22 : 제 1 층간절연막21 semiconductor substrate 22 first interlayer insulating film

23 : 티타늄 24 : 티타늄질화막23: titanium 24: titanium nitride film

25 : 텅스텐 26 : 실리콘옥시질화막25 tungsten 26 silicon oxynitride film

27 : 실리콘질화막 28 : 폴리실리콘27 silicon nitride film 28 polysilicon

29 : 실리사이드 30 : 측벽스페이서29: silicide 30: side wall spacer

31 : 제 2 층간절연막
31: second interlayer insulating film

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 텅스텐비트라인의 신뢰성을 향상시키도록 한 반도체소자의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device to improve the reliability of the tungsten bit line.

최근에, 텅스텐을 배선막으로 이용하는 비트라인에 있어, 후속 캐패시터 형성을 위한 열공정시 상기 텅스텐배선막의 리프팅 및 산화를 방지하기 위한 방법들이 제안되고 있다.Recently, in a bit line using tungsten as a wiring film, methods for preventing the lifting and oxidation of the tungsten wiring film in a thermal process for forming a subsequent capacitor have been proposed.

도 1a 내지 도 1c는 종래기술에 따른 비트라인의 형성 방법을 도시한 도면이다.1A to 1C illustrate a method of forming a bit line according to the prior art.

도 1a에 도시된 바와 같이, 소정공정이 완료된 반도체기판(11)상에 제 1 층간절연막(12)을 증착한 다음, 상기 제 1 층간절연막(12)상에 접착층(Glue layer)으로서 티타늄(Ti)(13)을 증착한다. 이어 상기 티타늄(13)상에 확산방지막으로서 티타늄질화막(TiN)(14)를 증착하고, 비트라인배선막인 텅스텐(15)과 후속 마스크공정 및 식각공정을 원활하게 하기 위한 난반사방지막으로서 실리콘옥시질화막(SiON) (16)을 순차적으로 증착한 다음, 하드마스크층으로서 실리콘질화막(SiNx)(17)을 증착한다.As shown in FIG. 1A, a first interlayer insulating film 12 is deposited on a semiconductor substrate 11 on which a predetermined process is completed, and then titanium (Ti) is formed as a glue layer on the first interlayer insulating film 12. 13). Subsequently, a titanium nitride film (TiN) 14 is deposited on the titanium 13 as a diffusion barrier film, and a silicon oxynitride film is used as an antireflection film for smoothing subsequent mask and etching processes with tungsten 15 as a bit line wiring film. (SiON) 16 are sequentially deposited, and then a silicon nitride film (SiN x ) 17 is deposited as a hard mask layer.

도 1b에 도시된 바와 같이, 마스크공정 및 식각 공정을 통해 실리콘옥시질화막(16), 텅스텐(15), 티타늄질화막(14), 티타늄(13)의 적층구조로 이루어진 비트라인패턴을 형성한 후, 상기 비트라인패턴의 전면에 스페이서용 실리콘질화막(18)을 증착한다. As shown in FIG. 1B, after forming a bit line pattern having a stacked structure of a silicon oxynitride layer 16, a tungsten 15, a titanium nitride layer 14, and a titanium 13 through a mask process and an etching process, The silicon nitride film 18 for the spacer is deposited on the entire surface of the bit line pattern.                         

도 1c에 도시된 바와 같이, 상기 스페이서용 실리콘질화막(18)을 전면식각하여 상기 비트라인패턴의 양측벽에 접하는 측벽스페이서(18a)를 형성한 다음, 상기 측벽스페이서(18a) 및 비트라인패턴을 포함한 전면에 제 2 층간절연막(19)을 형성한다.As shown in FIG. 1C, the silicon nitride film 18 for the spacer is etched to form a sidewall spacer 18a which is in contact with both sidewalls of the bitline pattern, and then the sidewall spacer 18a and the bitline pattern are formed. A second interlayer insulating film 19 is formed on the entire surface thereof.

이어 후속 열공정이 산소분위기에서 진행될 경우, 텅스텐과 다른 물질들간의 열팽창계수 차이에 기인하여 상기 실리콘질화막(17)과 측벽스페이 (18a)의 계면과, 측벽스페이서(18a)와 제 1 층간절연막(12)의 계면에 산소의 확산경로가 형성되고, 상기 확산경로를 통해서 확산된 산소가 텅스텐(15)과 산화반응을 일으키므로써 비트라인배선막인 텅스텐(15)의 산화와 리프팅(Lifting) 현상이 발생되어, 후속 공정 진행을 어렵게 한다.Subsequently, when the subsequent thermal process is performed in an oxygen atmosphere, the interface between the silicon nitride film 17 and the sidewall spacers 18a, the sidewall spacers 18a, and the first interlayer insulating film 12 are caused by the difference in the coefficient of thermal expansion between tungsten and other materials. Oxygen diffusion path is formed at the interface of the ()), and oxygen diffused through the diffusion path causes an oxidation reaction with the tungsten 15, thereby causing oxidation and lifting of the tungsten 15, which is a bit line wiring film, to occur. This makes it difficult to proceed with subsequent processes.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 후속 산소분위기의 열공정시에 산소의 확산경로를 봉쇄하거나 감소시켜 비트라인의 배선막인 텅스텐의 산화 및 리프팅현상을 방지하는데 적합한 반도체소자의 제조 방법을 제공함에 그 목적이 있다.
The present invention has been made to solve the problems of the prior art, a semiconductor device suitable for preventing the oxidation and lifting of the tungsten, the wiring film of the bit line by blocking or reducing the diffusion path of oxygen during the thermal process of the oxygen atmosphere in the subsequent Its purpose is to provide a method for producing the same.

상기의 목적을 달성하기 위한 본 발명의 반도체소자는 확산방지막, 텅스텐막및 하드마스크의 순서로 적층된 비트라인; 상기 비트라인의 양측벽에 접속되는 스페이서; 및 후속 열공정시 상기 하드마스크와 스페이서의 산소확산경로에 의해 발생되는 상기 텅스텐막의 산화 및 리프팅현상을 방지하기 위해 상기 텅스텐막의 양측벽에 접속된 실리사이드막을 포함하는 것을 특징으로 하고, 본 발명에 따른 반도체소자의 제조 방법은 소정공정이 완료된 반도체기판상에 제 1 층간절연막을 형성하는 단계; 상기 제 1 층간절연막상에 텅스텐막을 포함하는 적층구조의 비트라인을 형성하는 단계; 상기 비트라인상에 폴리실리콘을 형성한 후, 상기 폴리실리콘을 열처리하여 상기 비트라인의 텅스텐막의 양측벽에 접하는 실리사이드막을 형성하는 단계; 및 상기 실리사이드막 및 비트라인을 포함한 전면에 스페이서용 절연막을 형성한 후, 전면식각하여 상기 실리사이드막 및 비트라인의 양측벽에 접하는 스페이서를 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A semiconductor device of the present invention for achieving the above object is a bit line stacked in the order of the diffusion barrier, tungsten film and hard mask; Spacers connected to both sidewalls of the bit line; And a silicide film connected to both sidewalls of the tungsten film in order to prevent oxidation and lifting of the tungsten film generated by the oxygen diffusion path between the hard mask and the spacer during a subsequent thermal process. A device manufacturing method includes forming a first interlayer insulating film on a semiconductor substrate on which a predetermined process is completed; Forming a bit line of a stacked structure including a tungsten film on the first interlayer insulating film; After forming polysilicon on the bit line, heat treating the polysilicon to form a silicide film in contact with both sidewalls of the tungsten film of the bit line; And forming a spacer insulating layer on the entire surface including the silicide layer and the bit line and then etching the entire surface to form a spacer in contact with both sidewalls of the silicide layer and the bit line.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2는 본 발명의 실시예에 따른 비트라인을 도시한 구조 단면도로서, 본 발명의 실시예에 따른 비트라인은 티타늄(23a), 티타늄질화막(24a), 텅스텐(25a), 실리콘옥시질화막(26a), 실리콘질화막(27a)의 적층구조로 이루어지고, 상기 비트라인의 양측벽에는 측벽스페이서(30)가 형성된다.2 is a cross-sectional view illustrating a bit line according to an exemplary embodiment of the present invention. The bit line according to the exemplary embodiment of the present invention may include titanium 23a, titanium nitride layer 24a, tungsten 25a, and silicon oxynitride layer 26a. ), A silicon nitride film 27a is laminated, and sidewall spacers 30 are formed on both sidewalls of the bit line.

그리고, 상기 티타늄(23a), 티타늄질화막(24a) 및 텅스텐(25a)의 양측벽에는 실리사이드막(29)이 형성되는데, 상기 실리사이드막(29)는 후속 열공정시 상기 실리콘질화막(27a)과 측벽스페이서(30)의 산소확산경로에 의해 발생되는 상기 텅스텐(25)의 산화 및 리프팅현상을 방지하기 위함이다. 여기서, 상기 실리사이드 막(29)은 도우프드 폴리실리콘 또는 언도우프드 폴리실리콘을 열처리하여 형성되며, 50Å∼500Å의 두께로 형성된다. The silicide layer 29 is formed on both sidewalls of the titanium 23a, the titanium nitride layer 24a, and the tungsten 25a, and the silicide layer 29 is formed of the silicon nitride layer 27a and the sidewall spacers in a subsequent thermal process. This is to prevent oxidation and lifting of the tungsten 25 generated by the oxygen diffusion path (30). Here, the silicide film 29 is formed by heat treatment of the doped polysilicon or undoped polysilicon, it is formed to a thickness of 50 ~ 500Å.

도 3a 내지 도 3d는 본 발명의 실시예에 따른 비트라인의 형성 방법을 도시한 도면이다.3A to 3D illustrate a method of forming a bit line according to an exemplary embodiment of the present invention.

도 3a에 도시된 바와 같이, 소정공정이 완료된 반도체기판(21)상에 제 1 층간절연막(22)을 증착한 다음, 상기 제 1 층간절연막(22)상에 접착층(Glue layer)으로서 티타늄(Ti)(23)을 증착하되, 물리적기상증착법(Physical Vapor Deposition; PVD) 또는 화학적기상증착법(Chemical Vapor Deposition; CVD) 중 어느 하나를 이용하여 500Å∼1000Å두께로 증착한다. As shown in FIG. 3A, a first interlayer insulating film 22 is deposited on the semiconductor substrate 21 on which a predetermined process is completed, and then titanium (Ti) is deposited on the first interlayer insulating film 22. (23) is deposited, using any one of physical vapor deposition (PVD) or chemical vapor deposition (CVD) to a thickness of 500 ~ 1000Å.

이어 상기 티타늄(23)상에 확산방지막으로서 티타늄질화막(TiN)(24)를 증착하고, 비트라인배선막인 텅스텐(25)과 후속 마스크공정 및 식각공정을 원활하게 하기 위한 난반사방지막(Anti Reflective Coating layer; ARC)으로서 실리콘옥시질화막(SiON)(26)을 순차적으로 증착한다. 이 때, 상기 실리콘옥시질화막(26)은 저압화학적기상증착법(Low Pressure-CVD) 또는 플라즈마화학기상증착법(Plasma Enhanced CVD) 중 어느 하나를 이용하여 증착한다. 이어 상기 실리콘옥시질화막(26)상에 하드마스크층으로서 실리콘질화막 (SiNx)(27)을 증착한다.Subsequently, a titanium nitride layer (TiN) 24 is deposited on the titanium 23 as a diffusion barrier layer, and an anti-reflective coating layer to smooth tungsten 25, which is a bit line wiring layer, and subsequent masking and etching processes is performed. A silicon oxynitride film (SiON) 26 is sequentially deposited as a layer (ARC). At this time, the silicon oxynitride layer 26 is deposited using either low pressure chemical vapor deposition (Low Pressure-CVD) or plasma enhanced chemical vapor deposition (Plasma Enhanced CVD). Subsequently, a silicon nitride film (SiN x ) 27 is deposited on the silicon oxynitride film 26 as a hard mask layer.

도 3b에 도시된 바와 같이, 마스크공정 및 식각 공정을 통해 실리콘질화막 (27a), 실리콘옥시질화막(26a), 텅스텐(25a), 티타늄질화막(24a), 티타늄(23a)의 적층구조로 이루어진 비트라인패턴을 형성한 후, 상기 비트라인패턴의 전면에 폴리실리콘(28)을 증착한다. 이 때, 상기 폴리실리콘(28)은 도우프드 폴리실리콘(Doped polysilicon) 또는 언도우프드 폴리실리콘(Undoped polysilicon) 중 어느 하나를 이용하며, 화학적기상증착법(CVD), 플라즈마화학적기상증착법(PECVD), 물리적기상증착법(PVD) 중 어느 하나의 증착법을 이용하여 50Å∼500Å두께로 증착한다.As shown in FIG. 3B, a bit line including a stacked structure of a silicon nitride film 27a, a silicon oxynitride film 26a, a tungsten 25a, a titanium nitride film 24a, and a titanium 23a through a mask process and an etching process is performed. After the pattern is formed, polysilicon 28 is deposited on the entire surface of the bit line pattern. At this time, the polysilicon 28 uses any one of doped polysilicon or undoped polysilicon, chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), The deposition is carried out at a thickness of 50 kV to 500 kV using any one of physical vapor deposition (PVD).

도 3c에 도시된 바와 같이, 상기 폴리실리콘(28)을 열처리하여 상기 티타늄 (23a), 티타늄질화막(24a), 텅스텐(25a)의 표면에 실리사이드(29)를 형성한다. 이 때, 상기 실리사이드(29)를 형성하기 위한 열처리는 노(Furnace)열처리 또는 급속열처리(Rapid Thermal Annealing) 중 어느 하나의 열처리를 이용하며, 400℃∼1000℃에서 30초∼120분동안 실시한다.As shown in FIG. 3C, the polysilicon 28 is heat-treated to form silicide 29 on the surfaces of the titanium 23a, the titanium nitride film 24a, and the tungsten 25a. At this time, the heat treatment for forming the silicide 29 is carried out using a heat treatment of any one of furnace heat treatment or rapid thermal annealing, and is carried out for 30 seconds to 120 minutes at 400 ℃ to 1000 ℃. .

이어 상기 실리사이드(29)가 형성되지 않은 미반응막, 즉 제 1 층간절연막 (22), 실리콘옥시질화막(26), 실리콘질화막(27)상의 폴리실리콘을 건식식각 또는 습식식각하여 제거한다.Subsequently, polysilicon on the unreacted layer, that is, the first interlayer insulating layer 22, the silicon oxynitride layer 26, and the silicon nitride layer 27, on which the silicide 29 is not formed, is removed by dry etching or wet etching.

도 3d에 도시된 바와 같이, 실리사이드(29) 및 비트라인패턴을 포함한 전면에 스페이서용 실리콘질화막을 증착한 다음, 상기 스페이서용 실리콘질화막을 전면식각하여 상기 비트라인패턴 및 실리사이드(29)의 양측벽에 접하는 측벽스페이서 (30)를 500Å∼3000Å두께로 형성한다. 이어 상기 측벽스페이서(30) 및 비트라인패턴을 포함한 전면에 제 2 층간절연막(31)을 형성한다. 이 때, 상기 측벽스페이서 (30)는 실리콘질화막 대신 실리콘산화막 또는 실리콘산화질화막을 이용할 수 있다. 그리고, 상기 제 2 층간절연막(31)은 SiH4 또는 TEOS(Tetra Ethyl Ortho Silicate)를 원료로 사용한 플라즈마화학적기상증착법(PECVD) 또는 TEOS와 오존(O3)를 원료로 사용한 화학기상증착법(CVD) 중 어느 하나를 이용하여 200℃∼600℃에서 증착한다.As shown in FIG. 3D, a silicon nitride film for a spacer is deposited on the entire surface including the silicide 29 and the bit line pattern, and then the silicon nitride film for the spacer is etched over the both sides of the bit line pattern and the silicide 29. The sidewall spacers 30 in contact with each other are formed to have a thickness of 500 kV to 3000 kPa. Subsequently, a second interlayer insulating layer 31 is formed on the entire surface including the sidewall spacers 30 and the bit line patterns. In this case, the sidewall spacer 30 may use a silicon oxide film or a silicon oxynitride film instead of the silicon nitride film. In addition, the second interlayer insulating layer 31 may be formed by plasma chemical vapor deposition (PECVD) using SiH 4 or TEOS (Tetra Ethyl Ortho Silicate) as a raw material, or chemical vapor deposition (CVD) using TEOS and ozone (O 3 ) as raw materials. It deposits at 200 degreeC-600 degreeC using either.

이어 후속 공정으로 캐패시터전극(도시 생략)을 형성한다.Subsequently, a capacitor electrode (not shown) is formed in a subsequent process.

상술한 바와 같이, 상기 비트라이배선막인 텅스텐(25a)의 양측벽에 실리사이드(29)를 형성하므로써 후속 캐패시터를 형성하기 위한 열공정시 상기 실리콘질화막(27a)과 측벽스페이서(30)의 계면과, 측벽스페이서(30)와 제 1 층간절연막(22)의 계면에 형성되는 산소의 확산경로를 억제한다. 그리고, 상기 실리사이드(29)는 상기 측벽스페이서(30)와 텅스텐(25a)의 열팽창계수에 따른 계면특성을 향상시키기 위한 버퍼층의 역할을 한다.As described above, an interface between the silicon nitride film 27a and the sidewall spacer 30 during the thermal process for forming a subsequent capacitor by forming the silicide 29 on both side walls of the tungsten 25a as the bit line wiring film, The diffusion path of oxygen formed at the interface between the sidewall spacer 30 and the first interlayer insulating film 22 is suppressed. In addition, the silicide 29 serves as a buffer layer to improve the interfacial properties according to the thermal expansion coefficient of the sidewall spacer 30 and tungsten 25a.

상기한 본 발명의 실시예는 배선막으로 다른 금속층을 이용할 수 있고, 텅스텐을 이용하여 워드라인을 형성하는 경우에도 적용할 수 있을 것으로 사료된다.The above-described embodiment of the present invention may be applied to another metal layer as a wiring film, and may also be applicable to the case of forming a word line using tungsten.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이, 본 발명의 반도체소자의 제조 방법은 비트라인배선막인 텅스텐의 측벽에 산소의 확산경로의 형성을 방지하므로써 후속 캐패시터 열공정시 비트라인배선막인 텅스텐의 산화 및 리프팅현상을 방지하여 소자의 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method of manufacturing a semiconductor device of the present invention prevents the formation of diffusion paths of oxygen on the sidewalls of tungsten, which is a bit line wiring film, thereby preventing oxidation and lifting of tungsten, which is a bit line wiring film, during subsequent capacitor thermal processes. There is an effect that can improve the reliability of the device.

Claims (16)

확산방지막, 텅스텐막 및 하드마스크의 순서로 적층된 비트라인;A bit line stacked in order of a diffusion barrier film, a tungsten film, and a hard mask; 상기 비트라인의 양측벽에 접속되는 스페이서; 및Spacers connected to both sidewalls of the bit line; And 후속 열공정시 상기 하드마스크와 스페이서의 산소확산경로에 의해 발생되는 상기 텅스텐막의 산화 및 리프팅현상을 방지하기 위해 상기 텅스텐막의 양측벽에 접속된 실리사이드막Silicide films connected to both side walls of the tungsten film to prevent oxidation and lifting of the tungsten film caused by oxygen diffusion path between the hard mask and the spacer during the subsequent thermal process. 을 포함하는 반도체 소자.Semiconductor device comprising a. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 텅스텐막은 물리적기상증착법 또는 화학적기상증착법 중 어느 하나의 증착법을 이용하여 500Å∼1000Å두께로 형성된 것을 특징으로 하는 반도체 소자.And the tungsten film is formed to have a thickness of 500 kV to 1000 kV using any one of physical vapor deposition and chemical vapor deposition. 제 1 항에 있어서,The method of claim 1, 상기 확산방지막은 티타늄질화막인 것을 특징으로 하는 반도체 소자.The diffusion barrier is a semiconductor device, characterized in that the titanium nitride film. 제 1 항에 있어서,The method of claim 1, 상기 하드마스크는 실리콘옥시질화막인 것을 특징으로 하는 반도체 소자.The hard mask is a semiconductor device, characterized in that the silicon oxynitride film. 제 1 항에 있어서,The method of claim 1, 상기 스페이서는 실리콘질화막, 실리콘산화막 또는 실리콘산화질화막 중 어느 하나인 것을 특징으로 하는 반도체 소자.The spacer is any one of a silicon nitride film, a silicon oxide film or a silicon oxynitride film. 반도체소자의 제조 방법에 있어서,In the manufacturing method of a semiconductor device, 소정공정이 완료된 반도체기판상에 제 1 층간절연막을 형성하는 단계;Forming a first interlayer insulating film on the semiconductor substrate on which a predetermined process is completed; 상기 제 1 층간절연막상에 텅스텐막을 포함하는 적층구조의 비트라인을 형성하는 단계;Forming a bit line of a stacked structure including a tungsten film on the first interlayer insulating film; 상기 비트라인상에 폴리실리콘을 형성한 후, 상기 폴리실리콘을 열처리하여 상기 비트라인의 텅스텐막의 양측벽에 접하는 실리사이드막을 형성하는 단계; 및After forming polysilicon on the bit line, heat treating the polysilicon to form a silicide film in contact with both sidewalls of the tungsten film of the bit line; And 상기 실리사이드막 및 비트라인을 포함한 전면에 스페이서용 절연막을 형성한 후, 전면식각하여 상기 실리사이드막 및 비트라인의 양측벽에 접하는 스페이서를 형성하는 단계Forming a spacer insulating layer on the entire surface including the silicide layer and the bit line, and then etching the entire surface to form a spacer in contact with both sidewalls of the silicide layer and the bit line 를 포함하는 비트라인의 형성 방법.Bit line forming method comprising a. 제 7 항에 있어서,The method of claim 7, wherein 상기 비트라인을 형성하는 단계에서,In forming the bit line, 상기 텅스텐막은 물리적기상증착법 또는 화학적기상증착법을 이용하여 500Å∼1000Å두께로 형성하는 것을 특징으로 하는 비트라인의 형성 방법.And the tungsten film is formed to have a thickness of 500 kV to 1000 kV by physical vapor deposition or chemical vapor deposition. 제 7 항에 있어서,The method of claim 7, wherein 상기 실리사이드막을 형성하는 단계에서,In the forming of the silicide film, 상기 열처리는 노열처리 또는 급속열처리를 이용하여 400℃∼1000℃에서 30초∼120분동안 이루어지는 것을 특징으로 하는 비트라인의 형성 방법.And the heat treatment is performed for 30 seconds to 120 minutes at 400 ° C to 1000 ° C using furnace heat treatment or rapid heat treatment. 제 7 항에 있어서,The method of claim 7, wherein 상기 실리사이드막을 형성하는 단계에서,In the forming of the silicide film, 상기 폴리실리콘은 도우프드 폴리실리콘, 언도우프드 폴리실리콘 중 어느 하나를 이용하되, 화학적기상증착법, 플라즈마화학적기상증착법 또는 물리적기상증착법 중 어느 하나를 이용하여 50Å∼500Å의 두께로 형성하는 것을 특징으로 하는 비트라인의 형성 방법.The polysilicon may be formed using any one of doped polysilicon and undoped polysilicon, and formed using a chemical vapor deposition method, a plasma chemical vapor deposition method, or a physical vapor deposition method to a thickness of 50 μs to 500 μs. How to form a bit line. 제 7 항에 있어서,The method of claim 7, wherein 상기 스페이서를 형성하는 단계에서,In the forming of the spacer, 상기 스페이서용 절연막은 실리콘질화막, 실리콘산화막 또는 실리콘산화질화막 중 어느 하나를 이용하는 것을 특징으로 하는 비트라인의 형성 방법.And a silicon nitride film, a silicon oxide film, or a silicon oxynitride film. 제 7 항에 있어서,The method of claim 7, wherein 상기 스페이서를 형성하는 단계에서,In the forming of the spacer, 상기 스페이서는 500Å∼3000Å의 두께로 형성되는 것을 특징으로 하는 비트라인의 형성 방법.And the spacer is formed to a thickness of 500 mV to 3000 mV. 제 7 항 또는 제 8 항에 있어서,The method according to claim 7 or 8, 상기 비트라인을 형성하는 단계에서,In forming the bit line, 상기 비트라인은 티타늄, 티타늄질화막, 텅스텐, 실리콘옥시질화막, 실리콘질화막의 적층구조로 이루어지는 것을 특징으로 하는 비트라인의 형성 방법.And the bit line comprises a stacked structure of titanium, titanium nitride, tungsten, silicon oxynitride and silicon nitride. 제 13 항에 있어서,The method of claim 13, 상기 실리콘옥시질화막은 저압 또는 플라즈마방법으로 형성하는 것을 특징으로 하는 비트라인의 형성 방법.And forming the silicon oxynitride layer by a low pressure or plasma method. 제 7 항에 있어서,The method of claim 7, wherein 상기 스페이서를 형성하는 단계후에, After the step of forming the spacer, 상기 스페이서를 포함한 전면에 제 2 층간절연막을 형성하는 단계를 더 포함하여 이루어짐을 특징으로 하는 비트라인의 형성 방법.And forming a second interlayer insulating film on the entire surface including the spacers. 제 15 항에 있어서,The method of claim 15, 상기 제 2 층간절연막은 SiH4 또는 TEOS를 원료로 사용한 플라즈마화학적기상증착법 또는 TEOS와 오존을 원료로 사용한 화학적기상증착법 중 어느 하나를 이용하여 200℃∼600℃에서 형성하는 것을 특징으로 하는 비트라인의 형성 방법.The second interlayer insulating film is formed at 200 ° C. to 600 ° C. by using any one of plasma chemical vapor deposition using SiH 4 or TEOS or chemical vapor deposition using TEOS and ozone as raw materials. Forming method.
KR1020000036788A 2000-06-30 2000-06-30 Semiconductor device and method for manufacturing the same KR100623587B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000036788A KR100623587B1 (en) 2000-06-30 2000-06-30 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000036788A KR100623587B1 (en) 2000-06-30 2000-06-30 Semiconductor device and method for manufacturing the same

Publications (2)

Publication Number Publication Date
KR20020002578A KR20020002578A (en) 2002-01-10
KR100623587B1 true KR100623587B1 (en) 2006-09-12

Family

ID=19675099

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000036788A KR100623587B1 (en) 2000-06-30 2000-06-30 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR100623587B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3586268B2 (en) 2002-07-09 2004-11-10 株式会社東芝 Semiconductor device and manufacturing method thereof
US7776744B2 (en) * 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122747A (en) * 1993-10-22 1995-05-12 Sony Corp Formation of gate electrode structure
KR19990004862A (en) * 1997-06-30 1999-01-25 김영환 Semiconductor device manufacturing method
KR19990041628A (en) * 1997-11-24 1999-06-15 구본준 Manufacturing Method of Semiconductor Device
KR100210853B1 (en) * 1996-08-16 1999-07-15 구본준 Conducting line of semiconductor device and method of manufacturing the same
KR19990065425A (en) * 1998-01-13 1999-08-05 윤종용 Tungsten Pattern Formation Method of Semiconductor Device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122747A (en) * 1993-10-22 1995-05-12 Sony Corp Formation of gate electrode structure
KR100210853B1 (en) * 1996-08-16 1999-07-15 구본준 Conducting line of semiconductor device and method of manufacturing the same
KR19990004862A (en) * 1997-06-30 1999-01-25 김영환 Semiconductor device manufacturing method
KR19990041628A (en) * 1997-11-24 1999-06-15 구본준 Manufacturing Method of Semiconductor Device
KR19990065425A (en) * 1998-01-13 1999-08-05 윤종용 Tungsten Pattern Formation Method of Semiconductor Device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1002108530000 *

Also Published As

Publication number Publication date
KR20020002578A (en) 2002-01-10

Similar Documents

Publication Publication Date Title
US7772643B2 (en) Methods of fabricating semiconductor device having a metal gate pattern
KR940009599B1 (en) Forming method of inter-dielectric film for semiconductor device
KR100329773B1 (en) Method for fabricating fram
KR100234379B1 (en) Manufacturing method of semiconductor memory device with preventible oxidation of bit-line
KR20020041224A (en) Forming method for interlayer dielectric of semiconductor device
KR100623587B1 (en) Semiconductor device and method for manufacturing the same
KR100648859B1 (en) Method for manufacturing semiconductor device
KR100596775B1 (en) Method of manufacturing semiconductor device
KR100447256B1 (en) Method for manufacturing a semiconductor device
KR100329752B1 (en) Method for forming silicon nitride layers and method for fabricating memory device using the same
KR100620158B1 (en) Method for making contact in semiconductor device
US6541358B2 (en) Method of fabricating a semiconductor device by filling gaps between gate electrodes with HSQ
KR100332122B1 (en) Method of forming a metal wiring in a semiconductor device
KR100431741B1 (en) Method for fabrication of semiconductor device
KR100492790B1 (en) Device isolation insulating film formation method of semiconductor device
KR20080029151A (en) Method of forming an insulating layer in a semiconductor device
KR100675896B1 (en) Method for manufacturing transistor in semiconductor device using damascene process
KR100256232B1 (en) A method for forming interlayer dielectric layer in semiconductor device
KR100416814B1 (en) Method for forming interlayer dielectric of semiconductor device
KR100504550B1 (en) Method for Fabricating of Semiconductor Device
KR20010096862A (en) Self-align contact etch method of semiconductor device
KR20020002094A (en) Method for manufacturing semiconductor divice using damascene process
KR19990056330A (en) Gap Filling Method for Semiconductor Devices
KR100745905B1 (en) Method of Forming Tungsten Bit Line
KR100762879B1 (en) Method of manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100825

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee