KR20080029151A - Method of forming an insulating layer in a semiconductor device - Google Patents

Abstract

A method for forming an insulating layer of a semiconductor device is provided to improve the gap filling of an insulating layer by improving surface roughness in a gap-fill part. A structure(108) is formed on a semiconductor substrate(100). A surface pre-treatment process is performed to remove the semiconductor substrate and a part of an upper surface of the structure. An SOG layer coating process is performed to form an SOG layer by coating an SOG material to bury the pre-treated structure. A silicon oxide layer is formed by heat-treating the SOG layer. The SOG material includes an SOG solution which is formed by resolving the polisilazane in an organic solvent. The pre-treatment process includes an etch process or a plasma process using a wet-etch solution.

Description

Method of forming an insulating layer in a semiconductor device

1 to 4 are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

5 to 11 are cross-sectional views illustrating a method of forming a trench isolation layer in accordance with another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 and 200: semiconductor substrate 102: conductive film pattern

104: hard mask pattern 106: spacer

108: gate structure 110, 210: SOG film

112, 212: silicon oxide film 202: pad oxide film pattern

204: low film pattern 206: hard mask film pattern

208 trench for device isolation 214 field oxide film

The present invention relates to a method for forming an insulating film, and more particularly to a method for forming an insulating film that can easily fill the narrow gap inside.

As semiconductor devices become more integrated and faster, the formation of fine patterns is required, and not only the width of each pattern but also the space between the patterns is significantly reduced. Accordingly, it is very difficult to buried an insulating material without voids between the patterns to insulate the patterns. Therefore, the PE-CVD method which is generally used has a limitation in forming the insulating film which insulates between patterns which have a narrow space | interval. Therefore, in recent years, a process for forming an insulating film using an SOG film or a BPSG film having excellent gap fill characteristics has been developed.

A conventional method of forming an insulating film using the SOG film will be briefly described. A pattern structure is formed on a semiconductor substrate. The pattern structure may include, for example, a conductive film pattern, a hard mask pattern, and a nitride film spacer. The SOG material is coated to form spaces between the pattern structures to form an SOG film. The SOG film is formed by spin coating a SOG solution in which polysilazane is dissolved in an organic solvent. When the SOG film is heat-treated in an atmosphere containing oxygen gas or water vapor, Si-N or Si-H bonds are replaced with Si-O bonds to form a silicon oxide film. The silicon oxide film functions as an insulating film.

The silicon oxide film formed through the above process has an excellent ability to bury the spaces between the pattern structures, compared to the silicon oxide film formed by the conventional chemical vapor deposition (CVD) method.

However, the gap fill capability of the SOG film is affected by the surface roughness representing the interface state. That is, when the surface curvature is not good, the gap fill capability of the SOG film is poor. As a result, process defects occur, which causes a problem that the reliability and yield of the semiconductor device are lowered.

Accordingly, it is an object of the present invention to provide a method of forming an insulating film that can easily fill a narrow gap, thereby reducing the malfunction of the semiconductor device.

In the insulating film forming method according to an embodiment of the present invention for achieving the above object, first to form the structures on the semiconductor substrate. A surface pre-treatment process is performed to remove a portion of the upper surface of the semiconductor substrate and structures. The SOG material is coated to bury the pretreated structures to form an SOG film. The SOG film is heat-treated to form a silicon oxide film to complete the interlayer insulating film.

The SOG material may be composed of an SOG solution in which polysilaznae is dissolved in an organic solvent.

The pretreatment process may be achieved by etching or plasma treatment using a wet etchant.

The wet etching solution may be made of HF solution.

The gas used for the plasma treatment may be used alone or in combination with oxygen, nitrogen trifluoride (NF 3), nitrogen, hydrogen, argon or helium gas.

In an insulating film forming method according to another embodiment of the present invention, first, a device isolation trench is formed on a semiconductor substrate. A surface pre-treatment process is performed to remove a portion of the upper surface of the semiconductor substrate and the trench. The SOG material is coated to bury the pretreated trench inside to form an SOG film. The SOG film is heat-treated to form a silicon oxide film to complete a trench device isolation film.

The pretreatment process may be achieved by etching or plasma treatment using a wet etchant.

As described above, the surface roughness is improved by pre-treatment of the surface before the process of forming the SOG material into the silicon oxide film, thereby easily filling the narrow gap.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention. The interlayer insulating film described below is a film for insulating between gate electrodes included in the memory device.

Referring to FIG. 1, gate structures 108 are formed on a semiconductor substrate 100. The gate structure 108 may include a conductive layer pattern 102, a hard mask pattern 104, and a spacer 106.

A method of forming the gate structures 108 will be described in detail. A field oxide film (not shown) is formed on the semiconductor substrate 100 using a conventional device isolation process to activate the semiconductor substrate 100. It is divided into area and field area.

Subsequently, the semiconductor substrate 100 is thermally oxidized to grow a thin gate oxide film (not shown) having a thickness of about 20 to about 200 microseconds on the semiconductor substrate 100. A conductive film (not shown) for use as a gate electrode is formed on the gate oxide film. The conductive film is generally formed to have a thickness of about 1000 kPa by a doping process such as a diffusion process, an ion implantation process, or an in-situ doping process with a polysilicon layer doped with a high concentration of impurities. A tungsten silicide layer having a thickness of about 1500 kPa is formed on the polysilicon layer by sputtering or chemical vapor deposition (CVD) to have a polyside structure.

Subsequently, a first silicon nitride film (not shown) is formed on the conductive film at about 1800 to 2000 GPa. The first silicon nitride film is formed using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition (PECVD).

The first silicon nitride film is used as a hard mask film in a subsequent conductive film etching process. In addition, during the subsequent processes, the conductive film is protected so that the conductive film located under the first silicon nitride film is not exposed. Here, the film formed on the conductive film is not limited to the silicon nitride film, and may be a material having an etching selectivity with silicon oxide (SiO ₂ ) under specific etching process conditions.

Subsequently, after forming a photoresist film (not shown) on the first silicon nitride film, the photoresist film is selectively exposed. Subsequently, the photoresist film is formed to form a photoresist pattern (not shown) for forming a gate electrode.

Subsequently, the first silicon nitride film, the conductive film, and the gate oxide film are sequentially etched using the photoresist pattern as an etching mask, so that the gate oxide film pattern (not shown), the conductive film pattern 102 and the hard mask pattern 104 are used. This laminated structure is formed.

A second silicon nitride film (not shown) is uniformly formed on the structure and the semiconductor substrate 100. The second silicon nitride film is formed to a thickness of about 1300 kPa. Subsequently, the second silicon nitride layer is anisotropically etched such that the second silicon nitride layer remains only on the side surface of the structure to form a spacer 106.

Through the above process, the gate structure 108 including the conductive film pattern 102, the hard mask pattern 104, and the spacer 106 is completed.

Then, although not shown, ion source implantation of impurities below the substrate surface between the gate structures 108 forms a source / drain region of the transistor on the surface of the active region.

Here, the upper surfaces of the semiconductor substrate 100 and the gate structures 108 have non-uniform surface roughness due to the adsorption of residues generated after the etching process or the cleaning process.

Referring to FIG. 2, a surface pre-treatment process is performed to remove a portion of the upper surface of the semiconductor substrate 100 and the gate structures 108. The pretreatment process is achieved by etching or plasma treatment using a wet etchant.

In the etching treatment method using the wet etchant, the etchant uses HF solution, but it is preferable to use an HF solution diluted to about 200: 1. This is to prevent the gate structure 108 from being damaged by the HF solution. Thus, the diluted HF solution may remove only a portion of the non-uniform upper surface of the semiconductor substrate 100 and the gate structures 108 without damaging the gate structure 108. The etching process is accomplished by using HF solution in a bath or spin coating in-situ manner.

In addition, the gas for forming the plasma in the plasma processing method may be, for example, oxygen, nitrogen trifluoride (NF 3), nitrogen, hydrogen, argon, helium and the like. These gases can be used remote or plasma prepared by using alone or in combination.

In general, plasma treatment has anisotropy because the plasma formed hits directly on the target film, but the remote plasma applied as in the present invention isotropic because the plasma formed in a separate chamber is injected into the target reaction chamber. Will have Accordingly, the side surfaces of the gate structures 108 may be sufficiently processed.

Conventionally, residues are adsorbed on the upper surfaces of the semiconductor substrate 100 and the gate structures 108 so that the sites capable of bonding remain, so that the gap fill capability of the SOG film according to a subsequent process is lowered, thereby resulting in poor process. There is a problem that occurs.

However, such a pretreatment process may etch a non-uniform upper surface of the semiconductor substrate 100 and the gate structures 108 in a range of about 10 to about 20 microseconds to provide a site capable of bonding, and to provide surface roughness. To improve. As a result, when coating the SOG material according to a subsequent process, a dangling bond capable of bonding with the SOG material is formed on the upper surface of the semiconductor substrate 100 and the gate structures 108.

Since the dangling bond is in an unstable state in which a covalent bond is broken, there is a strong tendency to bond with other atoms in order to have a stable lowest energy level. Therefore, since the upper surfaces of the semiconductor substrate 100 and the gate structures 108 are unstable with dangling bonds, the reactivity with the SOG film in the subsequent process is improved, thereby improving the gap fill capability.

As a result, the pretreatment process increases the adhesion between the top surface of the semiconductor substrate 100 and the gate structures 108 and the SOG film, and serves to improve the bonding force at the interface.

Referring to FIG. 3, the SOG material is coated to bury the pretreated structures to form an SOG film 110. The SOG material is an SOG solution in which polysilazane is dissolved in an organic solvent. Since the SOG film 110 forms a SOG solution by a spin coating process, the gate structure 118 may be buried without voids.

In particular, as described above, the gap-filling capability of the SOG film is further improved by increasing the sites capable of bonding to the surfaces of the semiconductor substrate 100 and the gate structures 108 by the pretreatment process.

Referring to FIG. 4, the SOG film 110 is heat treated to form a silicon oxide film 112. The heat treatment process is performed by a preliminary baking process and a main baking process.

In detail, the heat treatment process is performed. First, the solvent contained in the SOG solution is removed, and a preliminary baking process is performed under a temperature range of about 50 to 450 ° C. to cure the SOG film 110. Next, a main baking process is performed to convert the SOG film 110 into the silicon oxide film 112 by performing heat treatment for about 10 to 120 minutes in an atmosphere containing oxygen gas or water vapor. The main baking process is carried out under a temperature range of about 400 to 1000 ° C.

Here, the basic skeleton of the polysilazane constituting the SOG film 110 is composed of Si-N, Si-H, and N-H bonds. Therefore, as described above, when the SOG film 110 is subjected to a main baking process in an atmosphere containing oxygen gas or water vapor, the Si-N and Si-H bonds of the SOG film 110 are replaced with Si-O bonds. The silicon oxide film 112 is formed. Since the silicon oxide film 112 has an irregular thickness, the silicon oxide film 112 may be planarized using an etch back or chemical mechanical polishing (CMP) process.

By performing the above steps, an interlayer insulating film according to an embodiment of the present invention is completed.

5 to 11 are cross-sectional views illustrating a method of forming a trench isolation layer in accordance with another embodiment of the present invention.

Referring to FIG. 5, the pad oxide film 201 is formed on the semiconductor substrate 200 to have a thickness of about 50 to about 200 kPa by a thermal oxidation process. The pad oxide film 201 is formed to relieve stress generated when depositing a subsequent stop film. A silicon nitride (SiN) is deposited on the pad oxide film 201 by a low pressure chemical vapor deposition (LPCVD) method to a thickness of about 100 to 3000 m 3 to form a stop layer 203. The blocking film 203 serves as a polishing finish film in a subsequent chemical mechanical polishing (CMP) process.

Subsequently, a high temperature oxide film (HTO) is deposited on the blocking film 203 by a low pressure chemical vapor deposition (LPCVD) method to form a hard mask film 205. Silicon oxynitride (SiON) is deposited on the hard mask layer 205 by a low pressure chemical vapor deposition (LPCVE) method to a thickness of about 200 to 1000 Å, thereby forming an antireflection film (not shown). The anti-reflection film serves to prevent reflection of light from the lower substrate during the subsequent photolithography process and facilitates formation of a photoresist pattern. This anti-reflection film is formed of a silicon oxynitride film (SiON), an organic film, or the like, and is removed during the subsequent trench formation process.

 Referring to FIG. 6, a photoresist composition is coated on the hard mask film 205 by a spin coating process to form a photoresist film (not shown). Subsequently, the photoresist film is exposed using a photo mask to form a photoresist pattern (not shown) defining an active region.

The hard mask film pattern 206 and the stop film pattern 204 are sequentially dry-etched by using the photoresist pattern as an etching mask and sequentially etching the hard mask film 205, the stop film 203, and the pad oxide film 201. And a pad oxide film pattern 202. Subsequently, the photoresist pattern is removed through an ashing and stripping process.

Referring to FIG. 7, an upper portion of the substrate 200 adjacent to the blocking layer pattern 204 is etched using the hard mask layer pattern 206 as an etching mask to form a device isolation trench 208.

Here, the upper surface of the device isolation trench 208 has a non-uniform surface roughness due to the adsorption of residues generated after the etching process or the cleaning process.

Referring to FIG. 8, a surface pre-treatment process is performed to remove a portion of the upper surface of the semiconductor substrate 200 and the trench 208. The pretreatment process is achieved by etching or plasma treatment using a wet etchant. Here, since the pretreatment process is the same as described in FIG. 2 of the embodiment, further description thereof will be omitted.

By using the pretreatment process, a non-uniform upper surface inside the semiconductor substrate 200 and the trench 208 may be etched in a range of about 10 to about 20 microseconds to provide a bondable site and to improve surface roughness. do. As a result, when coating the SOG material according to a subsequent process, dangling bonds are formed on the upper surfaces of the semiconductor substrate 200 and the trench 208 to react with the SOG material.

Referring to FIG. 9, the SOG material is coated to form an SOG film 210 so as to bury the inside of the pretreated trench 208.

If the SOG film is formed by spin coating the SOG material after the pretreatment, the gap-filling ability of the SOG film is further improved by increasing sites capable of bonding to upper surfaces of the semiconductor substrate 200 and the trench 208. do.

Referring to FIG. 10, the SOG film 210 is heat treated to form a silicon oxide film 212. Since the silicon oxide film has an irregular thickness, it can be planarized using an etch back or chemical mechanical polishing (CMP) process.

Referring to FIG. 11, a field oxide layer 214 is formed in the trench 208 by removing the blocking layer pattern 204 through a phosphate strip process.

By performing the above processes, a trench device isolation film according to an embodiment of the present invention is completed.

According to the present invention as described above, by improving the surface roughness (roughness) of the portion to be gap fill, it is possible to improve the gap fill capability of the insulating film. For this reason, the reliability improvement and the yield improvement of a semiconductor device can be anticipated.

In addition, by applying the insulating film forming method to the interlayer insulating film forming step or the trench element isolation film forming step, a semiconductor device having high reliability can be manufactured.

As described above, the present invention has been described with reference to the preferred embodiments of the present invention, but a person of ordinary skill in the art does not depart from the spirit and scope of the present invention as set forth in the claims below. It will be understood that various modifications and changes can be made.

Claims (7)

Forming structures on a semiconductor substrate; Performing a surface pre-treatment process to remove a portion of the upper surface of the semiconductor substrate and structures; Coating an SOG material to bury the pretreated structures to form an SOG film; And And heat-treating the SOG film to form a silicon oxide film. The method of claim 1, wherein the SOG material comprises an SOG solution in which polysilaznae is dissolved in an organic solvent. The method of claim 1, wherein the pretreatment step includes an etching process or a plasma process using a wet etching solution. The method of claim 3, wherein the wet etching solution is an HF solution. The insulating film of a semiconductor device according to claim 3, wherein the gas used for the plasma treatment is at least one selected from the group consisting of oxygen, nitrogen trifluoride (NF3), nitrogen, hydrogen, argon or helium gas. Forming method. Forming a trench for device isolation on the semiconductor substrate; Performing a surface pre-treatment process to remove a portion of the upper surface inside the semiconductor substrate and the trench; Coating an SOG material to bury the pre-treated trench to form an SOG film; And And heat-treating the SOG film to form a silicon oxide film. The method of claim 6, wherein the pretreatment step includes an etching process or a plasma process using a wet etching solution.

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