KR0171953B1 - Layer insulation film forming method of semiconductor device - Google Patents

Layer insulation film forming method of semiconductor device Download PDF

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Publication number
KR0171953B1
KR0171953B1 KR1019950066049A KR19950066049A KR0171953B1 KR 0171953 B1 KR0171953 B1 KR 0171953B1 KR 1019950066049 A KR1019950066049 A KR 1019950066049A KR 19950066049 A KR19950066049 A KR 19950066049A KR 0171953 B1 KR0171953 B1 KR 0171953B1
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South Korea
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semiconductor device
film
forming
teos usg
conductive wiring
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KR1019950066049A
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Korean (ko)
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KR970052864A (en
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박창서
이승무
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

본 발명은 반도체 소자의 중간 절연막 형성 방법에 관한 것으로, 공지의 기술로 반도체 기판 상부에 도전 배선을 형성하고, 상기 도전 배선 상부에 형성된 자연 산화막을 제거하기 위한 제1세정공정을 실시한 다음, 전체 표면상부에 묽은 수용액을 이용한 제2세정공정을 실시하고, 전체표면상부에 O3-TEOS USG 막을 소정두께 형성하여 평탄화시키는 공정으로 표면상부가 평탄화되고 갭필 특성이 향상된 층간 절연막을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an intermediate insulating film of a semiconductor device. The method includes forming a conductive wiring on a semiconductor substrate by a known technique, and performing a first cleaning process for removing a natural oxide film formed on the conductive wiring. A second cleaning process using a thin aqueous solution is performed on the upper part, and a flattening process is performed by forming a predetermined thickness of O 3 -TEOS USG film on the entire surface to form an interlayer insulating film having a flat upper surface and improved gap fill characteristics. And it is a technology to improve the reliability and thereby high integration of the semiconductor device.

Description

반도체소자의 층간절연막 형성방법Method of forming interlayer insulating film of semiconductor device

제1(a)도 내지 제1(d)도는 종래기술에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도.1 (a) to 1 (d) are cross-sectional views showing a method for forming an interlayer insulating film of a semiconductor device according to the prior art.

제2(a)도 및 제2(b)도는 본 발명의 실시예에 따른 반도체소자의 층간절연막 형성방법을 도시한 단면도.2 (a) and 2 (b) are cross-sectional views showing a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체 기판 13 : 절연막11 semiconductor substrate 13 insulating film

15 : 도전배선 17 : 패시베이션된 층15: conductive wiring 17: passivated layer

19 : 산화막 21 : 전하발생층19: oxide film 21: charge generating layer

23,25 : O3-TEOS USG막23,25: O 3 -TEOS USG film

본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, 특히 전극 간의 절연막으로 사용되는 오존-테오스 유.에스.지. (O3-TEOS USG : O3-TetraEthyOrthoSilicate UndopedSilicateGlass, 이하에서 O3-TEOS USG 라 함)의 증착 시증 착막의 균일도 개선을 통하여 평탄화 특성을 개선 시키기 위하여 증착 전에 세정하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device. (O 3 -TEOS USG: O 3 -TetraEthyOrthoSilicate UndopedSilicateGlass, hereinafter referred to as O 3 -TEOS USG) relates to a method of cleaning before deposition to improve the planarization characteristics through the uniformity improvement of the deposition film.

일반적으로, O3-TEOS USG는 우수한 갭필(gap fill) 특성과 자체 평탄화 특성을 가지고 있기 때문에 금속배선간 절연막, 폴리실리콘 배선간 절연막, 트렌치 소자분리막 공정 등에 적용이 가능하다.In general, since O 3 -TEOS USG has excellent gap fill characteristics and self-planarization characteristics, the O 3 -TEOS USG can be applied to an intermetal interconnection film, a polysilicon interconnection insulation film, and a trench isolation layer process.

그리고, 상기 O3-TEOS USG 는 하부층의 상태에 따라 증착이 불균일한 특성이 있다. 지금까지는 이러한 특성을 제거하기 위하여 플라즈마 처리방법이 이용되었다.In addition, the O 3 -TEOS USG has a non-uniform deposition property depending on the state of the lower layer. Until now, a plasma treatment method has been used to remove these characteristics.

그러나, 상기 플라즈마 처리는 처리 중 박막의 표면에 불 균일한 전하 발생 층이 형성될 수 있으며, O3-TEOS USG 의 자체 평탄화 특성을 악화 시키는 문제점을 갖고 있다.However, in the plasma treatment, a non-uniform charge generating layer may be formed on the surface of the thin film during the treatment, and has a problem of deteriorating the self-planarization characteristics of O 3 -TEOS USG.

또한, 상기의 불균일한 증착 특성을 제거하기 위한 다른 방안으로 과잉 실리콘 산화막을 증착하기도 하는데, 이 경우는 플라즈마 산화막인 과잉 실리콘 USG 의 단차피복성이 좋지 않기 때문에 갭(gap)의 윗부분에 과도한 증착이 이루어지는 오버행(over hang) 현상이 발생하여 O3-TEOS USG 가 후속으로 증착될 때 갭필 특성을 악화시키는 문제점이 있다.In addition, another method for removing the non-uniform deposition characteristics may be to deposit an excess silicon oxide film. In this case, the excessive deposition on the gap is not necessary because the step coverage of the excess silicon USG, which is a plasma oxide film, is not good. There is a problem that deterioration of the gapfill characteristics when O 3 -TEOS USG is subsequently deposited due to the over hang phenomenon occurs.

제1(a)도 내지 제1(d)도는 본 발명의 실시예에 따른 반도체 소자의 층간 절연막 형성방법을 도시한 단면도이다.1 (a) to 1 (d) are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

제1(a)도를 참조하면, 반도체기판(11) 상부에 절연막(13)과 도전체(15)을 증착한 후 패터닝 공정으로 도전배선(15)을 형성한다.Referring to FIG. 1A, an insulating layer 13 and a conductor 15 are deposited on the semiconductor substrate 11, and then the conductive wiring 15 is formed by a patterning process.

이 때, 상기 도전체(15)는 도프된 다결정실리콘막이나 알루미늄박막으로 형성된 것이다.At this time, the conductor 15 is formed of a doped polysilicon film or an aluminum thin film.

후속공정으로 다른 도전배선과의 브릿지(bridge) 현상을 방지하기 위하여 층간절연막을 증착하게 되는데 이 때, 상기 층간절연막은 도전배선(15)간의 브릿지를 막는 목적뿐만아니라, 후속공정시 패터닝을 용이하도록 하기 위하여 요철부분을 잘 메꿔주어야 하는 평탄화 특성을 가져야 한다. 이러한 목적에 잘 부합되는 O3-TEOS USG 막은 도전배선의 요철부분을 잘 메꿔주는 갭필 특성과 자체 평탄화 특성을 갖고 있어 금속배선간 절연, 다결정 실리콘막 배선간 절연 및 트랜치 소자분리 절연 공정에 적용되고 있다. 그러나, 상기 O3-TEOS USG 는 증착이 진행될 하부층의 표면 상태에 따라 증착이 불균일한 단점이 있다.In the subsequent process, an interlayer insulating film is deposited to prevent a bridge phenomenon from another conductive wiring. In this case, the interlayer insulating film is not only for preventing the bridge between the conductive wirings 15 but also for easy patterning in a subsequent process. In order to have a flattening property to fill the uneven portion well. O 3 -TEOS USG film, which is well suited for this purpose, has gap fill characteristics and self-planarization characteristics to fill the uneven portion of the conductive wiring, and is applied to insulation between metal wirings, insulation between polycrystalline silicon films, and trench isolation. have. However, the O 3 -TEOS USG has a disadvantage in that deposition is not uniform depending on the surface state of the lower layer to be deposited.

그래서, 도전배선의 패터닝 후 O3-TEOS USG 막의 전공정으로 도전배선의 자연산화막을 제거하기 위하여 산화막 식각 화학물질을 이용하여 플라즈마 처리를 진행하거나, 도전배선 위에 O3-TEOS USG 막의 증착 균일도를 좋게 하기 위하여 산화막을 소정두께 증착 한 후 플라즈마 처리를 진행한다.Thus, after the patterning of the conductive wiring layer O 3 -TEOS USG pre-process the O 3 -TEOS USG film deposition uniformity on the progress to a plasma treatment using an oxide etch chemistry, or a conductive wire to remove a natural oxide film of the conductive wire into a In order to improve the quality, an oxide film is deposited to a predetermined thickness, and then plasma treatment is performed.

제1(b)도를 참조하면, 상기 제1(a)도의 공정 후에 자연산화막을 제거하기 위하여 산화막 식각 화학물질을 이용하여 플라즈마 처리를 진행함으로써 상기 식각 화학물질 중에서 불소계나 염소계 이온들과 같이 (-) 전하를 갖는 이온들로 도전배선(15) 표면에 패시베이션(passivation) 된 층(17)이 형성된다.Referring to FIG. 1 (b), after the process of FIG. 1 (a), plasma treatment is performed using an oxide etching chemical to remove the natural oxide film, and thus, as in the etching chemicals, fluorine or chlorine ions may be The passivated layer 17 is formed on the surface of the conductive wiring 15 with ions having a charge.

제1(c)도를 참조하면, 도전배선 상부에 O3-TEOS USG 막의 증착 균일도를 좋게 하기 위하여 산화막(19)을 500Å 정도 증착한 후 플라즈마 처리를 진행한다. 이 때, 상기 산화막(19)의 표면으로부터 20 내지 30Å 정도의 두께로 전하가 밀집하는 전하발생층(chage-build-up-layer)(21)이 형성된다.Referring to FIG. 1 (c), in order to improve the uniformity of deposition of the O 3 -TEOS USG film on the conductive wiring, the oxide film 19 is deposited about 500 mW, and then plasma treatment is performed. At this time, a charge-build-up-layer 21 is formed in which charges are dense to a thickness of about 20 to 30 kHz from the surface of the oxide film 19.

제1(d)도를 참조하면, 상기 제1(b)도 또는 제1(c)도의 공정 후에 O3-TEOS USG 막(23)을 소정두께 증착한다.Referring to FIG. 1 (d), an O 3 -TEOS USG film 23 is deposited to a predetermined thickness after the process of FIG. 1 (b) or FIG. 1 (c).

이 때, 상기 O3-TEOS USG 막(23) 증착은 상기 O3-TEOS USG 막(23) 자체가 플라즈마 조건에서 증착 화학적 이온 가스를 이용하기 때문에 균일도가 좋지 못하며, 오버행과 같은 현상으로 인하여 갭필특성이 저하된다.At this time, the O 3 -TEOS USG film 23 deposition is not good uniformity because the O 3 -TEOS USG film 23 itself uses the deposition chemical ion gas in the plasma conditions, gap fill due to the phenomenon such as overhang Properties are degraded.

이상에서 설명한 바와같이 종래기술은 상부구조를 평탄화시키지 못하고, 오버행과 같은 현상으로 갭필 특성이 저하되어 반도체소자의 특성 및 신뢰성이 저하되고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, the prior art does not planarize the upper structure, and the gap fill characteristic is deteriorated due to a phenomenon such as an overhang, thereby deteriorating the characteristics and reliability of the semiconductor device, thereby making it difficult to integrate the semiconductor device.

따라서, 본 발명은 상기한 문제점을 해결하기 위하여, 층간절연막으로 사용되는 O3-TEOS USG 막을 형성전 표면을 세정하여 갭필특성과 평탄화특성이 향상된 층간 절연막을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키고, 그에 따른 반도체 소자의 고집적화를 가능하게 하는 반도체소자의 층간 절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention improves the characteristics and reliability of semiconductor devices by forming an interlayer insulating film having improved gap fill and planarization properties by cleaning the surface before forming the O 3 -TEOS USG film used as the interlayer insulating film. It is an object of the present invention to provide a method for forming an interlayer insulating film of a semiconductor device that enables high integration of the semiconductor device.

이상의 목적을 달성하기 위하여 본 발명에 따른 반도체 소자의 층간절연막 형성방법의 특징은, 공지의 기술로 반도체기판 상부에 도전배선을 형성하는 공정과, 상기 도전배선 상부에 형성된 자연산화막을 제거하기 위한 제1세정공정을 실시하는 공정과, 전체 표면상부에 묽은 수용액을 이용한 제2세정공정을 실시하는 공정과, 전체표면 상부에 O3-TEOS USG 막을 소정두께 형성하여 평탄화시키는 공정을 포함하는 것이다.In order to achieve the above object, a feature of the method for forming an interlayer insulating film of a semiconductor device according to the present invention is a method for forming a conductive wiring on a semiconductor substrate by a known technique, and a method for removing a natural oxide film formed on the conductive wiring. And a step of carrying out a first washing step, a step of carrying out a second washing step using a dilute aqueous solution on the entire surface, and a step of forming a planarized thickness of an O 3 -TEOS USG film on the entire surface.

이상의 목적을 달성하기 위한 본 발명의 원리는, O3-TEOS USG 막의 증착이 진행될 하부층 표면 상태를 습식 또는 건식 세정공정으로 현화시킴으로써 O3-TEOS USG 막의 증착공정을 안정화시키는 것이다.The principles of the present invention for achieving the above objectives, O 3 -TEOS USG layer deposited is to the lower layer take place a surface state stabilized the O 3 -TEOS USG film deposition process by flowering by a wet or dry cleaning process.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2(a)도 및 제2(b)도는 본 발명의 실시예에 따른 반도체 소자의 층간절연막 형성방법을 도시한 단면도이다.2 (a) and 2 (b) are cross-sectional views showing a method for forming an interlayer insulating film of a semiconductor device according to an embodiment of the present invention.

제2(a)도를 참조하면, 종래기술에서 기술한 제1(b), 제1(c)도의 공정 후 HF : H2O를 1:200 내지 1:500의 비율로 희석시킨 묽은 HF 수용액으로 세정공정을 실시한 것을 도시한 단면도로서, 상기 제1(c)도의 공정 후의 진행상황을 도시한 것이다.Referring to FIG. 2 (a), a dilute HF aqueous solution in which HF: H 2 O is diluted in a ratio of 1: 200 to 1: 500 after the processes of FIGS. 1 (b) and 1 (c) described in the prior art. The cross sectional view showing that the cleaning step is performed shows the progress after the step shown in FIG. 1 (c).

이 때, HF : H2O의 비율이 1:200 이상인 묽은 HF 수용액은 열산화막을 기준으로 할 때, 식각률이 0.25 Å/sec 미만으로 낮은 식각률을 보인다.At this time, the dilute HF aqueous solution having a ratio of HF: H 2 O of 1: 200 or more shows a low etching rate with an etching rate of less than 0.25 mW / sec based on the thermal oxide film.

그리고, O3-TEOS USG 막의 경우 0.5Å/sec 미만의 식각률을 가지며, 20 내지 30Å 두께의 전하발생층은 60 내지 100초 정도 상기 수용액에 담구어 두면 충분히 제거할 수 있다.In addition, the O 3 -TEOS USG film has an etching rate of less than 0.5 μs / sec, and the charge generation layer having a thickness of 20 to 30 μs may be sufficiently removed by immersing in the aqueous solution for about 60 to 100 seconds.

이로 인하여, 전체 표면에 형성된 (-) 전하를 제거할 수 있어 O3-TEOS USG 막의 증착 특성을 높일 수 있다.As a result, the negative charges formed on the entire surface can be removed, thereby improving the deposition characteristics of the O 3 -TEOS USG film.

여기서, 점선은 전하발생층(21)이 제거된 것을 도시한 것이다.Here, the dotted lines show that the charge generation layer 21 has been removed.

제2(b)도를 참조하면, 전체표면상부에 O3-TEOS USG 막(25)을 소정두께 형성함으로써 표면상부를 평탄화시킨 것을 도시한 단면도로서, 갭필특성이 향상된 것이다.Referring to FIG. 2 (b), a cross-sectional view showing the planarization of the upper surface by forming a predetermined thickness of the O 3 -TEOS USG film 25 on the entire surface, whereby the gap fill characteristic is improved.

이상에서 설명한 바와같이 본 발명에 따른 반도체 소자의 층간절연막 형성방법은, 종래의 플라즈마 처리로부터 발생되는 음이온계의 전하발생 및 산화막 내의 전하발생층을 묽은 HF 수용액으로 제거하여 O3-TEOS USG 막의 갭필 특성을 향상시키고, 표면상부를 평탄화시킴으로써 후속공정을 용이하게 실시 할 수 있어 반도체 소자의 특성 및 신뢰성을 향상시키고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, in the method for forming an interlayer insulating film of a semiconductor device according to the present invention, the gap fill of the O 3 -TEOS USG film is obtained by removing the anion-based charge generation and the charge generation layer in the oxide film generated by the conventional plasma treatment with dilute HF solution. The subsequent steps can be easily carried out by improving the characteristics and flattening the upper surface, thereby improving the characteristics and reliability of the semiconductor device, thereby enabling high integration of the semiconductor device.

Claims (3)

공지의 기술로 반도체기판 상부에 도전배선을 형성하는 공정과, 상기 도전배선 상부에 형성된 자연산화막을 제거하기 위한 제1세정공정을 실시하는 공정과, 전체표면상부에 묽은 수용액을 이용한 제2세정공정을 실시하는 공정과, 전체 표면상부에 O3-TEOS USG 막을 소정두께 형성하여 평탄화 시키는 공정을 포함하는 반도체 소자의 층간 절연막 형성방법.A process of forming a conductive wiring on the upper surface of the semiconductor substrate by a known technique, a first cleaning process for removing a natural oxide film formed on the conductive wiring, and a second cleaning process using a dilute aqueous solution on the entire surface. And forming a planarized thickness of an O 3 -TEOS USG film over the entire surface of the semiconductor device. 제1항에 있어서, 상기 묽은 수용액은 HF : H2O의 비율이 1 : 200 내지 1 : 500인 것을 특징으로 하는 반도체 소자의 층간절연막 형성방법.The method of claim 1, wherein the dilute aqueous solution has a ratio of HF: H 2 O of 1: 200 to 1: 500. 제1항에 있어서, 상기 제2세정공정은 60 내지 100초간 실시되는 것을 특징으로 하는 반도체소자의 층간 절연막 형성방법.The method of claim 1, wherein the second cleaning process is performed for 60 to 100 seconds.
KR1019950066049A 1995-12-29 1995-12-29 Layer insulation film forming method of semiconductor device KR0171953B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468687B1 (en) * 1997-09-08 2005-03-16 삼성전자주식회사 Manufacturing method of inter dielectric layer for semiconductor device
KR100558043B1 (en) * 1998-12-31 2006-05-03 매그나칩 반도체 유한회사 Copper metal wiring formation method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468687B1 (en) * 1997-09-08 2005-03-16 삼성전자주식회사 Manufacturing method of inter dielectric layer for semiconductor device
KR100558043B1 (en) * 1998-12-31 2006-05-03 매그나칩 반도체 유한회사 Copper metal wiring formation method of semiconductor device

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