KR100745905B1 - Method of Forming Tungsten Bit Line - Google Patents

Method of Forming Tungsten Bit Line Download PDF

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KR100745905B1
KR100745905B1 KR1020010039113A KR20010039113A KR100745905B1 KR 100745905 B1 KR100745905 B1 KR 100745905B1 KR 1020010039113 A KR1020010039113 A KR 1020010039113A KR 20010039113 A KR20010039113 A KR 20010039113A KR 100745905 B1 KR100745905 B1 KR 100745905B1
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forming
film
bit line
barrier metal
tungsten
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KR1020010039113A
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Korean (ko)
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KR20030003376A (en
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정성희
류창우
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 텅스텐을 이용한 비트라인의 형성 방법에 관한 것으로서, 소오스/드레인 영역 형성 후 도핑되지 않은 ESD ( elevated source/drain ) 막을 형성하고 비트 라인 공정을 진행함으로써 도펀트 손실을 감소시키고 콘택트의 저항을 개선시키는 텅스텐 비트 라인 형성 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line using tungsten of a semiconductor device, wherein an undoped ESD source is formed after a source / drain region is formed and a bit line process is performed to reduce dopant loss and A method of forming a tungsten bit line that improves the resistance is provided.

텅스텐, 비트 라인, ＥＳＤ막, 도펀트 손실Tungsten, Bit Line, ESD Film, Dopant Loss

Description

텅스텐 비트 라인 형성 방법{Method of Forming Tungsten Bit Line}Method of Forming Tungsten Bit Line

도 1a 내지 도 1f는 본 발명에 따른 텅스텐 비트 라인 형성 방법에 의한 반도체 소자의 제조 공정을 설명하기 위한 단면도들.1A to 1F are cross-sectional views illustrating a manufacturing process of a semiconductor device by a tungsten bit line forming method according to the present invention.

본 발명은 반도체 소자의 비트 라인 제조 방법에 관한 것으로, 특히 텅스텐을 이용한 비트라인의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a bit line of a semiconductor device, and more particularly to a method for forming a bit line using tungsten.

종래에는 W6/폴리실리콘을 이용하여 비트 라인을 제조하였으나, 최근에는 비트 라인의 저항값을 감소시키기 위해 W/TiN/Ti를 이용하여 비트 라인을 제조하는데 비트 라인의 안정적인 저항 확보를 위하여 배리어 금속층 어닐링 공정을 수행하여 TiSi2층을 형성한다. 그런데 배리어 금속층 어닐링 공정은 정션의 도펀트의 손실을 발생시켜 콘택트의 저항을 증가시킨다는 문제점이 있었다. 특히 p+ 정션에서 Ti와 B와의 높은 반응성에 의해 TiSi2/p+ Si의 경계면에서 도펀트의 공핍을 발생시켜 n+ 보다 높은 콘택트 저항을 가지게 되어 PMOS의 특성을 열화시킨다는 문제점이 있었다.Conventionally, a bit line is manufactured using W 6 / polysilicon, but recently, a bit metal is manufactured by using W / TiN / Ti to reduce the resistance of the bit line, and a barrier metal layer is used to secure stable resistance of the bit line. The annealing process is performed to form a TiSi 2 layer. However, the barrier metal layer annealing process has a problem of increasing the contact resistance by generating a loss of dopant in the junction. In particular, due to the high reactivity between Ti and B in the p + junction, dopant depletion occurs at the interface of TiSi 2 / p + Si, resulting in a higher contact resistance than n +, thereby degrading the characteristics of the PMOS.

본 발명은 이러한 문제를 해결하기 위해 소오스/드레인 영역 형성 후 도핑되지 않은 ESD ( elevated source/drain )막을 형성하고 비트 라인 공정을 진행함으로써 도펀트 손실을 감소시키고 콘택트의 저항을 개선시키는 텅스텐 비트 라인 형성 방법을 제공하는데 그 목적이 있다.In order to solve this problem, the present invention provides a method of forming a tungsten bit line to reduce dopant loss and improve contact resistance by forming an undoped elevated source / drain (ESD) layer after forming a source / drain region and performing a bit line process. The purpose is to provide.

본 발명에 따른 텅스텐 비트 라인 형성 방법은 반도체 기판 상에 게이트 산화막, 폴리실리콘막, 텅스텐 질화막, 텅스텐막 및 마스크 절연막 패턴이 적층된 게이트 전극을 형성하는 단계;
상기 게이트 전극의 측벽에 절연막 스페이서를 형성하는 단계;
상기 게이트 전극의 양측의 반도체 기판에 소오스/드레인 영역을 형성하는 단계;
상기 소오스/드레인 영역의 반도체기판 상부에 도핑되지 않은 ESD ( elevated source/drain )막을 형성하는 단계;
상기 반도체기판 상부에 상기 ESD막을 노출시키는 비트라인 콘택홀이 형성된 층간절연막을 형성하는 단계;
상기 비트라인 콘택홀을 포함하는 반도체기판 전면에 제1 및 제2 배리어 금속층을 형성하는 단계;
RTP 어닐링을 수행하는 단계;
상기 반도체 기판의 전면에 제3 배리어 금속층을 일정한 두께로 형성하는 단계; 및
상기 비트라인 콘택홀을 매립하는 텅스텐막을 형성하는 단계
를 포함하는 것을 특징으로 한다.A tungsten bit line forming method according to the present invention includes forming a gate electrode on which a gate oxide film, a polysilicon film, a tungsten nitride film, a tungsten film, and a mask insulating film pattern are stacked on a semiconductor substrate;
Forming an insulating film spacer on sidewalls of the gate electrode;
Forming source / drain regions on semiconductor substrates on both sides of the gate electrode;
Forming an undoped elevated source / drain (ESD) film on the semiconductor substrate in the source / drain region;
Forming an interlayer insulating film having a bit line contact hole exposing the ESD film on the semiconductor substrate;
Forming first and second barrier metal layers on an entire surface of the semiconductor substrate including the bit line contact holes;
Performing RTP annealing;
Forming a third barrier metal layer on a front surface of the semiconductor substrate to a predetermined thickness; And
Forming a tungsten film to fill the bit line contact hole
Characterized in that it comprises a.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.                     

도 1a 내지 도 1f는 본 발명에 따른 텅스텐 비트 라인 형성 방법에 의한 반도체 소자의 제조 공정을 설명하기 위한 단면도들이다.
도 1a 내지 도 1f를 참조하면, 반도체 기판(10) 상에 게이트 산화막(20)을 형성하고 게이트 산화막(20) 상부에 폴리실리콘막(30), 텅스텐 질화막(40), 텅스텐막(50)의 적층 구조로 된 게이트 전극을 형성한 후 텅스텐막(50)의 상부에 마스크 절연막 패턴(60)을 적층하여 게이트 전극을 형성한다. 그 다음에 상기 게이트 전극의 측벽에 절연막 스페이서(70)를 형성하고 상기 게이트 전극의 양측의 반도체 기판에 소오스/드레인 영역(80)을 형성한다(도 1a 참조).
다음에는 도핑되지 않은 ESD ( elevated source/drain )막(90)을 소오스/드레인 영역(80) 상부에 형성한다. 도핑되지 않은 ESD막(90)은 SiH4 및 SiH2Cl2 가스를 이용하여 700 내지 1000℃의 온도 및 760Torr 이하의 압력에서 형성하는 것이 바람직하다.(도 1b 참조)
반도체 기판(10)의 전면에 층간 절연막(100)을 형성한 후 ESD막(90)의 상부에 위치한 층간 절연막(100)의 일부를 식각하여 ESD막(90)을 노출시키는 비트라인 콘택홀(110)을 형성한다(도 1c 참조).
다음에는 반도체 기판(10)의 전면에 제1 배리어 금속층(120) 및 제2 배리어 금속층(125)을 형성한다(도 1d 참조). 여기서 제1 배리어 금속층(120)은 Ti막인 것이 바람직하며, 제2 배리어 금속층(125)은 TiN막인 것이 바람직하다. 또한 제1 배리어 금속층(120) 및 제2 배리어 금속층(125)은 Ar 스퍼터링을 이용하여 400℃ 이하의 온도 및 10Torr 이하의 압력에서 형성하는 것이 바람직하다.
다음에는 RTP 어닐링을 수행하여 ESD막(90)의 상부에 TiSi2막(130)을 형성한다(도 1e 참조). RTP 어닐링은 바람직하게는 700 내지 1000℃의 온도에서 수행한다. RTP 어닐링을 수행하면 제1 배리어 금속층(120)과 ESD막(90)이 반응하여 실리사이드가 형성된다.
그 다음에 반도체 기판(10)의 전면에 제3 배리어 금속층(140)을 형성한 후 텅스텐막(150)을 형성한다(도 1f 참조). 제3 배리어 금속층(140)은 TiN막인 것이 바람직하다.1A to 1F are cross-sectional views illustrating a manufacturing process of a semiconductor device by a tungsten bit line forming method according to the present invention.
1A to 1F, the gate oxide film 20 is formed on the semiconductor substrate 10, and the polysilicon film 30, the tungsten nitride film 40, and the tungsten film 50 are formed on the gate oxide film 20. After forming a gate electrode having a stacked structure, a mask insulating film pattern 60 is stacked on the tungsten film 50 to form a gate electrode. Next, an insulating film spacer 70 is formed on sidewalls of the gate electrode, and source / drain regions 80 are formed on semiconductor substrates on both sides of the gate electrode (see FIG. 1A).
An undoped elevated source / drain (ESD) film 90 is then formed over the source / drain regions 80. The undoped ESD film 90 is preferably formed using SiH 4 and SiH 2 Cl 2 gas at a temperature of 700 to 1000 ° C. and a pressure of 760 Torr or less (see FIG. 1B).
The bit line contact hole 110 exposing the ESD layer 90 by etching the portion of the interlayer insulating layer 100 disposed on the ESD layer 90 after forming the interlayer insulating layer 100 on the entire surface of the semiconductor substrate 10. ) (See FIG. 1C).
Next, the first barrier metal layer 120 and the second barrier metal layer 125 are formed on the entire surface of the semiconductor substrate 10 (see FIG. 1D). The first barrier metal layer 120 is preferably a Ti film, and the second barrier metal layer 125 is preferably a TiN film. In addition, the first barrier metal layer 120 and the second barrier metal layer 125 may be formed at a temperature of 400 ° C. or less and a pressure of 10 Torr or less using Ar sputtering.
Next, RTP annealing is performed to form a TiSi 2 film 130 on top of the ESD film 90 (see FIG. 1E). RTP annealing is preferably carried out at a temperature of 700 to 1000 ° C. When the RTP annealing is performed, the first barrier metal layer 120 and the ESD film 90 react to form silicide.
Thereafter, the third barrier metal layer 140 is formed on the entire surface of the semiconductor substrate 10, and then a tungsten film 150 is formed (see FIG. 1F). The third barrier metal layer 140 is preferably a TiN film.

상기 설명한 바와 같이, 본 발명에 따른 텅스텐 비트 라인 형성 방법은 소오스/드레인 영역 형성 후 도핑되지 않은 ESD막을 형성하고 비트 라인 공정을 진행함으로써 도펀트 손실을 감소시키고 콘택트의 저항을 개선시키는 효과가 있다.As described above, the tungsten bit line forming method according to the present invention has an effect of reducing the dopant loss and improving the contact resistance by forming an undoped ESD film after the source / drain region formation and performing the bit line process.

Claims (7)

반도체 기판 상에 게이트 산화막, 폴리실리콘막, 텅스텐 질화막, 텅스텐막 및 마스크 절연막 패턴이 적층된 게이트 전극을 형성하는 단계;Forming a gate electrode on which a gate oxide film, a polysilicon film, a tungsten nitride film, a tungsten film, and a mask insulating film pattern are stacked on a semiconductor substrate; 상기 게이트 전극의 측벽에 절연막 스페이서를 형성하는 단계;Forming an insulating film spacer on sidewalls of the gate electrode; 상기 게이트 전극의 양측의 반도체 기판에 소오스/드레인 영역을 형성하는 단계;Forming source / drain regions on semiconductor substrates on both sides of the gate electrode; 상기 소오스/드레인 영역의 반도체기판 상부에 도핑되지 않은 ESD ( elevated source/drain )막을 형성하는 단계;Forming an undoped elevated source / drain (ESD) film on the semiconductor substrate in the source / drain region; 상기 반도체기판 상부에 상기 ESD막을 노출시키는 비트라인 콘택홀이 형성된 층간절연막을 형성하는 단계;Forming an interlayer insulating film having a bit line contact hole exposing the ESD film on the semiconductor substrate; 상기 비트라인 콘택홀을 포함하는 반도체기판 전면에 제1 및 제2 배리어 금속층을 형성하는 단계;Forming first and second barrier metal layers on an entire surface of the semiconductor substrate including the bit line contact holes; RTP 어닐링을 수행하는 단계;Performing RTP annealing; 상기 반도체 기판의 전면에 제3 배리어 금속층을 일정한 두께로 형성하는 단계; 및Forming a third barrier metal layer on a front surface of the semiconductor substrate to a predetermined thickness; And 상기 비트라인 콘택홀을 매립하는 텅스텐막을 형성하는 단계Forming a tungsten film to fill the bit line contact hole 를 포함하는 것을 특징으로 하는 텅스텐 비트 라인 형성 방법.Tungsten bit line forming method comprising a. 제 1 항에 있어서,The method of claim 1, 상기 도핑되지 않은 ESD막을 형성하는 단계는 SiH4 및 SiH2Cl2 가스를 이용하여 700 내지 1000℃의 온도 및 760Torr 이하의 압력에서 수행되는 것을 특징으로 하는 텅스텐 비트 라인 형성 방법.Forming the undoped ESD film using a SiH 4 and SiH 2 Cl 2 gas at a temperature of 700 to 1000 ° C. and a pressure of 760 Torr or less. 제 1 항에 있어서,The method of claim 1, 상기 제1 배리어 금속층은 Ti막인 것을 특징으로 하는 텅스텐 비트 라인 형성 방법.And the first barrier metal layer is a Ti film. 제 1 항에 있어서,The method of claim 1, 상기 제2 배리어 금속층은 TiN막인 것을 특징으로 하는 텅스텐 비트 라인 형성 방법.And the second barrier metal layer is a TiN film. 제 3 항 또는 제 4 항 중 어느 하나에 있어서,The method according to any one of claims 3 to 4, 상기 제1 및 제2 배리어 금속층은 Ar 스퍼터링을 이용하여 400℃ 이하의 온도 및 10Torr 이하의 압력에서 수행되는 것을 특징으로 하는 텅스텐 비트 라인 형성 방법.And the first and second barrier metal layers are formed at a temperature of 400 ° C. or less and a pressure of 10 Torr or less using Ar sputtering. 제 1 항에 있어서,The method of claim 1, RTP 어닐링을 수행하는 단계는 700 내지 1000℃의 온도에서 수행되는 것을 특징으로 하는 텅스텐 비트 라인 형성 방법.The step of performing the RTP annealing is carried out at a temperature of 700 to 1000 ℃ a tungsten bit line forming method. 제 1 항에 있어서,The method of claim 1, 상기 제3 배리어 금속층은 TiN막인 것을 특징으로 하는 텅스텐 비트 라인 형성 방법.And the third barrier metal layer is a TiN film.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990012160A (en) * 1997-07-28 1999-02-25 윤종용 Morse element having a source / drain silicide and a method of manufacturing the same
KR20000004457A (en) * 1998-06-30 2000-01-25 윤종용 Method for manufacturing semiconductor device having local silicide film

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990012160A (en) * 1997-07-28 1999-02-25 윤종용 Morse element having a source / drain silicide and a method of manufacturing the same
KR20000004457A (en) * 1998-06-30 2000-01-25 윤종용 Method for manufacturing semiconductor device having local silicide film

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