JPH07122747A - Formation of gate electrode structure - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the dielectric strength between a gate electrode and wiring layer and, at the same time, to prevent the formation of overhang parts on the side wall of the gate electrode. CONSTITUTION:A gate electrode structure forming method consists of (a) a process for forming a gate oxide film 12, polysilicon layer 14, and silicide layer 16 on a semiconductor substrate 10 and (b) another process for etching the layers 16 and 14 and oxidizing a reaction product 30 in such a state that the side walls of the layers 16 and 14 are coated with the reaction product 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode structure in a semiconductor device.

[0002]

2. Description of the Related Art With the progress of high integration of semiconductor devices, the demand for fine processing technology is becoming more and more severe. The dry etching technology in the manufacturing process of semiconductor devices is no exception, and various studies are being carried out with the aim of highly accurate processing.

In the recent SRAM manufacturing technology, the cell size has been reduced by utilizing a self-aligned contact (SAC) process. Hereinafter, using the schematic partial cross-sectional views of the semiconductor device of FIGS. 7 and 8, S
The AC process will be briefly described.

[0004] [Step -10] For example, the surface of the semiconductor substrate 10 made of a silicon semiconductor substrate, after forming a gate oxide film 12 made of SiO _2, a silicide layer made of polysilicon layer 14 and tungsten silicide (WSi _X) 16 is deposited. After that, an oxide film made of SiO ₂ is formed on the silicide layer 16, and the oxide film is patterned by the photolithography technique and the dry etching technique (see FIG. 7A). The oxide film thus obtained is also called an offset oxide film 20, and a gate electrode is formed below the offset oxide film 20 in the next step.

[Step-20] That is, the offset oxide film 2
Using 0 as a mask, the silicide layer 16 and the polysilicon layer 14 are dry-etched by the RIE method (see FIG. 7B). Thus, the gate electrode 18 having the polycide structure including the patterned polysilicon layer 14 and the silicide layer 16 is formed. Depending on the dry etching conditions, the side wall of the gate electrode 18 may be covered with the reaction product generated by the reaction between the dry etching gas and polysilicon or silicide. In this case, for example, hydrofluoric acid is used to remove the reaction product.

[Step-30] Then, after performing LDD ion implantation, an insulating film 22 made of SiO ₂ is deposited on the entire surface in order to form a gate sidewall on the sidewall of the gate electrode 18 ((in FIG. See C)).

[Step-40] Next, the insulating film 22 made of SiO ₂ is etched back to form a gate sidewall 22A on the sidewall of the gate electrode 18. The gate sidewall 22A also extends to the sidewall of the offset oxide film 20. At the same time, a part of the gate oxide film 12 formed on the surface of the semiconductor substrate 10 is also removed (FIG. 8).
(A)). Thus, the gate electrode structure including the gate oxide film 12, the polysilicon layer 14, the silicide layer 16, the gate sidewall 22A, and the offset oxide film 20 is formed.

[Step-50] After that, impurity ion implantation is performed to form the source / drain regions 24.

[Step-60] Next, a wiring layer 26 made of, for example, polysilicon is formed on the source / drain regions 24 and the gate sidewalls 22A (see FIG. 7E). The offset oxide film 20 and the gate sidewall 22A are left as they are as an interlayer insulating film.

[0010]

In the above SAC process, in step [30], the insulating film 22 made of SiO ₂ is formed by the CVD method while the semiconductor substrate is heated to about 700 ° C. . Since the semiconductor substrate 10 is heated to about 700 ° C. before the insulating film 22 is started to be deposited, the WSi _X is formed in the silicide layer 16 made of WSi _X.
7C grows, and the silicide layer 16 is in a state of protruding in a whisker shape from the side wall of the gate electrode 18, as shown in FIG. 7C. This part is 1
6B. Therefore, as shown in FIG. 8B, there is a problem that the breakdown voltage between the gate electrode 18 and the wiring layer 26 is deteriorated. In addition, such a silicide layer 1
6 projects from the side wall of the gate electrode 18,
An overhang portion may be formed on the gate sidewall 22A, and as a result, a stringer (a streak-like residue of a natural oxide film that remains after etching the wiring layer 26) is generated when the wiring layer 26 made of polysilicon is formed. There is also a risk of

Therefore, an object of the present invention is to provide the gate electrode 18
It is an object of the present invention to provide a method for forming a gate electrode structure in a semiconductor device, which does not cause deterioration in withstand voltage between the wiring layer 26 and the wiring layer 26 and does not form an overhang portion in the gate sidewall 22A.

[0012]

The method for forming a gate electrode structure according to the first aspect of the present invention for achieving the above object is as follows: (a) A gate oxide film, a polysilicon layer and a silicide on a semiconductor substrate. Forming a layer and etching the (b) silicide layer and the polysilicon layer, and then
And a step of oxidizing the reaction product while the sidewalls of the silicide layer and the polysilicon layer are covered with the reaction product generated by etching.

In this case, it is desirable that the reaction product be a Si-based compound and capable of forming an oxide.

Second aspect of the present invention for achieving the above object
The method of forming a gate electrode structure according to the aspect of (1) comprises: (a) forming a gate oxide film, a polysilicon layer and a silicide layer on a semiconductor substrate; and (b) etching the silicide layer and the polysilicon layer. So that the side wall of the silicide layer is recessed more than the side wall of the polysilicon layer,
It is characterized in that the silicide layer is etched.

A third aspect of the present invention for achieving the above object.
The method of forming a gate electrode structure according to the aspect of (1), (a) forming a gate oxide film, a polysilicon layer and a silicide layer on the semiconductor substrate; and (b) heating the semiconductor substrate to a predetermined temperature, (C) The step of etching the silicide layer and the polysilicon layer.

In this case, after the step (c), the method further includes (d) a step of depositing an insulating film on the entire surface to form a gate sidewall, and the predetermined temperature in the step (b) is (d) The temperature may be equal to or higher than the temperature for heating the semiconductor substrate in order to deposit the insulating film in the step (1).

In the method of forming a gate electrode structure according to the first to third aspects of the present invention, in the step (a),
It is preferable to form an offset oxide film on the silicide layer above the gate electrode formation planned region.

[0018]

In the method of forming the gate electrode structure according to the first aspect of the present invention, the sidewalls of the silicide layer and the polysilicon layer are covered with the oxide of the reaction product. Therefore, when the insulating film is formed by the CVD method to form the gate side wall, even if the semiconductor substrate is heated to about 700 ° C., the silicide grains grown in the silicide layer protrude from the side wall of the gate electrode. Can be suppressed.

In the method of forming the gate electrode structure according to the second aspect of the present invention, the silicide layer is etched so that the side wall of the silicide layer is recessed more than the side wall of the polysilicon layer. Therefore, when the insulating film is formed by the CVD method to form the gate sidewall, the semiconductor substrate is heated to about 700 ° C. Even if the silicide grains grow laterally in the silicide layer, It is possible to prevent the layer from protruding from the side wall of the gate electrode.

In the method of forming the gate electrode structure according to the third aspect of the present invention, after the gate oxide film, the polysilicon layer and the silicide layer are formed on the semiconductor substrate, the semiconductor substrate is heated to a predetermined temperature. Therefore, lateral growth of the silicide grains in the silicide layer is substantially complete during this heating. Therefore, even if the semiconductor substrate is heated to about 700 ° C. when the silicide layer and the polysilicon layer are etched in the subsequent steps and then the insulating film is formed by the CVD method to form the gate sidewall, There is no lateral growth of silicide grains in the silicide layer. Therefore, it is possible to prevent the silicide layer from protruding from the side wall of the gate electrode.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A gate electrode forming method of the present invention will be described below with reference to the drawings based on the embodiments.

Example 1 Example 1 relates to a method of forming a gate electrode structure according to the first aspect of the present invention. Less than,
The method of Example 1 will be described with reference to FIGS. 1 and 2 which are schematic partial cross-sectional views of a semiconductor device.

[Step-100] For example, S is formed on the surface of the semiconductor substrate 10 made of a silicon semiconductor substrate by a thermal oxidation method.
After forming the gate oxide film 12 having a thickness of 10nm made iO _2, a thickness of 100nm n ⁺ polysilicon layer 14 and the thickness 100nm of the tungsten silicide (WSi _X)
A silicide layer 16 made of, for example, CV under the following conditions:
The gate oxide film 12 is sequentially deposited by the D method. Formation of n ⁺ Polysilicon Layer 14 Gas used: SiH ₄ / PH ₃ (SiH ₄ base 0.5
%) = 400/100 sccm Pressure: 40 Pa Substrate temperature: 550 ° C. Formation of silicide layer 16 made of tungsten silicide Working gas: SiH ₄ / WF ₆ = 1000/10 sccm Pressure: 27 Pa Substrate temperature: 360 ° C.

After that, an oxide film made of SiO ₂ is formed on the silicide layer 16, and the oxide film is patterned by the photolithography technique and the dry etching technique (see FIG. 1A). Thus, the offset oxide film 20
Is formed. A gate electrode is formed below the offset oxide film 20 in the next step.

[Step-110] Next, using the offset oxide film 20 as a mask, the silicide layer 16 made of tungsten silicide and the polysilicon layer 14 are EC-coated.
Dry etching is performed using an R plasma etching apparatus (see FIG. 1B). A gate electrode 18 having a polycide structure composed of a patterned polysilicon layer 14 and a silicide layer 16 made of tungsten silicide can be formed. The conditions of dry etching can be set as follows, for example. Gas used: Cl ₂ / O ₂ = 75/15 sccm Pressure: 1 Pa Microwave power: 850 W (2.45 GHz) RF bias: 40 W (2 MHz) Substrate temperature: -10 ° C

The silicide layer 16 and the polysilicon layer 14
Is anisotropically etched, the sidewalls of the silicide layer 16 and the polysilicon layer 14 are covered with the reaction product 30 (see FIG. 1B). In the conventional method of forming the gate electrode structure, the reaction product 30
Are removed using, for example, hydrofluoric acid. In the method of Example 1, this reaction product 30 is not removed. The composition of the reaction product 30 is mainly SiCl _x , and in addition, SiO _x ,
WCl _X , SiO _X Cl _{Y and the} like are included. The reaction product 30 also extends to the sidewall of the offset oxide film 20.

With the reaction product 30 thus generated by etching covering the sidewalls of the silicide layer 16 and the polysilicon layer 14, the reaction product 3 is then formed.
Oxidize 0. Oxidation of the reaction product 30 can be performed using a microwave downstream asher device, for example, under the following conditions. Gas used: O ₂ = 100 sccm Pressure: 5 Pa Microwave power: 1000 W (2.45 GHz) Substrate temperature: 300 ° C Time: 10 minutes

As a result, the side walls of the silicide layer 16 and the polysilicon layer 14 are covered with the reaction product oxide 30A (see FIG. 1C). The main composition of the reaction product oxide 30A is SiO _X Cl _Y.

In this [Step-110], Cl ₂ / O ₂ gas was used for dry etching of the silicide layer 16 and the polysilicon layer 14, but instead of this, Cl ₂ / O ₂ gas was used.
_The silicide layer 16 may be mainly dry-etched using ₂ / O ₂ gas, and then the polysilicon layer 14 may be dry-etched using HBr / O ₂ gas or HI / O ₂ gas. The dry etching conditions when using HBr / O ₂ gas or HI / O ₂ are illustrated below. Gas used: HBr (or HI) / O ₂ = 12
0 / 4sccm Pressure: 1Pa Microwave power: 850W (2.45GHz) RF bias: 30W (2MHz) Substrate temperature: -10 ° C

In this case, when the silicide layer 16 and the polysilicon layer 14 are anisotropically etched, the sidewalls of the silicide layer 16 and the polysilicon layer 14 are covered with the reaction product 30. Incidentally, the main composition of the reaction product 30, SiCl _X + SiBr _X like (in the case of using a HI gas, SiCl _X + SiI _X, etc.). Further, by oxidizing the reaction product 30, the side walls of the silicide layer 16 and the polysilicon layer 14 are covered with the reaction product oxide 30A. The main composition of the oxide of the reaction product is SiO _X Cl _Y + SiO _X Br _Y (H
When I gas is used, SiO _X Cl _Y + SiO _X I _Y )
Is.

[Step-120] Next, after performing LDD ion implantation, an insulating film 22 made of SiO ₂ is deposited on the entire surface to form a gate sidewall on the sidewall of the gate electrode 18 (see FIG. 1). (D)). The deposition conditions of the insulating film 22 can be set as follows, for example. Gas used: TEOS = 800 sccm Substrate temperature: 720 ° C Pressure: 10 Pa Film thickness: 0.5 μm

The oxide of such a case that the insulating film 22 made of SiO ₂ is deposited on the entire surface under the conditions, lateral growth is the reaction product of silicide grains consisting WSi _X of within the silicide layer 16 made of WSi _X It is suppressed by 30A. Therefore, the silicide layer 16 can be prevented from protruding from the side wall of the gate electrode 18.

[Step-130] Next, the insulating film 22 made of SiO ₂ is etched back. As a result, the gate sidewall 22A can be formed on the sidewall of the gate electrode 18 having the polycide structure including the polysilicon layer 14 and the silicide layer 16. At the same time, a part of the gate oxide film 12 formed on the surface of the semiconductor substrate 10 is also removed (see FIG. 2A). The gate sidewall 22A also extends to the sidewall of the offset oxide film 20. Thus, the gate oxide film 12 and the polysilicon layer 1
4, silicide layer 16, gate sidewall 22A,
A gate electrode structure composed of the offset oxide film 20 is formed. The entire surface of the insulating film 22 made of SiO ₂ can be etched back under the following conditions, for example. Gas used: C ₄ F ₈ = 50 sccm RF bias: 1200 W Pressure: 2 Pa

[Step-140] After that, impurity ion implantation is performed to form the source / drain regions 24. Impurity ion implantation is performed, for example, under the following conditions. Formation of N-type channel As 20 KeV, 5 × 10 ¹⁵ / cm ² Formation of P-type channel BF _{2 20} KeV, 3 × 10 ¹⁵ / cm ²

[Step-150] Next, the wiring layer 26 made of, for example, polysilicon is formed on the source / drain regions 24 and the gate sidewalls 22A (FIG. 2).
(B)). The offset oxide film 20 and the gate sidewall 22A are left as they are as an interlayer insulating film. In this way, a semiconductor element is formed by the SAC process.

Example 2 Example 2 relates to a method of forming a gate electrode structure according to the second aspect of the present invention. Less than,
The method of the second embodiment will be described with reference to FIGS. 3 and 4 which are schematic partial cross-sectional views of the semiconductor element.

[Step-200] [Step-10 of Example 1]
0], the semiconductor substrate 10
Above, the gate oxide film 12, the polysilicon layer 14, and a silicide layer 16 made of tungsten silicide (WSi _X) is formed, further, to form an offset oxide film 20 (see (A) in FIG. 3).

[Step-210] Next, the silicide layer 16 and the polysilicon layer 14 are dry-etched by the RIE method using the offset oxide film 20 as a mask (see FIG. 3B). At this time, the silicide layer is etched so that the side wall of the silicide layer 16 is recessed from the side wall of the polysilicon layer 14. The concave portion of the silicide layer 16 is indicated by 16A. Thus, the gate electrode 18 having the polycide structure composed of the patterned polysilicon layer 14 and the silicide layer 16 is formed. The conditions of dry etching can be set as follows, for example. Gas used: Cl ₂ / O ₂ = 75/15 sccm Pressure: 1Pa Microwave power: 850W (2.45GHz) RF bias: 40W (2MHz) Substrate temperature: 30 ° C

In Example 1, the substrate temperature during etching was set to -10 ° C. On the other hand, in Example 2, the substrate temperature during etching is set to 30 ° C. in this way,
By making the substrate temperature during etching higher than that in Example 1, the etching rate of the silicide layer 16 becomes faster than the etching rate of the polysilicon layer 14 when Cl ₂ / O ₂ gas is used. When Cl ₂ / O ₂ gas is used, Si in the silicide layer 16 and the polysilicon layer 14
Based on the above, SiO _X Cl _Y and SiO _X are generated. Further, WO _X Cl _Y is generated based on W in the silicide layer 16 made of WSi _X. The etching rate of WO _X Cl _Y is faster than that of SiO _X Cl _Y or SiO _X. as a result,
The silicide layer 16 is etched so that the side wall of the silicide layer 16 is recessed from the side wall of the polysilicon layer 14 to form a recess 16A (see FIG. 3B).

In this [Step-210], Cl ₂ / O ₂ gas was used for dry etching of the silicide layer 16 and the polysilicon layer 14, but instead of this, Cl ₂ / O ₂ gas was used.
_The silicide layer 16 may be etched mainly by using ₂ / O ₂ gas, and then the polysilicon layer 14 may be dry-etched by using HBr / O ₂ gas or HI / O ₂ gas. The dry etching conditions when using HBr / O ₂ gas or HI / O ₂ are illustrated below. Gas used: HBr (or HI) / O ₂ = 12
0 / 4sccm Pressure: 1Pa Microwave power: 850W (2.45GHz) RF bias: 30W (2MHz) Substrate temperature: 30 ° C

The silicide layer 16 and the polysilicon layer 14
After anisotropic etching, the reaction products (not shown) deposited on the side walls of the silicide layer 16 made of WSi _x and the polysilicon layer 14 are removed by using, for example, hydrofluoric acid.

[Step-220] Next, after performing the LDD ion implantation, in order to form the gate sidewall on the side wall of the gate electrode 18, as in the case of [Step-120] of the first embodiment, SiO 2 is formed on the entire surface. _An insulating film 22 made of ₂ is deposited (see FIG. 3C). When depositing the insulating film 22 on the entire surface, so silicide grains consisting of WSi _X in the silicide layer 16 made of WSi _X is will be grown in the lateral direction, advance sidewalls of the silicide layer 16 is recessed than the sidewalls of the polysilicon layer 14 Since the silicide layer 16 is formed in the above, it is possible to prevent the silicide grains grown in the lateral direction from protruding from the side wall of the gate electrode 18.

[Step-230] Next, the insulating film 22 made of SiO ₂ is etched back to form gate sidewalls 22A on the sidewalls of the gate electrode 18 and the offset oxide film 20. At the same time, a part of the gate oxide film 12 formed on the surface of the semiconductor substrate 10 is also removed (see FIG. 4A). Thus, the gate electrode structure including the gate oxide film 12, the polysilicon layer 14, the silicide layer 16, the gate sidewall 22A, and the offset oxide film 20 is formed. The insulating film 2 made of SiO ₂
The entire surface etch-back of No. 2 is performed by, for example, [Step-1 of Example 1
30].

[Step-240] After that, as in [Step-140] and [Step-150] of the first embodiment, the source / drain regions 24 are formed by impurity ion implantation, and the wiring layer 26 made of polysilicon is formed. Is performed (see FIG. 4B).

Example 3 Example 3 relates to a method of forming a gate electrode structure according to the third aspect of the present invention. Less than,
The method of the third embodiment will be described with reference to FIGS. 5 and 6 which are schematic partial cross-sectional views of the semiconductor element.

[Step-300] [Step-10 of Example 1]
0], the semiconductor substrate 10
A gate oxide film 12, a polysilicon layer 14 and a silicide layer 16 are formed on top, and an offset oxide film 20 is further formed (see FIG. 5A).

[Step-310] Next, the semiconductor substrate 10 is heated to a predetermined temperature (see FIG. 5B). This predetermined temperature is preferably equal to or higher than the temperature at which the semiconductor substrate 10 is heated to form the insulating film 22 in [Step-330]. Specifically, in an inert gas atmosphere, 6
00 ° C to 900 ° C x 5 to 6 minutes, for example 720
Heat treatment at ° C x 5 minutes. By this heat treatment, silicide grains grow laterally in the silicide layer 16. Since the lateral growth of the silicide grains is almost completed in this step, the lateral growth of the silicide grains hardly occurs in the heat treatment in the subsequent steps.

[Step-320] Next, as in [Step-110] of the first embodiment, the silicide layer 16 made of tungsten silicide and the polysilicon layer 14 are subjected to RIE by using the offset oxide film 20 as a mask. Dry etching is performed (see FIG. 5C). After that, the reaction product (not shown) deposited on the sidewalls of the offset oxide film 20, the silicide layer 16 and the polysilicon layer 14 may be removed by using, for example, hydrofluoric acid, or may be left as it is. .

[Step-330] Next, LDD ion implantation
After performing the above, the gate sidewall is attached to the sidewall of the gate electrode 18.
[Step-120] of Example 1 to form a
Similarly, the entire surface is SiO ₂An insulating film 22 made of
(See FIG. 6A). [Step-310]
In the silicide layer 16, the silicide grains are already in the lateral direction.
Since it has grown, when the insulating film 22 is deposited on the entire surface,
Even if the semiconductor substrate 10 is heated, the silicide layer 16 is gated
It does not project from the side wall of the electrode 18.

[Step-340] Next, the insulating film 22 made of SiO ₂ is etched back to form the gate sidewall 22A on the side wall of the gate electrode 18 made of the patterned polysilicon layer 14 and the silicide layer 16. At the same time, a part of the gate oxide film 12 formed on the surface of the semiconductor substrate 10 is also removed (see FIG. 6B). Thus, the gate oxide film 12 and the polysilicon layer 1
4, silicide layer 16, gate sidewall 22A,
A gate electrode structure composed of the offset oxide film 20 is formed. The entire surface of the insulating film 22 made of SiO ₂ can be etched back in the same manner as in [Step-130] of the first embodiment.

[Step-350] After that, as in [Step-140] and [Step-150] of the first embodiment, the source / drain regions 24 are formed by impurity ion implantation, and the wiring layer 26 made of polysilicon is formed. Is performed (see FIG. 6C).

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The conditions and numerical values described in the examples are examples,
It can be changed appropriately.

Silicide layer 1 forming the gate electrode 18
Instead of tungsten silicide, 6 can be composed of refractory metal silicide such as molybdenum silicide, titanium silicide, or tantalum silicide.

In the method of forming the gate electrode structure according to the second and third aspects of the present invention, the offset oxide film 20 is used.
Can be omitted in some cases. In this case, a resist layer may be formed on the silicide layer above the gate electrode formation planned region, and the silicide layer and the polysilicon layer may be etched using the resist layer as a mask. Then, the reaction product attached to the side wall of the resist layer and the side wall of the formed gate electrode may be removed with, for example, hydrofluoric acid.

[0055]

According to the method of forming a gate electrode structure of the present invention, it is possible to prevent the silicide layer from protruding from the side wall of the gate electrode. As a result, the gate electrode 18 and the wiring layer 2
6 does not cause deterioration of the withstand voltage. Further, no overhanging portion is formed on the gate sidewall 22A. Therefore, a highly reliable gate electrode structure can be formed.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor element in each step for explaining a method of forming a gate electrode structure of Example 1.

FIG. 2 is a schematic partial cross-sectional view of the semiconductor element in each step for explaining the method of forming the gate electrode structure of Example 1 subsequent to FIG.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor element in each step for explaining a method of forming a gate electrode structure of Example 2.

FIG. 4 is a schematic partial cross-sectional view of the semiconductor element in each step for explaining the method of forming the gate electrode structure according to the second embodiment, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of a semiconductor element in each step for explaining a method of forming a gate electrode structure of Example 3.

FIG. 6 is a schematic partial cross-sectional view of the semiconductor element in each step for explaining the method of forming the gate electrode structure of Example 3 subsequent to FIG. 5;

FIG. 7 is a schematic partial cross-sectional view of a semiconductor element in each step for explaining a conventional method of forming a gate electrode structure.

FIG. 8 is a schematic partial cross-sectional view of the semiconductor element in each step for explaining the conventional method for forming the gate electrode structure, following FIG. 7;

[Explanation of symbols]

 10 semiconductor substrate 12 gate oxide film 14 polysilicon layer 16 silicide layer 18 gate electrode 20 offset oxide film 22 insulating film 22A gate sidewall 24 source / drain region 26 wiring layer 30 reaction product 30A reaction product oxide

Claims (6)

[Claims] 1. A step of: (a) forming a gate oxide film, a polysilicon layer and a silicide layer on a semiconductor substrate; and (b) etching the silicide layer and the polysilicon layer, and then producing a reaction generated by the etching. A step of oxidizing the reaction product in a state where the side walls of the silicide layer and the polysilicon layer are covered with a material, the method for forming a gate electrode structure. 2. The method for forming a gate electrode structure according to claim 1, wherein the reaction product is a Si-based compound and is capable of forming an oxide. 3. A step of: (a) forming a gate oxide film, a polysilicon layer and a silicide layer on a semiconductor substrate; and (b) a step of etching the silicide layer and the polysilicon layer. A method for forming a gate electrode structure, comprising: etching a silicide layer so as to be recessed from a sidewall of a polysilicon layer. 4. (a) A step of forming a gate oxide film, a polysilicon layer and a silicide layer on a semiconductor substrate, (b) a step of heating the semiconductor substrate to a predetermined temperature, and (c) a silicide layer and a polysilicon layer. A method of forming a gate electrode structure, which comprises the step of etching a silicon layer. 5. The method further comprises, after the step (c), a step (d) of depositing an insulating film on the entire surface to form a gate sidewall, wherein the predetermined temperature in the step (b) is The method for forming a gate electrode structure according to claim 4, wherein the temperature is equal to or higher than the temperature at which the semiconductor substrate is heated to deposit the insulating film in the step (d). 6. The offset oxide film is formed on the silicide layer above the gate electrode formation planned region in the step (a), according to any one of claims 1 to 5. Method of forming gate electrode structure.