KR100416814B1 - Method for forming interlayer dielectric of semiconductor device - Google Patents
Method for forming interlayer dielectric of semiconductor device Download PDFInfo
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- KR100416814B1 KR100416814B1 KR1019960057362A KR19960057362A KR100416814B1 KR 100416814 B1 KR100416814 B1 KR 100416814B1 KR 1019960057362 A KR1019960057362 A KR 1019960057362A KR 19960057362 A KR19960057362 A KR 19960057362A KR 100416814 B1 KR100416814 B1 KR 100416814B1
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- Prior art keywords
- forming
- insulating film
- film
- semiconductor device
- bpsg
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000011229 interlayer Substances 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 26
- 238000009413 insulation Methods 0.000 abstract description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052731 fluorine Inorganic materials 0.000 abstract description 5
- 239000011737 fluorine Substances 0.000 abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- 239000005368 silicate glass Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 층간 절연막 형성방법에 관한 것으로 특히, 폴리실리콘층 및 금속층 간의 절연 및 단차완화를 위하여 다층으로 이루어지는 층간 절연막 형성시 각 절연막에 대한 식각 비율 차이를 동일하게 할 수 있는 반도체 소자의 층간 절연막 형성방법에 관한 것이다.The present invention relates to a method of forming an interlayer insulating film of a semiconductor device, and more particularly, to a semiconductor device capable of equalizing the difference in etching rates for each insulating film when forming a multilayer interlayer insulating film for insulating and reducing step difference between a polysilicon layer and a metal layer. A method of forming an interlayer insulating film.
일반적으로 반도체 소자의 제조공정중 층간 절연 및 단차 완화를 위하여 산화막 및 BPSG(Borophospho Silicate Glass)막이 적층된 형태를 갖는 층간 절연막을 사용하게 된다. 종래에는 소정의 제조공정을 거쳐 실리콘 기판상에 게이트 전극 및 접합영역을 형성하고, 그 전체 상부면에 게이트 전극을 이루는 폴리실리콘층과 후속공정의 금속층 사이에 절연 및 단차 완화를 위하여 TEOS(Tetra Ethyl OthoSilicate) 베이스(Base) 산화막 및 BPSG막을 순차적으로 형성한 후 콘택홀을 형성하기 위하여 상기 산화막 및 BPSG막을 순차적으로 식각할 때 산화막 및 BPSG막의 식각 비율 차이로 인하여 층의 경계면에 턱이 생기게 된다. 이는 금속층의 스텝 커버리지(Stpe Coverage)를 나쁘게 하며 심한 경우 금속층의 단선 현상으로 소자의 신뢰성을 저하시키는 문제가 발생된다.In general, an interlayer insulating film having a form in which an oxide film and a BPSG (Borophospho Silicate Glass) film are stacked in order to reduce interlayer insulation and step difference in a semiconductor device manufacturing process is used. Conventionally, a gate electrode and a junction region are formed on a silicon substrate through a predetermined manufacturing process, and TEOS (Tetra Ethyl) is used to reduce insulation and step difference between the polysilicon layer forming the gate electrode on the entire upper surface thereof and the metal layer of the subsequent process. After sequentially forming the base oxide layer and the BPSG layer, the etch occurs at the interface between the layers due to the difference in the etching ratio between the oxide layer and the BPSG layer in order to sequentially etch the oxide layer and the BPSG layer to form a contact hole. This deteriorates the step coverage of the metal layer and, in severe cases, a problem of deterioration of the reliability of the device due to disconnection of the metal layer occurs.
따라서 본 발명은 소정의 제조공정을 거쳐 실리콘 기판상에 게이트 전극및 접합영역을 형성하고, 그 전체 상부면에 산화막을 형성한 후 산화막 상에 불소(F) 계열의 가스를 이온주입하여 산화막 내의 원자 결합력을 약화시키고, 그 위에 BPSG막을 형성하여 산화막이 BPSG막과 동일한 식각비율을 갖도록 형성할 수 있는 반도체 소자의 층간 절연막 형성방법을 제공하는 것을 그 목적으로 한다.Accordingly, the present invention forms a gate electrode and a junction region on a silicon substrate through a predetermined manufacturing process, forms an oxide film on the entire upper surface thereof, and then implants fluorine (F) -based gas on the oxide film to form atoms in the oxide film. It is an object of the present invention to provide a method for forming an interlayer insulating film of a semiconductor device in which the bonding force is weakened and a BPSG film is formed thereon so that the oxide film can be formed to have the same etching rate as that of the BPSG film.
상술한 목적을 실현하기 위한 본 발명에 따른 반도체 소자의 층간 절연막형성방법은 소정의 제조공정으로 게이트 전극 및 접합영역이 형성된 실리콘 기판의 전체 상부면에 절연막을 형성하는 단계와, 절연막 내의 원자 결합력을 약화시키기 위하여 상기 절연막 내에 이온 주입공정을 실시하는 단계와, 절연막 상에 BPSG막을 형성하는 단계로 이루어진다.The interlayer insulating film forming method of a semiconductor device according to the present invention for realizing the above object is to form an insulating film on the entire upper surface of the silicon substrate on which the gate electrode and the junction region are formed in a predetermined manufacturing process, and the atomic bonding force in the insulating film In order to weaken, an ion implantation process is performed in the insulating film, and a BPSG film is formed on the insulating film.
도 1A 내지 1E는 본 발명에 따른 반도체 소자의 층간 절연막 형성방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 기호설명><Description of Symbols on Main Parts of Drawing>
1 : 실리콘기판 2 : 폴리실리콘층1: silicon substrate 2: polysilicon layer
3 : 텅스텐 실리사이드층 4 : 접합영역3: tungsten silicide layer 4: junction region
5 : 스페이서 6 : 절연막5 spacer 6 insulating film
7 : BPSG막 A : 콘택홀7: BPSG film A: contact hole
10 : 게이트 전극10: gate electrode
이하, 본 발명에 따른 층간 절연막 형성방법을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, a method of forming an interlayer insulating film according to the present invention will be described in detail with reference to the accompanying drawings.
도 1A 내지 1E는 층간 절연막 형성방법을 설명하기 위한 소자의 단면도로서, 도 1A는 실리콘 기판(1)상에 폴리실리콘층(2) 및 텅스텐 실리사이드층(3)으로 이루어지는 게이트 전극(10)을 형성한 후 접합영역(4)을 형성하고, 게이트 전극(10)의 양 측벽에 스페이서(5)를 형성한 상태를 도시한다. 텅스텐 실리사이드층(3)은 2000 내지 2500Å의 두께로 형성된다.1A to 1E are cross-sectional views of a device for explaining an interlayer insulating film forming method, and FIG. 1A shows a gate electrode 10 formed of a polysilicon layer 2 and a tungsten silicide layer 3 on a silicon substrate 1. After that, the junction region 4 is formed and the spacers 5 are formed on both sidewalls of the gate electrode 10. The tungsten silicide layer 3 is formed to a thickness of 2000 to 2500 kPa.
도 1B는 실리콘 기판(1)의 전체 상부면에 산화막(6)을 형성한 상태를 도시한다. 산화막(6)은 TEOS 베이스 산화막으로 이루어지며 저압 화학 기상 증착(LPCVD) 방법으로 800 내지 850℃의 온도 조건에서 1500 내지 2500Å의 두께로 형성된다.FIG. 1B shows a state in which the oxide film 6 is formed on the entire upper surface of the silicon substrate 1. The oxide film 6 is made of a TEOS base oxide film and is formed to a thickness of 1500 to 2500 Pa by a low pressure chemical vapor deposition (LPCVD) method at a temperature of 800 to 850 ° C.
도 1C는 산화막(6) 내에 F계열 가스를 이온 주입공정으로 주입하는 상태를 도시한다. 이온주입 공정은 60 내지 80KeV의 에너지 및 1014내지 1015이온/cm2의이온량 조건에서 실시된다. 이때, 불소(F) 이온은 산화막(6) 내로 주입되어 산화막(6) 내의 원자 결합력을 약화시키게 된다.FIG. 1C shows a state in which an F-based gas is injected into the oxide film 6 by an ion implantation process. The ion implantation process is carried out at an energy of 60 to 80 KeV and an ion amount of 10 14 to 10 15 ions / cm 2 . At this time, fluorine (F) ions are injected into the oxide film 6 to weaken the atomic bonding force in the oxide film 6.
도 1D는 산화막(6) 상에 BPSG막(7)을 형성한 상태를 도시한다. BPSG막(7)은 상압 화학 기상 증착(APCVD) 방법으로 900 내지 920℃의 온도조건에서 5000내지 7000Å의 두께로 형성된다.1D shows a state where the BPSG film 7 is formed on the oxide film 6. The BPSG film 7 is formed to a thickness of 5000 to 7000 kPa under an atmospheric chemical vapor deposition (APCVD) method at a temperature of 900 to 920 ° C.
도 1E는 후속공정의 콘택홀(A)을 형성하기 위하여 접합영역(4)이 노출되도록건식 식각방법으로 BPSG막(7) 및 산화막(6)을 순차적으로 식각한 후 BPSG막(7)을 습식 식각방법으로 식각한 상태를 도시한다. 이때, 산화막(6) 및 BPSG막(7)의 경계면에는 식각비율이 동일하므로 턱이 생기지 않게된다.FIG. 1E sequentially wets the BPSG film 7 and the oxide film 6 by a dry etching method to expose the junction region 4 to form a contact hole A in a subsequent process, and then wets the BPSG film 7. The state etched by the etching method is shown. At this time, since the etching rate is the same on the interface between the oxide film 6 and the BPSG film 7, the jaw is not formed.
본 실시예에서는 반도체 소자의 제조공정 중 산화막(6) 및 BPSG막(7)으로 이루어진 층간 절연막의 콘택홀 형성을 양호하게 하기 위한 예를 설명하였으나 이것에 한정되는 것은 아니다. 즉, 산화막(6) 및 BPSG막(7)으로 이루는 절연막의 어떠한 패턴을 실시하는 경우에 양호한 패턴을 얻기 위하여 적용할 수 있음은 물론이다.In the present embodiment, an example for improving the contact hole formation of the interlayer insulating film composed of the oxide film 6 and the BPSG film 7 during the manufacturing process of the semiconductor device has been described, but the present invention is not limited thereto. That is, of course, it can be applied to obtain a good pattern when any pattern of the insulating film composed of the oxide film 6 and the BPSG film 7 is performed.
상술한 바와같이 본 발명에 의하면 소정의 제조공정을 거쳐 실리콘 기판상에 게이트 전극 및 접합영역을 형성하고, 그 전체 상부면에 산화막을 형성한 후 산화막 상에 불소 계열의 가스를 이온주입하여 산화막 내의 원자 결합력을 약화시키고, 그 위에 BPSG막을 형성하여 산화막이 BPSG막과 식각비율이 동일하도록 형성하므로써 양호한 패턴을 얻을 수 있음은 물론 접합영역이 노출되도록 절연막 및 BPSG막의 순차적인 식각공정시 과도 식각을 방지하므로써 노출된 접합영역에 미치는 영향을 최소화 할 수 있는 효과가 있다.As described above, according to the present invention, a gate electrode and a junction region are formed on a silicon substrate through a predetermined manufacturing process, an oxide film is formed on the entire upper surface thereof, and fluorine-based gas is ion-implanted on the oxide film, thereby By weakening the atomic bonding force and forming a BPSG film thereon, the oxide film is formed to have the same etching rate as the BPSG film, so that a good pattern can be obtained. As a result, the effect on the exposed junction area can be minimized.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960057362A KR100416814B1 (en) | 1996-11-26 | 1996-11-26 | Method for forming interlayer dielectric of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960057362A KR100416814B1 (en) | 1996-11-26 | 1996-11-26 | Method for forming interlayer dielectric of semiconductor device |
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| Publication Number | Publication Date |
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| KR19980038458A KR19980038458A (en) | 1998-08-05 |
| KR100416814B1 true KR100416814B1 (en) | 2004-04-06 |
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