KR20020056285A - Method for manufacturing gate in semiconductor device - Google Patents
Method for manufacturing gate in semiconductor device Download PDFInfo
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- KR20020056285A KR20020056285A KR1020000085608A KR20000085608A KR20020056285A KR 20020056285 A KR20020056285 A KR 20020056285A KR 1020000085608 A KR1020000085608 A KR 1020000085608A KR 20000085608 A KR20000085608 A KR 20000085608A KR 20020056285 A KR20020056285 A KR 20020056285A
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- gate
- film
- layer
- hole
- etch stop
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 85
- 239000010409 thin film Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000002265 prevention Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
Description
본 발명은 반도체 소자의 게이트 제조방법에 관한 것으로, 보다 구체적으로는, 자기정렬콘택 공정을 사용하는 게이트 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a gate of a semiconductor device, and more particularly, to a method for manufacturing a gate using a self-aligned contact process.
최근, 소자가 고집적화됨에 따라, 절연막을 식각장벽막으로 이용하는 자기정렬콘택(이하, SAC : Self Align Contact) 형성방법이 사용되고, 이는 마스크의 오정렬에 크게 영향을 받지 않으며, 항상 일정한 위치에 일정한 크기의 콘택홀을 얻을 수 있다.Recently, as the device is highly integrated, a method of forming a self alignment contact (SAC) using an insulating film as an etch barrier film is used. A contact hole can be obtained.
종래의 기술은 게이트 구조를 폴리/금속막 구조를 형성하기 위하여 게이트 절연막과 폴리실리콘막을 차례로 증착한 다음, 이온주입 공정을 통하여 N+폴리 또는 P+ 폴리를 형성한다.In the prior art, a gate insulating film and a polysilicon film are sequentially deposited to form a gate structure as a poly / metal film structure, and then an N + poly or P + poly is formed through an ion implantation process.
그 후 금속막을 증착하고 SAC 공정을 적용하기 위하여서는 산화막/질화막/산화막등을 순차적으로 증착한 후 패터닝을 실시한다. 이 때, 패터닝시에 층이 두꺼워지는 문제 때문에 폴리층을 두껍게 해 주기 어려워 이온주입시에 초저에너지(Ultra Low Energy) 이온주입을 실시하여야 하므로 최신 개발된 고가의 장비가 필요하여 소자의 특성도 공정에 매우 민감하게 변하게 된다.After that, in order to deposit a metal film and apply the SAC process, an oxide film / nitride film / oxide film is sequentially deposited and then patterned. At this time, due to the problem of thickening of the layer during patterning, it is difficult to thicken the poly layer. Therefore, ultra-low energy ion implantation should be performed during ion implantation. It becomes very sensitive to.
또한, 일반적인 반도체 공정에서 IPO(inter poly oxide) 이후에 금속막이 형성되는데 반해, 상기 SAC 공정에서는 게이트 절연막 공정 이후부터 금속막이 증착되게 되어 게이트 절연막의 GOI(Gate Oxide Integrity)등에 문제를 유발시킬 수 있다.In addition, in a general semiconductor process, a metal film is formed after an inter poly oxide (IPO), whereas in the SAC process, a metal film is deposited after the gate insulation process, which may cause problems such as gate oxide integrity (GOI) of the gate insulation layer. .
또한, 트랜지스터의 채널 영역에도 영향을 주어 소자 특성의 악화를 발생시킨다.It also affects the channel region of the transistor, causing deterioration of device characteristics.
따라서, IPO 공정에 의한 열공정 때문에 사용될 수 있는 금속막의 종류도한정적이며, 폴리와 금속막을 열공정에 의한 확산에 의하여 문제가 발생되지 않도록 분리시키면서 전기적으로는 작은 저항을 갖도록 중간층을 반드시 넣어야 한다.Therefore, the type of metal film that can be used due to the thermal process by the IPO process is also limited, and the intermediate layer must be inserted so as to have a small resistance electrically while separating the poly and the metal film so as not to cause a problem by diffusion by the thermal process.
그리고, 게이트 패턴 형성후 발생되는 플라즈마 데미지를 치유하기 위하여 재산화 공정이 반드시 필요한데, 이때 금속막이 존재함으로 인하여 많은 제약을 받아 열공정에 제약이 많이 발생하여 전류의 감소등 많은 문제가 발생한다. 따라서, 현재까지도 실질적인 트랜지스터의 형성이 어려워 제품에 적용되는 사례가 드물다.In addition, in order to heal the plasma damage generated after the gate pattern is formed, a reoxidation process is necessary. In this case, many problems occur such as a decrease in current due to a lot of constraints due to the presence of a metal film and a lot of limitations in the thermal process. Therefore, even in the present, practical transistor formation is difficult, so it is rarely applied to products.
따라서, 상기 목적을 달성하기 위한 본 발명은, IPO 공정 형성 후, 금속막을 접촉시킬 수 있는 반도체 소자의 게이트 제조방법을 제공하는 것이다.Accordingly, the present invention for achieving the above object is to provide a method for manufacturing a gate of a semiconductor device capable of contacting a metal film after the formation of the IPO process.
도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 게이트 제조방법을 설명하기 위한 제조공정도.1A to 1E are manufacturing process diagrams illustrating a method for manufacturing a gate of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체 기판 11 : 게이트 절연막10 semiconductor substrate 11 gate insulating film
12 : 게이트용 도전막 13 : 박막의 산화막12 gate conductive film 13 thin film oxide film
14 : 게이트용 희생막 20 : 게이트 패턴14: sacrificial film for the gate 20: gate pattern
21 : 소오스/드레인 영역 22 : 스페이서21: source / drain region 22: spacer
25 : 층간절연막 26 : 제1 홀25 interlayer insulating film 26 first hole
27 : 배리어막 28 : 금속막27 barrier film 28 metal film
30 : 제2 홀 31 : 캡핑질화막30: second hole 31: capping nitride film
32 : 버퍼용 산화 박막32: oxidized thin film for buffer
상기 목적을 달성하기 위한 본 발명은, 반도체 기판상에 불순물 이온 주입된 소정의 게이트용 도전막을 형성하는 단계; 상기 게이트용 도전막 상부에 식각 방지막을 증착하는 단계; 상기 식각 방지막 상부에 소정의 게이트용 게이트용 희생막을 증착하는 단계; 상기 게이트용 희생막, 식각 방지막 및 게이트용 도전막을 차례로 패터닝하여 게이트 패턴을 형성하는 단계; 상기 단계까지의 전체구조상에 층간절연막을 증착하고 상기 게이트용 희생막 표면이 노출되도록 연마하는 단계; 상기 게이트용 희생막을 제거한 다음 상기 식각방지막을 제거하여 제1 홀을 형성하는 단계; 상기 제1 홀상에 배리어 박막을 형성한 다음 금속막을 매립하는 단계; 상기 금속막 및 배리어 박막을 상기 층간절연막이 노출되도록 연마하는 단계; 상기 금속막 소정부분을 제거하여 제2 홀을 형성하는 단계; 및 상기 제2 홀상에 캡핑질화막을 매립하고, 상기 층간절연막이 노출되도록 연마하는 단계를 포함하여 구성하는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a predetermined conductive film for a gate implanted with impurity ions on a semiconductor substrate; Depositing an etch stop layer on the gate conductive layer; Depositing a predetermined gate sacrificial layer on the etch stop layer; Forming a gate pattern by sequentially patterning the gate sacrificial layer, the etch stop layer, and the gate conductive layer; Depositing an interlayer insulating film over the entire structure up to the step and polishing the exposed surface of the sacrificial film for the gate; Removing the gate sacrificial layer and then removing the etch stop layer to form a first hole; Forming a barrier thin film on the first hole and then filling a metal film; Polishing the metal film and the barrier thin film to expose the interlayer insulating film; Removing a predetermined portion of the metal film to form a second hole; And embedding a capping nitride film on the second hole and polishing the exposed interlayer insulating film.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 게이트 제조방법을 설명하기 위한 제조공정도이다.1A to 1E are manufacturing process diagrams illustrating a method of manufacturing a gate of a semiconductor device according to an exemplary embodiment of the present invention.
먼저, 도 1a에 도시된 바와같이, 반도체 기판(10) 상에 소자형성 영역을 한정하는 소자분리막(미도시)을 형성한다. 그 다음, 상기 반도체 기판(10)상에 게이트 절연막(11)을 증착한다. 이어서, 상기 게이트 절연막(11) 상부에 소정의 게이트용 도전막(12)을 증착한다. 이 때, 상기 게이트용 도전막(12)은 바람직하게 상기 게이트 절연막(11)상부에 도핑되지 않은 폴리실리콘막을 증착한 후, 불순물 이온주입된 도핑된 폴리실리콘막이다.First, as shown in FIG. 1A, an isolation layer (not shown) defining an element formation region is formed on the semiconductor substrate 10. Next, a gate insulating film 11 is deposited on the semiconductor substrate 10. Subsequently, a predetermined gate conductive film 12 is deposited on the gate insulating film 11. At this time, the gate conductive film 12 is preferably a doped polysilicon film implanted with impurity ions after depositing an undoped polysilicon film on the gate insulating film 11.
그 다음, 상기 게이트용 도전막(12) 상부에 박막의 산화막(13)을 증착한다. 이 때, 상기 박막의 산화막(13)은 식각 방지막 역할을 수행한다. 그 다음, 상기 박막의 산화막(13) 상부에 소정 두께를 갖는 게이트용 희생막(14)을 증착한다. 이 때, 상기 게이트용 희생막(14)은 바람직하게 도핑되지 않은 폴리실리콘막으로 구성된다. 이어서, 상기 게이트용 희생막(14), 박막의 산화막(13), 게이트용 도전막(12) 및 게이트 절연막(11)을 차례로 식각하여 게이트 패턴(20)을 형성한다.Next, a thin film oxide film 13 is deposited on the gate conductive film 12. At this time, the oxide layer 13 of the thin film serves as an etch stop layer. Next, a gate sacrificial layer 14 having a predetermined thickness is deposited on the oxide layer 13 of the thin film. In this case, the gate sacrificial film 14 is preferably composed of a undoped polysilicon film. Subsequently, the gate sacrificial layer 14, the thin oxide layer 13, the gate conductive layer 12, and the gate insulating layer 11 are sequentially etched to form a gate pattern 20.
그 다음, 도 1b에 도시된 바와같이, 상기 게이트 패턴이 형성된 결과물상에 LDD(lightly doped drain) 구조를 갖는 소오스/드레인 영역(21)을 형성한다. 여기서, 상기 LDD 구조를 갖는 소오스/드레인 영영(21)은 상기 게이트 패턴 양측의 반도체 기판에 저농도 이온주입을 실시한 다음, 상기 게이트 패턴(20) 양측벽에 스페이서(22)를 형성하고, 상기 스페이서(22) 양측의 반도체 기판(10)에 고농도 이온주입을 실시함으로써 형성된다.Next, as shown in FIG. 1B, a source / drain region 21 having a lightly doped drain (LDD) structure is formed on the resultant product on which the gate pattern is formed. Here, the source / drain region 21 having the LDD structure is subjected to low concentration ion implantation into semiconductor substrates on both sides of the gate pattern, and then forms spacers 22 on both sidewalls of the gate pattern 20. 22) It is formed by implanting high concentration ions into the semiconductor substrate 10 on both sides.
그 다음, 도 1c에 도시된 바와같이, 상기 단계까지의 결과물 상에 층간절연막(25)을 형성한다. 상기 층간절연막(25)은 바람직하게 HTO 또는 BPSG막 등의 IPO(inter poly oxide)막으로 형성된다. 이어서, 상기 층간절연막(25)을 화학기계연마(CMP)하여 상기 게이트용 희생막(14)을 노출시킨다.Then, as shown in Fig. 1C, an interlayer insulating film 25 is formed on the resultant up to this step. The interlayer insulating film 25 is preferably formed of an inter poly oxide (IPO) film such as an HTO or BPSG film. Subsequently, the interlayer insulating layer 25 is subjected to chemical mechanical polishing (CMP) to expose the gate sacrificial layer 14.
그 다음, 도 1d에 도시된 바와같이, 상기 게이트용 희생막(14)을 블랭킷 식각으로 제거한 다음, 이어서, 상기 박막의 산화막(13)을 제거하여 제1 홀(26)을 형성한다. 그 다음, 상기 제1 홀(26)상에 배리어막(27)을 증착하고 이어서, 금속막(28)을 매립한다. 이 때, 본 발명의 실시예에서는 상기 배리어막(27)을 바람직하게 Ti/TiN막의 적층구조 형성하고, 상기 금속막(28)을 텅스텐막으로 형성한다. 그 다음, 상기 금속막(28)과 배리어막(27)을 연마하여 상기 층간절연막(25)을 노출시킨다.Next, as shown in FIG. 1D, the gate sacrificial layer 14 is removed by blanket etching, and then the oxide layer 13 of the thin film is removed to form the first hole 26. Next, a barrier film 27 is deposited on the first hole 26, and then a metal film 28 is buried. At this time, in the embodiment of the present invention, the barrier film 27 is preferably formed of a stacked structure of a Ti / TiN film, and the metal film 28 is formed of a tungsten film. Next, the metal film 28 and the barrier film 27 are polished to expose the interlayer insulating film 25.
그 다음, 도 1e에 도시된 바와같이, 상기 금속막(28)을 소정부분 제거하여 제2 홀(30)을 형성한다. 그 다음, 상기 제2 홀(30)상에 캡핑질화막(31)을 매립한 다음, 상기 캡핑질화막(31)을 연마하여 층간절연막(25)을 노출시킨다. 이어서, 상기 결과물 전면상에 버퍼용 산화 박막(32)을 증착한다.Next, as shown in FIG. 1E, a predetermined portion of the metal film 28 is removed to form the second hole 30. Then, the capping nitride film 31 is buried in the second hole 30, and then the capping nitride film 31 is polished to expose the interlayer insulating film 25. Subsequently, an oxide thin film 32 for buffer is deposited on the entire surface of the resultant product.
이후, 도시하지 않았지만, 상기 층간절연막을 제거하면서 자기정렬콘택 공정을 실시한다.Subsequently, although not shown, a self-aligning contact process is performed while removing the interlayer insulating film.
상술한 실시예에서는 상기 금속막을 텅스텐막으로 형성한 다음 CMP 공정을 실시하여 연마하였지만, 상기 금속막을 알루미늄막이면 플로우(flow)가 가능하므로 CMP 공정대신 에치 백 공정을 사용할 수 있다.In the above-described embodiment, the metal film is formed of a tungsten film and then polished by performing a CMP process. However, if the metal film is an aluminum film, flow is possible, and thus an etch back process may be used instead of the CMP process.
상기한 바와같은 반도체 소자의 게이트 제조방법은 다음과 같은 효과가 있다.The gate manufacturing method of the semiconductor device as described above has the following effects.
본 발명에 따른 반도체 소자의 게이트 제조방법은 층간절연막 공정 형성 후 금속막을 형성함으로써, 금속막과 반도체와의 반응에 의한 부작용들이 완전히 없어지면서 SAC 공정을 수행할 수 있는 폴리/금속막 게이트를 형성할 수 있다.In the method of manufacturing a gate of a semiconductor device according to the present invention, a metal film is formed after the formation of an interlayer insulating film process, thereby forming a poly / metal film gate capable of performing a SAC process while completely eliminating side effects due to the reaction between the metal film and the semiconductor. Can be.
또한, 기존 장비를 통하여 본 발명을 형성할 수 있으므로, 신기술에 대한 제조 단가를 감소시킬 수 있고, 게이트 저항의 감소에 의한 칩 크기의 감소가 가능하다.In addition, since the present invention can be formed through existing equipment, the manufacturing cost for the new technology can be reduced, and the chip size can be reduced by reducing the gate resistance.
기타, 본 발명의 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시할 수 있다.In addition, it can implement in various changes within the range which does not deviate from the summary of this invention.
Claims (6)
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