KR100210853B1 - Conducting line of semiconductor device and method of manufacturing the same - Google Patents
Conducting line of semiconductor device and method of manufacturing the same Download PDFInfo
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- KR100210853B1 KR100210853B1 KR1019960033874A KR19960033874A KR100210853B1 KR 100210853 B1 KR100210853 B1 KR 100210853B1 KR 1019960033874 A KR1019960033874 A KR 1019960033874A KR 19960033874 A KR19960033874 A KR 19960033874A KR 100210853 B1 KR100210853 B1 KR 100210853B1
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- film
- silicide
- silicon
- semiconductor device
- oxidation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 43
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 41
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
- 230000002401 inhibitory effect Effects 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 49
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 8
- 239000003112 inhibitor Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 27
- 229920005591 polysilicon Polymers 0.000 description 27
- 239000010410 layer Substances 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000010937 tungsten Substances 0.000 description 10
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 238000009413 insulation Methods 0.000 description 7
- 238000001459 lithography Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 229910001930 tungsten oxide Inorganic materials 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 239000003963 antioxidant agent Substances 0.000 description 2
- 230000003078 antioxidant effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 2
- VVRQVWSVLMGPRN-UHFFFAOYSA-N oxotungsten Chemical class [W]=O VVRQVWSVLMGPRN-UHFFFAOYSA-N 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 239000005046 Chlorosilane Substances 0.000 description 1
- OCJDVBMRRGKEBU-UHFFFAOYSA-N [W][Si][W] Chemical compound [W][Si][W] OCJDVBMRRGKEBU-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 실리사이드막을 포함하는 반도체 소자의 전도선 및 그 제조방법에 관한 것으로써, 실리사이드막의 측면과 상면에 실리사이드의 금속성분의 산화를 억제하는 산화억제막이 형성된 것을 특징으로 하는 전도선 구조와, 기판 상의 절연막 위에 소정 전도체막과 제1실리사이드막의 적층막을 형성하는 공정과, 적층막을 부분 선택적으로 식각하여 원하는 전도선 형태의 도선패턴을 형성하는 공정과, 도선패턴이 형성된 절연막 상에 제1실리사이드막의 금속성분의 산화를 억제하는 산화억제막을 형성하는 공정과, 산화억제막을 부분 선택적으로 식각하여 도선패턴의 측면과 상면 외 부위를 제거하고 도선패턴의 측면과 상면에 산화억제막이 남도록 하는 공정을 포함하여 이루어진 제조방법이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductive line of a semiconductor device including a silicide film and a method of manufacturing the same, wherein an oxide suppressing film is formed on the side and top surfaces of the silicide film to inhibit oxidation of the metal component of the silicide film. Forming a laminated film of a predetermined conductor film and a first silicide film on the insulating film on the upper surface; forming a conductive pattern in the form of a desired conductive line by partially etching the laminated film; and forming a metal of the first silicide film on the insulating film on which the Forming an oxidation inhibiting film that inhibits oxidation of the component; and removing the side and top portions of the lead pattern by selectively etching the oxidation inhibiting film, and leaving the oxidation inhibitor film on the side and the top surface of the lead pattern. It is a manufacturing method.
Description
제1도는 일반적인 반도체 소자 일부의 레이아웃(Layout)도.1 is a layout diagram of a part of a general semiconductor device.
제2도는 종래의 반도체 소자의 전도선을 설명하기 위해 전도선으로 비트라인을 예로 하여 반도체 소자 일부를 도시한 도면으로써, 제1도의 A-A'선에 따른 단면도.FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1 to illustrate a portion of a semiconductor device using a bit line as an example of a conductive line to explain a conductive line of a conventional semiconductor device.
제3도는 종래의 반도체 소자의 전도선을 설명하기 위해 전도선으로 비트라인을 예로 하여 반도체 소자 일부를 도시한 도면으로써, 제1도의 B-B'선에 다른 단면도.3 is a cross-sectional view of a portion of a semiconductor device with a bit line as an example of a conductive line for explaining a conductive line of a conventional semiconductor device, which is different from the line B-B 'of FIG.
제4도는 본 발명의 반도체 소자의 전도선을 갖는 반도체 소자의 일부단면도로써, 제1도의 a-A'선에 따른 단면도.4 is a partial cross-sectional view of a semiconductor device having conductive lines of the semiconductor device of the present invention, and is a cross-sectional view taken along line a-A 'in FIG.
제5도는 본 발명의 반도체 소자의 전도선을 갖는 반도체 소자의 일부 단면도로써, 제1도의 B-B'선에 따른 단면도이다.5 is a partial cross-sectional view of a semiconductor device having conductive lines of the semiconductor device of the present invention, and is a cross-sectional view taken along the line BB ′ of FIG. 1.
제6도는 본 발명의 반도체 소자의 전도선 제조방법을 설명하기 위해 반도체 소자의 일부를 도시한 단면도로써, 제1도의 B-B'선 방향으로 절단한 공정단면도.6 is a cross-sectional view showing a portion of a semiconductor device for explaining the method of manufacturing a conductive line of the semiconductor device of the present invention, a process cross-sectional view taken in the line B-B 'of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10,20 : 실리콘기판 11,21,22' : 폴리실리콘막10,20: Silicon substrate 11,21,22 ': Polysilicon film
12 : 텅스텐실리사이드막 22,22' : 제1텅스텐실리사이드막12: tungsten silicide film 22,22 ': first tungsten silicide film
23,23' : 산화억제막 14,24 : 트랜지스터23,23 ': oxidation inhibiting film 14,24: transistor
15,25' : 절연층15,25 ': insulation layer
본 발명은 반도체 소자의 전도선 및 그 제조방법에 관한 것으로써, 특히 라인(line) 저항을 감소시켜 소자의 동작특성 향상에 적당하도록 한 전도선 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductive line of a semiconductor device and a method of manufacturing the same, and more particularly, to a conductive line and a method of manufacturing the same, which reduce line resistance and are suitable for improving operating characteristics of the device.
반도체 소자의 집적도가 커지면서 임계치수(CD; Critical Dimension)가 감소하고 그에 따라 전도선의 선폭이 작아지고 있으므로, 같은 비저항을 갖는 재료를 사용할 경우에 전도선의 저항이 커지게 되어 고집적소자의 동작속도가 감소된다. 따라서 비트라인(Bit line) 등과 같이 반도체 소자의 전도선에 실리콘과 실리사이드로 된 적층막을 사용하는 것은, 라인 저항을 감소시켜 소자의 동작특성(비트라인의 경우에 예컨데 데이터전송속도)을 좋게 하기 위한 것이다.As the integration of semiconductor devices increases, the critical dimension (CD) decreases and the line width of the conductive wires decreases. Therefore, when the material having the same resistivity is used, the resistance of the conductive wires increases, thereby reducing the operation speed of the highly integrated device. do. Therefore, the use of a laminated film made of silicon and silicide as a conductive line of a semiconductor device, such as a bit line, is intended to reduce the line resistance to improve the operation characteristics of the device (e.g., data transfer rate in the case of a bit line). will be.
제1도는 일반적인 반도체 소자 일부의 레이아웃(Layout)도이다.1 is a layout view of a part of a general semiconductor device.
제2도 내지 제3도는 종래의 반도체 소자의 전도선을 설명하기 위해 전도선으로 비트라인을 예로 하여 반도체 소자 일부를 도시한 도면으로써, 제2도는 제1도의 A-A'선에 따른 단면도이고, 제3도는 제1도의 B-B'선에 다른 단면도이다.2 to 3 are views illustrating a part of a semiconductor device using a bit line as an example of a conductive line to explain the conductive line of a conventional semiconductor device. FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1. 3 is another cross-sectional view taken along the line BB ′ of FIG. 1.
제2도와 제3도에 도시한 바와 같이, 종래의 반도체 소자의 전도선인 비트라인은 폴리실리콘막(11)과 텅스텐실리사이드(WSix)(12)의 적층막으로 구성되어 있다. 이 적층막의 비트라인은 트랜지스터(14)의 게이트와 절연을위해 형성된 절연층(15) 위에 형성되고, 절연층(15)에 형성된 접속홀을 통하여 트랜지스터(14)의 드레인영역에 접속되어 있다.As shown in FIG. 2 and FIG. 3, the bit line which is the conducting line of the conventional semiconductor element is comprised by the laminated film of the polysilicon film 11 and tungsten silicide (WSi x ) 12. The bit line of this laminated film is formed on the insulating layer 15 formed for insulation with the gate of the transistor 14, and is connected to the drain region of the transistor 14 through a connection hole formed in the insulating layer 15.
이와같이 실리사이드막을 반도체소자의 전도선에 적용할 경우에, 실리사이드의 금속성분에 대한 실리콘 조성비에 의해 전도선의 저항이 달라지게 된다. 즉 텅스텐실리사이드(WSix)(12)에서 텅스텐(W)에 대한 실리콘(Si) 조성비인 (x)가 낮을수록 실리사이드의 비저항이 낮아지게 된다. 그러나 조성비(x)가 너무 낮으면 층간절연을 위해 전도선 위 즉, 텅스텐실리사이드(12) 위에 절연층(도시안함)인 실리콘산화막(SiO2)을 증착하는 단계에서 텅스텐실리사이드(WSix) 표면의 실리콘(Si)이 부족하게 되어 텅스텐옥사이드(예컨대, WO2, WO3)가 실리콘산화막(SiO2)과 같이 생성된다. 따라서 상술한 종래의 구조로는 텅스텐실리사이드의 텅스텐에 대한 실리콘의 조성비(x)가 2.5 이상이 되도록 하고 있다.When the silicide film is applied to the conductive line of the semiconductor device as described above, the resistance of the conductive line varies depending on the silicon composition ratio of the silicide metal. That is, the lower the resistivity of silicide, the lower the ratio (x) of silicon (Si) to tungsten (W) in tungsten silicide (WSi x ) 12. However, if the composition ratio (x) is too low, the surface of the tungsten silicide (WSi x ) surface is deposited in the step of depositing a silicon oxide film (SiO 2 ), which is an insulating layer (not shown), on the conductive line, that is, on the tungsten silicide 12 for interlayer insulation. Lack of silicon (Si) causes tungsten oxides (eg, WO 2 , WO 3 ) to be produced like silicon oxide (SiO 2 ). Therefore, in the conventional structure described above, the composition ratio (x) of silicon to tungsten of tungsten silicide is set to be 2.5 or more.
또한 상술한 구조를 갖는 종래의 전도선인 비트라인의 제조방법은, 제2도와 제3도에서와 같이, 우선 실리콘기판(10)에 일반적인 방법으로 트랜지스터(14)를 형성한 다음, 트랜지스터가 형성된 기판(10)에 절연층(15)인 실리콘산화막을 형성하고, 리소그래피 단계를 적용하여 절연층(15)에 접속홀을 형성한다. 이 접속홀은 이미 언급한 바와 같이 트랜지스터(14)의 드레인 영역 부위와 비트라인과의 접속을 위한 것이다. 이어서 전면에 폴리실리콘막(11)을 증착한다. 이때 증착과 동시에 PH3가스를 이용하여 1019내지 1021atoms/cm3정도의 'P' 원자를 인시튜(in-situ) 도핑하여 폴리실리콘막(11)의 저항을 낮춘다. 다음에 폴리실리콘막(11) 표면의 자연산화막(SiO2)을 제거하기 위하여 세정을 실시한 후, 텅스텐실리사이드(WSix)막(12)을 폴리실리콘막(11) 위에 증착한다. 텅스텐실리사이드(WSix)의 텅스텐에 대한 실리콘의 조성비(x)는 공정조건에 따라 바뀌며, 이미 언급한 바와 같이, 증착 직후의 조성비(x)를 약 2.5 이상으로 하고 있다. 그후, 텅스텐실리사이드막(12)의 결정구조를 안정화시키고 저항을 낮추기 위해 약 600℃ 이상의 온도에서 열처리(Anneal)한다. 이어서, 리소그래피 단계를 적용하여, 즉 포토레지스트마스크패턴(도시안함)을 텅스텐실리사이드막(12) 위에 형성하고 포토레지스트마스크패턴을 마스크로하여 텅스텐실리사이드막(12)과 폴리실리콘막(11)을 식각하여 비트라인을 형성한다.In the conventional method for manufacturing a bit line, which has the above-described structure, as shown in FIGS. 2 and 3, first, the transistor 14 is formed on the silicon substrate 10 by a general method, and then the substrate on which the transistor is formed. A silicon oxide film, which is the insulating layer 15, is formed on 10, and a connection hole is formed in the insulating layer 15 by applying a lithography step. This connection hole is for connection between the drain region portion of the transistor 14 and the bit line as already mentioned. Subsequently, a polysilicon film 11 is deposited on the entire surface. At the same time, the resistance of the polysilicon film 11 is lowered by in-situ doping of 'P' atoms of about 10 19 to 10 21 atoms / cm 3 using PH 3 gas simultaneously with the deposition. Next, after the washing is performed to remove the native oxide film (SiO 2 ) on the surface of the polysilicon film 11, a tungsten silicide (WSi x ) film 12 is deposited on the polysilicon film 11. The composition ratio (x) of silicon to tungsten of tungsten silicide (WSi x ) changes depending on the process conditions, and as mentioned above, the composition ratio (x) just after deposition is about 2.5 or more. Thereafter, heat treatment is performed at a temperature of about 600 ° C. or higher to stabilize the crystal structure of the tungsten silicide film 12 and lower the resistance. Then, the lithography step is applied, that is, a photoresist mask pattern (not shown) is formed on the tungsten silicide film 12 and the tungsten silicide film 12 and the polysilicon film 11 are etched using the photoresist mask pattern as a mask. To form a bit line.
상술한 바와 같이 종래의 폴리실리콘막(11)과 그 위에 형성된 텅스텐실리사이드막(WSix)(12)으로 된 전도선의 구조로는, 텅스텐실리사이드막(WSix)의 금속성분(W)에 대한 실리콘(Si)의 조성비(x)를 약 2.5 이상으로 해야 하는 제약이 따르게 된다. 종래의 전도선 구조에서 텅스텐실리사이드막의 금속성분에 대한 실리콘의 조성비를 약 2.4 이하로 할 경우에는, 텅스텐실리사이드막 위에 절연을 위한 실리콘산화막(SiO2)를 형성할 때 텅스텐실리사이드 표면의 실리콘(Si)이 부족하게 되어 텅스텐옥사이드(WO2, WO3)가 생성된다. 이 텅스텐옥사이드는 실리콘산화막(SiO2)와 같이 치밀하지 못하고 접착력도 좋지 않기 때문에, 그 표면에 텅스텐옥사이드(WO2, WO3)와 같은 이상산화막을 형성하게 되어 웨이퍼 전체에 대한 치명적인 불량을 유발하게 된다. 이와 같이, 종래의 전도선의 구조로는 전도선의 저항을 낮추는데 한계가 있고, 결국 미세치수의 고집적소자에 적합하지 못하게 된다.As described above, in the structure of the conductive line made of the conventional polysilicon film 11 and the tungsten silicide film (WSi x ) 12 formed thereon, the silicon to the metal component (W) of the tungsten silicide film (WSi x ) There is a restriction that the composition ratio (x) of (Si) should be about 2.5 or more. When the composition ratio of silicon to the metal component of the tungsten silicide film is about 2.4 or less in the conventional conductive wire structure, when forming a silicon oxide film (SiO 2 ) for insulation on the tungsten silicide film, silicon (Si) on the surface of the tungsten silicide film is formed. This shortage produces tungsten oxides (WO 2 , WO 3 ). Since the tungsten oxide is not as dense as the silicon oxide film (SiO 2 ) and the adhesion is not good, an abnormal oxide film such as tungsten oxide (WO 2 , WO 3 ) is formed on the surface thereof, which causes a fatal defect for the entire wafer. do. As such, the structure of the conventional conductive line has a limit in lowering the resistance of the conductive line, and thus, it is not suitable for the high-integration device having a fine dimension.
본 발명은 종래의 전도선의 문제점을 개선하기 위한 것으로써, 저항을 최소화하여 고집적소자에 적합한 전도선의 구조 및 그 제조방법을 제공하고자 한다.The present invention is to improve the problems of the conventional conductive wire, to minimize the resistance to provide a structure of the conductive wire suitable for the high integration device and a method of manufacturing the same.
상술한 목적을 달성하기 위한 본 발명은 실리사이드막을 포함하는 반도체 소자의 전도선으로써, 실리사이드막의 측면과 상면에 실리사이드의 금속성분의 산화를 억제하는 산화억제막이 형성된 것을 특징으로 한다. 여기서, 전도선은 실리콘막과 실리콘막 위의 실리사이드막으로 된 적층막이다. 산화억제막은 실리사이드막의 금속성분에 대한 실리콘 조성비보다 실리콘 조성비가 높은 실리사이드이며, 이때, 산화억제막은 실리콘막 측면까지 연장 형성된다.The present invention for achieving the above object is characterized in that, as a conductive line of a semiconductor device including a silicide film, an oxidation inhibiting film is formed on the side and top of the silicide film to suppress oxidation of the metal component of the silicide. Here, the conductive line is a laminated film made of a silicon film and a silicide film on the silicon film. The oxidation inhibiting film is a silicide having a higher silicon composition ratio than the silicon composition ratio with respect to the metal component of the silicide film. In this case, the oxidation inhibiting film extends to the side of the silicon film.
다른 산화억제막으로는, 실리콘막 또는 실리콘질화막이 적용된다.As another oxidation inhibiting film, a silicon film or a silicon nitride film is applied.
또한, 본 발명의 반도체 소자의 전도선 제조방법은, 기판 상의 절연막 위에 소정 전도체막과 제1실리사이드막의 적층막을 형성하는 공정과, 적층막을 부분 선택적으로 식각하여 원하는 전도선 형태의 도선패턴을 형성하는 공정과, 도선패턴이 형성된 절연막 상에 제1실리사이드막의 금속성분의 산화를 억제하는 산화억제막을 형성하는 공정과, 산화억제막을 부분 선택적으로 식각하여 도선패턴의 측면과 상면 외 부위를 제거하고 도선패턴의 측면과 상면에 산화억제막이 남도록 하는 공정을 포함하여 이루어진다. 여기서, 산화억제막의 형성은, 제1실리사이드막의 금속성분에 대한 실리콘의 조성비보다 금속성분에 대한 실리콘 조성비가 큰 제2실리사이드막으로 형성하며, 이때, 제1 및 제2실리사이드는 텅스텐실리사이드이다. 다른 산화억제막 형성의 예로는 실리콘막, 또는 실리콘지로하막을 형성한다. 여기서, 절연막은 접속홀이 형성되어 있고, 적층막의 전도체막이 접속홀을 통하여 기판의 소정전도영역에 접속된 것이 특징이다. 소정 전도체막은 실리콘막인 것이 특징이다.In addition, the method of manufacturing a conductive line of a semiconductor device of the present invention comprises the steps of forming a laminated film of a predetermined conductor film and a first silicide film on an insulating film on a substrate, and selectively etching the laminated film to form a conductive pattern in the form of a desired conductive line. And forming an oxidation inhibiting film that inhibits oxidation of the metal component of the first silicide film on the insulating film on which the conducting wire pattern is formed, and selectively etching the oxidation inhibiting film to remove the side surface and the outside of the upper surface of the conducting pattern, And a step of leaving an oxidation inhibiting film on the side and the top surface thereof. Here, the oxidation inhibiting film is formed of a second silicide film having a silicon composition ratio with respect to the metal component larger than that of silicon with respect to the metal component of the first silicide film, wherein the first and second silicides are tungsten silicide. As another example of the formation of the oxidation inhibiting film, a silicon film or a silicon sublayer film is formed. Here, the insulating film has a connection hole, and the conductor film of the laminated film is connected to the predetermined conductive region of the substrate through the connection hole. The predetermined conductor film is characterized by being a silicon film.
첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 아래에 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
제4e 내지 제6도는 전도선의 예로 비트라인(Bit Line)을 들어 본 발명의 반도체 소자의 전도선 및 그 제조방법을 설명하기 이해 도시한 도면이다.4E to 6 are diagrams for explaining a conductive line and a manufacturing method of the semiconductor device of the present invention by taking a bit line as an example of the conductive line.
제4도와 제5도는 본 발명의 반도체 소자의 전도선을 갖는 반도체 소자의 일부 단면도로써, 제4도는 제1도의 A-A'선에 따른 단면도이고, 제5도는 제1도의 B-B'선에 따른 단면도이다.4 and 5 are partial cross-sectional views of a semiconductor device having conductive lines of the semiconductor device of the present invention. FIG. 4 is a cross-sectional view taken along a line A-A 'of FIG. 1, and FIG. 5 is a line B-B' of FIG. In accordance with the cross-sectional view.
제4도 및 제5도는 본 발명의 반도체 소자의 전도선은, 하부에 폴리실리콘(Poly-Silicon)막(21')이 있고 그 위에 텅스텐(W)에 대한 실리콘(Si)의 조성비가 약 2.4 이하인 제1텅스텐실리사이드(WSix:X는 약 2.4 이하) 막(22')이 있는 적층막과, 적층막의 측면과 상면에 텅스텐실리사이드(WSix)의 금속성분(W)의 산화를 억제하는 산화억제막(23'), 예로성 텅스텐(W)에 대한 실리콘(Si)의 조성비가 약 2.5 내지 3.7 정도인 제2텅스텐실리사이드(WSix:X는 약 2.5 이상)막이 형성된 것이다. 이때, 제1텅스텐실리사이드막(21')은 최종적으로 원하는 실리사이드막의 50% 내지 90% 정도의 두께와 선폭을 갖고, 산화억제막(23')인 제2텅스텐실리사이드가 그 나머지를 채우게 된다.4 and 5 show that the conductive line of the semiconductor device of the present invention has a polysilicon film 21 'at the bottom thereof and a composition ratio of silicon (Si) to tungsten (W) on the bottom thereof. A lamination film having a first tungsten silicide (WSi x : X is about 2.4 or less) film 22 'and an oxide for inhibiting oxidation of the metal component (W) of tungsten silicide (WSi x ) on the side and top surfaces of the lamination film. A second tungsten silicide (WSi x : X is about 2.5 or more) film having a composition ratio of silicon (Si) to the suppression film 23 ', for example, tungsten (W), is about 2.5 to 3.7. At this time, the first tungsten silicide film 21 'has a thickness and a line width of about 50% to 90% of the desired silicide film, and the second tungsten silicide as the oxidation inhibiting film 23' fills the rest.
본 발명의 전도선인 비트라인은 제4도에 도시한 바와 같이, 기판(20)에 형성된 트랜지스터(24)의 드레인영역에 접속되는데, 트랜지스터의 게이트와 절연을 위해 형성된 절연층(25') 위에 형성되고, 절연층(25')에 형성된 접속홀을 통하여 트랜지스터(24)의 드레인영역에 접속된다.The bit line, which is the conductive line of the present invention, is connected to the drain region of the transistor 24 formed in the substrate 20, as shown in FIG. 4, and is formed on the insulating layer 25 'formed to insulate the gate of the transistor. It is connected to the drain region of the transistor 24 through the connection hole formed in the insulating layer 25 '.
이렇게 텅스텐에 대한 실리콘의 조성비가 2.4 이하 정도로 낮은 제1텅스텐실리사이드막(22')를 사용하고 제1텅스텐실리사이드막(22')의 표면을 산화억제막(23')인, 텅스텐에 대한 실리콘의 조성비가 2.5 이상인 제2텅스텐실리사이드막이 덮도록 형성하면, 제2텅스텐실리사이드막은 실리콘을 충분히 함유하므로써 차후 층간절연을 위해 그 위에 실리콘산화막을 증착시킬 때 실리사이드 표면의 이상산화현상 즉 WO2또는 WO3등이 생성되는 것을 방지할 수 있게 된다. 또한, 제4e 및 제5도에서 알 수 있는 바와 같이 산하억제막(23')을 텅스텐실리사이드막으로 할 경우에는, 전도선의 하부에 위치하는 폴리실리콘막(22')의 측면에도 제2텅스텐실리사이드가 덮어 있으므로써 전도선의 저항을 더욱 감소시킬 수 있다. 본 발명의 전도선에 사용되는 실리사이드를 텅스텐실리사이드에 국한되지 않고, 타이타늄실리사이드 또는 코발트실리사이드에도 적용된다.The silicon-tungsten-to-tungsten film of the silicon-tungsten-tungsten film, which is composed of the first tungsten silicide film 22 'having a low composition ratio of silicon to tungsten of about 2.4 or less, is formed on the surface of the first tungsten silicide film 22'. When the second tungsten silicide film having a composition ratio of 2.5 or more is formed to cover the second tungsten silicide film, the second tungsten silicide film sufficiently contains silicon, so that when the silicon oxide film is deposited thereon for interlayer insulation, an ideal oxidation phenomenon of the silicide surface, that is, WO 2 or WO 3, etc. This can be prevented from being generated. In addition, as shown in FIGS. 4E and 5, when the acid suppression film 23 'is a tungsten silicide film, the second tungsten silicide is also formed on the side surface of the polysilicon film 22' positioned below the conductive line. By covering it, the resistance of the conductor can be further reduced. The silicide used in the conductive line of the present invention is not limited to tungsten silicide but also applies to titanium silicide or cobalt silicide.
산화억제막(23)의 다른 예(도시안함)로는 폴리실리콘막과, 실리콘질화막이 각각 적용될 수 ldT다. 폴리실리콘막의 경우에는 차후 절연을 위한 실리콘산화막의 증착시에 폴리실리콘막이 실리콘(Si) 소오스(Source)가 되어 그 내부에 위치하는 실리콘을 적게 함유한 텅스텐실리사이드의 이상산화를 방지하게 된다. 산화방지막으로 널리 사용되고 있는 실리콘질화막을 산화억제막으로 적용할 경우에는 실리콘질화막이 약 50내지 100정도가 되도록 형성하여 산소원자의 확산을 방지하게 된다.Another example of the oxidation inhibiting film 23 (not shown) is a polysilicon film and a silicon nitride film ldT, respectively. In the case of the polysilicon film, the polysilicon film becomes a silicon (Si) source during deposition of the silicon oxide film for subsequent insulation to prevent abnormal oxidation of tungsten silicide containing less silicon located therein. When the silicon nitride film, which is widely used as an antioxidant film, is applied as an oxidation inhibiting film, the silicon nitride film is about 50 To 100 It is formed to a degree to prevent the diffusion of oxygen atoms.
제6도는 본 발명의 반도체 소자의 전도선 제조방법을 설명하기 위해 반도체 소자의 일부 단면을 도시한 공정단면도이다.6 is a process cross-sectional view showing a partial cross section of the semiconductor device in order to explain the method for manufacturing a conductive line of the semiconductor device of the present invention.
제6도는 제1도의 B-B'선 방향으로 절단한 공정단면도이다.6 is a cross-sectional view taken along the line BB ′ of FIG. 1.
본 발명의 반도체 소자의 전도선 제조방법은, 제6도의 (a)와 같이 우선 실리콘기판에 일반적인 방법으로 트랜지스터(제4도 참조)를 형성한 다음, 트랜지스터가 형성한 기판(20)에 실리콘산화막으로 절연층을 형성한다. 이후, 리소그래피단계를 적용하여 절연층(25')에 접속홀(제4도 참조)을 형성한다. 리소그래피 단계(도시안함)에 대해 구체적으로 설명하면, 절연층 위에 포토레지스트막을 형성한 다음, 접속홀 패턴이 형성된 마스크를 포토레지스트 위에 위치시키고 포토레지스트막을 노광 및 현상하여 포토레지스트 마스크패턴을 형성한 뒤, 포토레지스트 마스크패턴을 마스크로 하여 실리콘산화막인 절연층을 식각하는 것이다. 이 접속홀은 이미 언급한 바와 같이 트랜지스터의 드레인영역 부위와 비트라인인 본 발명의 전도선과의 접속을 위한 것이다.In the method of manufacturing a conductive line of the semiconductor device of the present invention, as shown in FIG. 6A, first, a transistor (see FIG. 4) is formed on a silicon substrate in a general manner, and then a silicon oxide film is formed on the substrate 20 formed by the transistor. To form an insulating layer. Thereafter, a lithography step is applied to form a connection hole (see FIG. 4) in the insulating layer 25 '. The lithography step (not shown) is described in detail. After forming a photoresist film on the insulating layer, the mask having the connection hole pattern formed thereon is placed on the photoresist, and the photoresist film is exposed and developed to form a photoresist mask pattern. The insulating layer which is a silicon oxide film is etched using the photoresist mask pattern as a mask. This connection hole is for connection between the drain region portion of the transistor and the conductive line of the present invention, which is a bit line, as mentioned above.
이어서, 제6도의 (b)와 같이 접속홀이 형성된 절연층(25') 전면에 폴리실리콘막(21)을 증착한다. 이 폴리실리콘막(21)은 절연층(25')에 형성된 접속홀을 통해 기판(20)의 드레인영역(제6도에서는 안보임)에 접속된다. 이때, 종래와 마찬가지로 폴리실리콘막(21)의 증착과 동시에 PH3가스를 이용하여 1019내지 1021atoms/cm3정도의 농도로 'P'원자를 인시튜(in-situ) 도핑하여 폴리실리콘막(21)의 저항을 낮춘다.Subsequently, as shown in FIG. 6B, the polysilicon film 21 is deposited on the entire surface of the insulating layer 25 ′ in which the connection holes are formed. The polysilicon film 21 is connected to the drain region (not shown in FIG. 6) of the substrate 20 through a connection hole formed in the insulating layer 25 '. At this time, the polysilicon is doped in-situ at the concentration of 10 19 to 10 21 atoms / cm 3 at the same time using the PH 3 gas simultaneously with the deposition of the polysilicon film 21 as in the prior art. The resistance of the film 21 is lowered.
다음에 폴리실리콘막(21) 표면의 자연산화막(SiO2)을 제거하기 위하여 세정을 실시한 후, 제6도의 (c)와 같이 제1텅스텐실리사이드(WSix)막(22)을 폴리실리콘막(21) 위에 증착한다. 이때, 제1텅스텐실리사이드(WSix)막(22)의 텅스텐에 대한 실리콘의 조성비(x)는 약 2.4 이하로 최대한 낮게 설정하여 저항을 최소화하도록 한다. 그 증착방법은 WF6가스를 SiH4또는 SiH2치3(DCS; Di Chloro silane) 가스로 환원하여 증착하는 것이며, 증착직후의 텅스텐에 대한 실리콘이 조성비(x)는 WF6가스와 이들 환원용 가스의 유량비로 조절 가능하다. 또한 제1텅스텐실리사이드막(22)의 두께는 원하는 최종 실리사이드막 두께의 약 50% 내지 90% 정도로 형성한다. 그 후, 제1텅스텐실리사이드막(22)의 결정구조를 안정화시키고 저항을 낮추기 위해 약 600℃ 이상의 온도에서 열처리(Anneal)한다.Next, after washing to remove the native oxide film (SiO 2 ) on the surface of the polysilicon film 21, the first tungsten silicide (WSi x ) film 22 is replaced with the polysilicon film ((c) of FIG. 6). 21) Deposit on. At this time, the composition ratio (x) of silicon to tungsten of the first tungsten silicide (WSi x ) film 22 is set as low as about 2.4 or less to minimize resistance. The deposition method is to reduce the WF 6 gas by SiH 4 or SiH 2 value 3 (DCS; Di Chloro silane) gas, and the composition ratio (x) of silicon to tungsten immediately after deposition is WF 6 gas and Adjustable by gas flow rate In addition, the thickness of the first tungsten silicide film 22 is about 50% to 90% of the desired thickness of the final silicide film. Thereafter, heat treatment is performed at a temperature of about 600 ° C. or higher to stabilize the crystal structure of the first tungsten silicide layer 22 and lower the resistance.
이어서 리소그래피 단계를 적용하여 즉 포토레지스트 마스크패턴(도시안함)을 제1텅스텐실리사이드막(22) 위에 형성하고 포토레지스트마스크패턴을 마스크로 하여 제1텅스텐실리사이드막(22)와 폴리실리콘막(21)을 식각하여, 제6도의 (d)와 같이, 원하는 전도선 형태의 폴리실리콘막(21')과 제1텅스텐실리사이드막(22')으로 적층된 도시패턴을 형성한다.Subsequently, a photoresist mask pattern (not shown) is formed on the first tungsten silicide layer 22 by applying a lithography step, and the first tungsten silicide layer 22 and the polysilicon layer 21 are formed using the photoresist mask pattern as a mask. Is etched to form a city pattern laminated with the polysilicon film 21 'and the first tungsten silicide film 22' of the desired conductive line shape as shown in FIG.
이어, 포토레지스트마스크패턴을 제거한 다음, 제6도의 (e)와 같이 도선패턴이 형성된 절연층(25') 전면에 산화억제막(23)인 제2텅스텐실리사이드막을 증착 형성한다. 제2텅스텐실리사이드(WSix)막은 제1텅스텐실리사이드막(22') 보다 텅스텐에 대한 실리콘의 조성비(x)가 높도록 형성하는데 바람직하기로는 약 2.5 내지 3.7 정도가 좋다.Subsequently, after removing the photoresist mask pattern, a second tungsten silicide film, which is an oxidation inhibiting film 23, is deposited on the entire surface of the insulating layer 25 'on which the conductive wire pattern is formed as shown in FIG. The second tungsten silicide (WSi x ) film is formed to have a higher composition ratio (x) of silicon to tungsten than the first tungsten silicide film 22 ', preferably about 2.5 to 3.7.
계속하여, 리소그래피 단계를 적용하여 제6도의 (f)와 같이 폴리실리콘막(21')과 제1텅스텐실리사이드막(22')으로 된 적층막 도선패턴의 측면과 상면에 제2텅스텐실리사이드막인 산하억제막(23')이 남도록 하고 그 외 부위를 제거하여 본 발명의 전도선을 완성한다. 마찬가지로 리소그래피단계는 산화억제막(23) 위에 포토레지스트마스크패턴(도시안함)을 형성한 다음, 포토레지스트마스크패턴을 마스크로 하여 산화억제막(23)을 식각하는 것이다.Subsequently, by applying a lithography step, the second tungsten silicide film is formed on the side and top of the laminated film lead pattern of the polysilicon film 21 'and the first tungsten silicide film 22' as shown in FIG. The conductive layer of the present invention is completed by leaving the acid suppression layer 23 'and removing other portions. Similarly, in the lithography step, a photoresist mask pattern (not shown) is formed on the oxidation inhibiting film 23, and then the oxidation inhibiting film 23 is etched using the photoresist mask pattern as a mask.
또한, 산화억제막으로 폴리실리콘막 또는 실리콘질화막을 형성하는 것은, 산화억제막으로 폴리실리콘막 또는 실리콘질화막을 적용하여 제6도의 (e)와 (f)에 도시한 단계를 적용하는 것이다.In addition, forming the polysilicon film or the silicon nitride film as the oxidation inhibiting film is to apply the steps shown in (e) and (f) of FIG. 6 by applying the polysilicon film or the silicon nitride film as the oxidation inhibiting film.
폴리실리콘막을 산화억제막으로 적용하는 경우에는 제1텅스텐실리사이드막의 두께와 선폭을 원하는 전도선의 최종적인 값으로 하여 저항을 최소화하도록 한다. 산화억제막으로 적용된 폴리실리콘막의 역할은, 이미 언급한 바와 같이, 차후 절연을 위해 그 위에 형성된 실리콘질화막 증착시 실리콘 소오스(Source)를 제공하므로써, 제1텅스텐실리사이드막 표면의 산소 원자의 출현을 막아 실리사이드막이 이상산화를 방지하는 것이다.When the polysilicon film is applied as an oxidation inhibiting film, the resistance is minimized by setting the thickness and line width of the first tungsten silicide film as the final value of the desired conductive line. The role of the polysilicon film applied as an oxidation inhibiting film, as already mentioned, prevents the appearance of oxygen atoms on the surface of the first tungsten silicide film by providing a silicon source when depositing a silicon nitride film formed thereon for subsequent insulation. The silicide film prevents abnormal oxidation.
산화방지막으로 널리 사용되고 있는 실리콘질화막을 본 발명의 산화억제막으로 적용할 경우에도 제1텅스텐실리사이드막의 두께와 선폭을 원하는 전도선의 최종적인 값으로 하면 되는데, 실리콘질화막의 두께는 약 50내지 100정도로 형성한다.When the silicon nitride film, which is widely used as an antioxidant film, is applied to the oxidation inhibiting film of the present invention, the thickness and line width of the first tungsten silicide film may be the final value of the desired conductive line, and the thickness of the silicon nitride film is about 50. To 100 Form to the extent.
상술한 바와 같이 본 발명의 전도선은 실리사이드 표면에 실리사이드의 금속성분의 산화를 억제하는 산화억제막을 형성하므로써, 저항이 낮은 실리사이드를 적용할 수 있으므로 고속동작을 하는 고집적소자에 적합하다. 특히 산화방지막을 금속성분에 대한 실리콘 조성비가 높은 실리사이드를 적용할 경우 하부의 폴리실리콘막의 측면까지 실리사이드가 형성되므로써, 전도선의 저항을 더욱 감소시킬 수 있다.As described above, the conductive wire of the present invention is suitable for high-integration devices with high-speed operation since silicide with low resistance can be applied by forming an oxidation inhibiting film that suppresses oxidation of the metal component of the silicide on the silicide surface. In particular, when the silicide is applied to the silicon film having a high silicon composition ratio to the metal component, silicide is formed up to the side surface of the polysilicon film below, thereby further reducing the resistance of the conductive line.
Claims (6)
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