KR100583962B1 - 반도체 장치의 트랜지스터들 및 그 제조 방법들 - Google Patents
반도체 장치의 트랜지스터들 및 그 제조 방법들 Download PDFInfo
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- KR100583962B1 KR100583962B1 KR1020040005858A KR20040005858A KR100583962B1 KR 100583962 B1 KR100583962 B1 KR 100583962B1 KR 1020040005858 A KR1020040005858 A KR 1020040005858A KR 20040005858 A KR20040005858 A KR 20040005858A KR 100583962 B1 KR100583962 B1 KR 100583962B1
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- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 39
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 39
- 238000009792 diffusion process Methods 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims description 68
- 125000006850 spacer group Chemical group 0.000 claims description 42
- 238000005468 ion implantation Methods 0.000 claims description 40
- 150000002500 ions Chemical class 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 229910020776 SixNy Inorganic materials 0.000 claims description 12
- -1 HfOx Inorganic materials 0.000 claims description 4
- 229910020286 SiOxNy Inorganic materials 0.000 claims description 4
- 229910003134 ZrOx Inorganic materials 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 230000002265 prevention Effects 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
Claims (25)
- 활성 영역을 갖는 반도체 기판에 배치되되, 그들은 상기 활성 영역에 배치된 전극 영역들 및 확산 방지 영역들;상기 전극 영역들 사이에 위치되어서 상기 활성 영역 상에 배치된 게이트 절연막;상기 게이트 절연막 상에 배치되는 게이트 패턴; 및상기 게이트 패턴의 측부들로부터 이격되도록 배치되어서 상기 전극 영역들에 전기적으로 각각 접속하는 전극 패턴들을 포함하되,상기 게이트 패턴은 실리 사이드 막으로 형성되고, 상기 게이트 패턴 및 상기 전극 영역들은 동일한 도전성을 가지고, 상기 전극 영역들은 각각이 상기 확산 방지 영역들로 감싸지도록 배치되고, 상기 확산 방지 영역들은 서로 이격되어서 상기 게이트 절연막과 중첩하도록 배치되고, 상기 확산 방지 영역들은 상기 전극 영역들과 다른 도전성을 가지는 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 게이트 패턴 및 상기 전극 영역들은 N 타입이고 동시에 상기 확산 방지 영역들은 P 타입인 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 게이트 패턴 및 상기 전극 영역들은 P 타입이고 동시에 상기 확산 방지 영역들은 N 타입인 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 게이트 패턴은 그 패턴의 측벽들에 각각이 게이트 스페이서들을 구비해서 상기 전극 패턴들과 절연되는 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 전극 영역들은 LDD(Lightly Doped Drain) 구조를 갖는 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 실리 사이드 막은 Ti, Co, Ni, Ta 및 그 조합물 중의 선택된 하나의 금속막과 폴리 실리콘 막의 결합으로 이루어진 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 전극 패턴은 Ti, Co, Ni, Ta 및 그 조합물 중의 선택된 하나의 금속막과 반도체 기판의 결합으로 이루어진 금속 실리 사이드 막인 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 전극 영역은 불순물 전극 한정 영역 및 불순물 전극 영역으로 이루어진 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 전극 영역들 사이에 채널 영역을 더 포함하는 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 게이트 패턴은 그 패턴의 직각 방향으로 절단한 단면이 정방형을 갖는 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 게이트 패턴은 그 패턴의 직각 방향으로 절단한 단면이 직방형을 갖는 것이 특징인 트랜지스터.
- 제 1 항에 있어서,상기 게이트 절연막은 SiOx, SiOxNy, HfOx, ZrOx 및 그들의 복합막 중의 선택된 하나인 것이 특징인 트랜지스터.
- 마스크 패턴들을 갖는 반도체 기판 상에 그 패턴들의 측벽을 덮는 마스크 스페이서들을 형성하되, 상기 마스크 스페이서들은 반도체 기판의 주 표면을 노출시키도록 형성하고,상기 마스크 스페이서들로 노출된 상기 반도체 기판의 주 표면 상에 게이트 절연막을 형성하고,상기 게이트 절연막 상에 배치하고 동시에 상기 마스크 스페이서들 사이에 위치하도록 희생 폴리막 패턴(Sacrified Poly Layer Pattern)을 형성하고,상기 마스크 패턴들 및 상기 마스크 스페이서들을 이온 주입 마스크로 사용해서 상기 희생 폴리막 패턴에 제 1 이온 주입 공정을 실시하여 그 폴리막 패턴에 불순물 이온들을 주입하고,상기 희생 폴리막 패턴에 실리 사이드 공정을 실시하여 그 폴리막 패턴을 실리 사이드 막(Silicide Layer)으로 변형시켜서 게이트 패턴을 형성하고,상기 마스크 패턴들 및 상기 마스크 스페이서들을 상기 반도체 기판으로부터제거하고,상기 게이트 패턴을 이온 주입 마스크로 사용해서 상기 반도체 기판에 제 2 및 제 3 이온 주입 공정들을 차례로 실시하여 그 기판에 불순물 전극 한정 영역들 및 확산 방지 영역들을 형성하고,상기 게이트 패턴들의 측벽들에 게이트 스페이서들을 형성하고,상기 게이트 패턴 및 상기 게이트 스페이서들을 이온 주입 마스크로 사용해서 상기 반도체 기판에 제 4 이온 주입 공정을 실시하여 그 기판에 불순물 전극 영역들을 형성하되, 상기 불순물 전극 한정 영역 및 상기 불순물 전극 영역은 하나의 전극 영역을 형성하고,상기 전극 영역들과 전기적으로 각각 접속하는 전극 패턴들을 형성하는 것을 포함하되,상기 전극 영역들은 상기 확산 방지 영역들 내 각각 형성되고, 상기 확산 방지 영역들은 상기 전극 영역들과 다른 도전성을 갖도록 형성되고, 상기 전극 영역들은 상기 게이트 패턴과 동일한 도전성을 갖도록 형성되고, 상기 희생 폴리막 패턴은 폴리실리콘 막을 사용해서 형성하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 마스크 패턴 및 상기 마스크 스페이서의 각각은 SixNy/ SiOx/ SixNy, SixNy/ SiOx, SiOx/ SixNy, SiOx/ SixNy/ SiOx, 및 SixNy 중의 선택된 하나를 사용해서 형성하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 게이트 절연막은 SiOx, SiOxNy, HfOx, ZrOx 및 그들의 복합막 중의 선택된 하나를 사용해서 형성하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 희생 폴리막 패턴을 형성하는 것은,상기 마스크 패턴들 및 상기 마스크 스페이서들을 갖는 반도체 기판 상에 희생 폴리막을 형성하고,상기 희생 폴리막에 평탄화 공정을 수행해서 상기 마스크 패턴들 및 상기 마스크 스페이서들을 부분 식각하는 것을 포함하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 전극 패턴들은 Ti, Co, Ni, Ta 및 그 조합물 중의 선택된 하나의 금속막 및 반도체 기판을 반응시킨 금속 실리사이드 막으로 형성한 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 실리 사이드 막은 Ti, Co, Ni, Ta 및 그 조합물 중의 선택된 하나의 금속막 및 도핑된 폴리 실리콘 막을 반응시켜서 형성한 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 게이트 절연막을 형성하기 전,상기 마스크 스페이서들로 노출된 상기 반도체 기판에 불순물 한정 영역을 형성하는 것을 더 포함하되,상기 불순물 전극 한정 영역들은 상기 불순물 한정 영역을 고립시켜서 상기 게이트 패턴 아래의 반도체 기판에 채널 영역을 형성하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 전극 영역은 LDD(Lightly Doped Drain) 구조를 갖도록 형성하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 게이트 패턴 및 상기 전극 영역들은 N 타입의 도전형을 갖고 동시에 상기 확산 방지 영역들은 P 타입의 도전형을 갖도록 형성하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 게이트 패턴 및 상기 전극 영역들은 P 타입의 도전형을 갖고 동시에 상기 확산 방지 영역들은 N 타입의 도전형을 갖도록 형성하는 것이 특징인 트랜지스터의 제조방법.
- 제 13 항에 있어서,상기 게이트 패턴은 상기 제 1 내지 제 4 이온 주입 공정들을 통해서 하나 의 도전형을 갖도록 형성하는 것이 특징인 트랜지스터의 제조방법
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