KR100576458B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the BPSG layer in the cell region is unnecessarily etched to remove the BPSG layer in the peripheral region by the selective etching of the BPSG layer. In order to solve the problem of voids in the BPSG layer and deterioration of the characteristics of the semiconductor device, a bit line plug layer is further formed at the boundary between the cell region and the peripheral region to serve as an etch barrier, and voids are generated. The present invention relates to an invention capable of improving the yield and reliability of devices, such as preventing short circuits between bit lines.

Description

Method for manufacturing semiconductor device

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2 is a photograph showing that voids are generated in a conventional cell region.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
4 is a photo showing a cell region during the BPSG layer etching process of the peripheral region of the present invention
5 is a photograph showing a cell region of the present invention.
<Description of Symbols for Main Parts of Drawings>

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11, 31: semiconductor substrate 13, 33: device isolation film

15, 35: word line 17, 37: first nitride film

18, 38: second nitride film 19, 39: BPSG layer

21: plug layer 23, 43: third photosensitive film

25: void 41: plug layer for first bit line
42: plug layer for second bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the BPSG layer in the cell region is unnecessarily etched to remove the BPSG layer in the peripheral region by the selective etching of the BPSG layer. In order to solve the problem of voids in the BPSG layer and deterioration of the characteristics of the semiconductor device, a bit line plug layer is further formed at the boundary between the cell region and the peripheral region to serve as an etch barrier, and voids are generated. The present invention relates to an invention capable of improving the yield and reliability of devices, such as preventing short circuits between bit lines.

Semiconductor devices show an increase in the degree of integration every year, and the increase in the density is accompanied by a reduction in the area and size of each component of the device has a variety of process constraints.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, and FIG. 2 is a photograph showing that voids are generated in a conventional cell region.

In the conventional method of manufacturing a semiconductor device, as shown in FIG. 1A, a first oxide film and a first oxide film are formed on a semiconductor substrate 11 in which a device isolation film 13 is formed in a device isolation region and a cell region and a peripheral region are defined. A polycrystalline silicon layer, a first nitride film 17 which is a hard mask layer, and a first photosensitive film (not shown) are sequentially formed.

Thereafter, the first photoresist film is selectively exposed and developed to remain only in a portion where a word line is to be formed, and then the first nitride film 17 and the first photoresist film are selectively exposed and developed. After the first polycrystalline silicon layer and the first oxide film are selectively etched to form a word line 15 with a gate insulating film on the semiconductor substrate 11, the first photosensitive film is removed.

After the second nitride film 18 is formed on the entire surface, a BPSG (Boron Phosphor Silicate Glass) layer 19 and a second photosensitive film (not shown) are formed on the second nitride film 18. ) Are formed sequentially.

Subsequently, the second photoresist layer is selectively exposed and developed to be removed only at a portion where a bit line contact is to be formed, and then the BPSG layer 19 is selected using the selectively exposed and developed second photoresist layer as a mask. After etching, the second photosensitive film is removed.

In addition, the second nitride layer 18 is etched back using the BPSG layer 19 as a mask to form a first contact hole, and the semiconductor substrate 11 on one side of the exposed word line 15 is formed. The second nitride film spacer 18a is formed on the substrate.

Thereafter, a second polycrystalline silicon layer is formed on the entire surface including the first contact hole, and then the second polycrystalline silicon layer is flat-etched by a chemical mechanical polishing method using the BPSG layer 19 as an etching end point. 21 is formed.

As shown in FIG. 1B, a third photosensitive film 23 is coated on the BPSG layer 19.

The third photosensitive film 23 is selectively exposed and developed to remain only in the cell region.

As shown in FIG. 1C, the BPSG layer 19 in the peripheral region is wet-etched and removed using the selectively exposed and developed third photoresist layer 23 as a mask.

Here, in the process of removing the BPSG layer in the peripheral region due to the poor contact between the BPSG layer 19 and the third photoresist layer 23, an etching solution is formed along the third photoresist layer 23 in the BPSG layer 19 of the cell region. As it penetrates, the side etching of the BPSG layer 19 is generated, and as shown in FIG. 2, a void 25 is generated.

Then, the third photosensitive film 23 is removed in a subsequent step.

The conventional method for manufacturing a semiconductor device has a problem that the yield and reliability of the device are deteriorated due to the following reasons.

First, in the process of removing the BPSG layer in the peripheral region due to poor contact between the BPSG layer and the photoresist layer, side etching of the BPSG layer occurs along the photoresist layer, and the etching solution penetrates into the BPSG layer of the cell region, thereby causing voids. In the chemical mechanical polishing process, a slurry is caught in the voids, and a large amount of particles are generated, and in the bit line forming process, the bit line forming material remains along the voids, causing short circuits between the bit lines. .

Second, in order to solve the first problem, an HDP (High Density Plasma) oxide film is formed on the BPSG layer, but the side etching of the BPSG layer is not prevented.

Third, in order to solve the first problem, a nitride film is formed on the BPSG layer, but the nitride film removing process is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the semiconductor layer prevents the BPSG layer etching phenomenon in the cell region by protruding the plug layer by selective front etching of the BPSG layer and then proceeding to remove the BPSG layer in the peripheral region. It is an object of the present invention to provide a method for manufacturing a device.

The method of manufacturing a semiconductor device of the present invention comprises the steps of forming a word line in a cell region and a peripheral region on a semiconductor substrate,
Forming an etch stop layer on the entire surface of the semiconductor substrate;
Forming an interlayer insulating film including a bit line contact plug layer formed between a word line of the cell region and a boundary between the cell region and a peripheral region;
Selectively etching the interlayer insulating film to protrude an upper portion of the bit plug contact plug layer;
And removing the interlayer insulating film in the peripheral area by a wet etching method.

When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, an isolation layer 33 is formed at a boundary between a cell region and a peripheral region of a semiconductor substrate, and a first oxide film, a first polycrystalline silicon layer, is formed on a semiconductor substrate 31 having a cell region and a peripheral region defined therein. The first nitride film 37 and the first photosensitive film (not shown) which are hard mask layers are sequentially formed.

Thereafter, the first photoresist film is selectively exposed and developed to remain only at the site where the word line is to be formed, and then the first nitride film 37 and the first polycrystalline silicon layer are formed using the selectively exposed and developed first photoresist film as a mask. And selectively etching the first oxide layer to form a word line 35 on the semiconductor substrate 31 with a gate insulating layer thereon, and then removing the first photosensitive layer.

After the second nitride film 38 is formed on the entire surface, the BPSG layer 39 and the second photosensitive film (not shown) which are interlayer insulating films are sequentially formed on the second nitride film 38.

Subsequently, the second photoresist layer is selectively exposed and developed so as to be removed only at a portion where a contact for the bit line is to be formed, and then selectively etched the BPSG layer 39 using the selectively exposed and developed second photoresist layer as a mask. , The second photosensitive film is removed. In this case, the first bit line contact hole is formed between the word line 35 of the cell region, and the second bit line contact hole is formed at the boundary between the cell region and the peripheral region.

The second nitride layer 38 is etched back using the BPSG layer 39 as a mask to form a second nitride layer spacer 38a on the exposed sidewall of the word line 35.

Thereafter, after forming a second polycrystalline silicon layer on the front surface including the first and second bit line contact holes, the second polycrystalline silicon layer is flattened by a chemical mechanical polishing method with the BPSG layer 39 as an etch end point. Etching is performed to form contact plug layers 41 and 42 for the first and second bit lines.

Referring to FIG. 3B, the BPSG layer 39 may be selectively etched to protrude the first and second bit line contact plug layers 41 and 42.

Here, the BPSG layer 39 may be entirely etched by a dry etching method or a wet etching method, but when etched by a dry etching method as follows.

The BPSG layer 39 is a carbon-containing gas that causes a large amount of polymer (Polymer) selected from the group consisting of C ₃ F ₈ , C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , and C ₂ F ₄ Etching is performed by a dry etching method using a first etching gas.

Alternatively, the second BPSG layer 39 is at least one gas selected from the group consisting of CHF ₃ , C ₂ HF ₅ , CH ₂ F ₂ , CH ₃ F, CH ₂ , CH ₄ , C ₂ H ₄ and H ₂ . Etch by a dry etching method using an etching gas.

Alternatively, the BPSG layer 39 may be etched by a dry etching method using a third etching gas mixed with an inert gas, or by a dry etching method using a gas mixed with the first, second and third etching gases. Etch it.

Referring to FIG. 3C, a third photosensitive layer 43 is coated on the entire surface of the semiconductor substrate including the protruding first and second bit line contact plug layers 41 and 42.

In order to increase the contact force between the first and second bit line contact plug layers 41 and 42 and the third photoresist layer 43, the third photoresist layer 43 may be subjected to a heat treatment, an E-beam treatment, or the like. Ultra-Violet Light processing is in progress.

Subsequently, the third photoresist layer 43 is selectively exposed and developed to remain only in the cell region.

Referring to FIG. 3D, the BPSG layer 39 in the peripheral region is exposed to the HF: NH ₄ F: DI mixed solution, HF: DI mixed solution, and HF: using the selectively exposed and developed third photoresist layer 43 as a mask. It is etched by a wet etching process using a mixed solution selected from a mixed solution of NH ₄ F: DI surfactant and a HNO ₃ : CH ₃ COOH: HF mixed solution.

Then, the third photosensitive film 43 is removed in a subsequent step.

Here, in the wet etching process of the BPSG layer 39, the first and second bit line contact plug layers 41 and 42 and the third and third bit line contact plug layers 41 and 42 may be formed. The contact area with the photosensitive film 43 is increased, and the protruding second bit line contact plug layer 42 serves as an etching barrier so that the etching solution is formed along the third photosensitive film 43 with the BPSG in the cell region. Since it is prevented from penetrating the layer 39, no void is generated in the cell region as shown in FIGS. 4 and 5.

In the method of manufacturing a semiconductor device of the present invention, the bit line plug layer is further formed at the boundary between the cell region and the peripheral region to serve as an etch barrier, and after protruding the plug layer by selective front etching of the BPSG layer, By performing the BPSG layer removal process in the peripheral region, the BPSG layer etching phenomenon of the cell region generated during the BPSG layer removal process is prevented, thereby suppressing void generation and preventing short circuit between bit lines, thereby improving device yield and reliability. It works.

Claims (6)

Forming word lines in the cell region and the peripheral region on the semiconductor substrate; Forming an etch stop layer on the entire surface of the semiconductor substrate; Forming an interlayer insulating layer including a bit line contact plug layer formed between a word line of the cell region and a boundary between the cell region and a peripheral region; Selectively etching the interlayer insulating layer to protrude an upper portion of the contact plug layer for the bit line; And And removing the interlayer insulating film in the peripheral region by a wet etching method. The method of claim 1, And the interlayer insulating film is formed of a BPSG layer. The method of claim 1, Selective front side etching of the interlayer insulating film may include C ₃ F ₈ , C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , and C ₂ F ₄ . A method of manufacturing a semiconductor device, characterized in that performed by a dry etching method using a gas. The method of claim 1, The step of selectively etching the interlayer insulating film may include at least one gas selected from the group consisting of CHF ₃ , C ₂ HF ₅ , CH ₂ F ₂ , CH ₃ F, CH ₂ , CH ₄ , C ₂ H ₄ and H ₂ . Method of manufacturing a semiconductor device, characterized in that carried out by a dry etching method using. The method according to claim 3 or 4, Selectively etching the interlayer insulating film may be performed by a dry etching method using a gas in which an inert gas is mixed. The method of claim 1, The interlayer insulating film in the peripheral region is selected from a mixed solution of HF: NH ₄ F: DI mixed solution, HF: DI mixed solution, HF: NH ₄ F: DI surfactant mixed solution, and HNO ₃ : CH ₃ COOH: HF mixed solution. Method for manufacturing a semiconductor device characterized in that the etching by the wet etching process using.

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