KR100488159B1 - Method and apparatus for dual scanning plasma display panel - Google Patents

Abstract

The present invention relates to a dual scanning method and apparatus for a plasma display panel which reduces the address period without increasing the data drive integrated circuit.

In the dual scanning method of the PDP according to the present invention, a scan pulse of a first polarity is supplied to the first scan electrode and a scan pulse of a second polarity is supplied to the second scan electrode. Selecting one of three data voltages and a base voltage having different synchronous voltage levels, and supplying the selected data voltage and base voltage to the data electrode to select a cell;

Description

Dual scanning method and apparatus of plasma display panel {METHOD AND APPARATUS FOR DUAL SCANNING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a dual scanning method and apparatus for a plasma display panel which reduces the address period without increasing the data drive integrated circuit.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development. Recently, a three-electrode AC surface discharge type PDP that lowers the driving voltage using wall charges accumulated in a dielectric has been developed and sold.

Referring to FIG. 1, in the conventional three-electrode AC surface discharge type PDP, n scan electrodes (Y1 to Yn) and n common sustain electrodes (Z) have m data electrodes (X1 to) with a discharge space therebetween. Intersect Xm) and m × n cells 1 are formed at the intersection. A partition 2 is formed between the adjacent data electrodes X1 to Xm to block electrical and optical interference between horizontally adjacent cells 1.

After the scan signals are sequentially applied to the scan electrodes Y1 to Yn to select the scan lines, the sustain pulses are commonly applied to generate the sustain discharge for the selected cells. The common sustain electrodes Z apply sustain pulses alternately with the sustain pulses supplied to the scan electrodes Y1 to Yn to generate sustain discharges for the selected cells. The data electrodes X1 to Xm select a cell 1 by applying a data pulse synchronized with the scan signal.

The PDP is time-divisionally driven by dividing one field period (NTSC system: 16.67 ms) into several subfields with different number of emission times in order to realize grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and a cell for selecting a cell in the selected scan line, and a sustain period (or display period) for expressing gray scales according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. As described above, each of the eight subfields SF1 to SF8 is divided into a reset period, a scan period, and a display period. Here, the reset period and the address period of each subfield are the same for each subfield, while the display period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased.

3 schematically illustrates a conventional single bank type PDP apparatus.

Referring to FIG. 3, the conventional single bank type PDP apparatus includes a data driving circuit 31 for supplying video data to the data electrodes X1 to Xm of the PDP 30, and the scan electrodes Y1 to Yn. Scan driving circuit 32 for supplying an initialization signal, scan pulses and sustain pulses, and sustain drive circuit 33 for supplying sustain pulses to the common sustain electrode (Z).

The PDP 30 has data electrodes X1 to Xm formed on the lower plate. In addition, the scan electrodes Y1 to Yn and the common sustain electrode Z are formed on the upper surface of the PDP 30 so as to cross the data electrodes X1 to Xm.

The data driving circuit 31 supplies video data to the data electrodes X1 to Xm to be synchronized with the scan pulses sequentially supplied to the scan electrodes Y1 to Yn.

The scan driving circuit 32 simultaneously supplies the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the scan electrodes Y1 to Yn during the reset period. The scan driving circuit 32 sequentially supplies the scan pulses to the scan electrodes Y1 to Yn during the address period.

During the sustain period, the scan driving circuit 32 and the sustain driving circuit 33 alternately operate to supply the sustain pulses to the scan electrodes Y1 to Yn and the common sustain electrode Z.

4 illustrates a driving waveform of the PDP generated from the driving circuit shown in FIG. 3.

Referring to FIG. 4, during the reset period, the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down are simultaneously applied to all scan electrodes Y. FIG. Ramp-up causes a slight discharge in the cells of the full screen, resulting in wall charges in the cells of the full screen. Ramp-down generates a weak erase discharge in the cells, thereby eliminating unnecessarily excessive charges during wall charges and space charges generated by the setup discharge, thereby uniforming the wall charges required for address discharge in the cells of the full screen. Is left.

In the address period, a negative scan pulse (-scn) is sequentially applied to the scan electrodes (Y) and a positive data pulse (data) is applied to the data electrodes (X) so as to be synchronized with the scan pulse (-scn). do. As the voltage difference between the scan pulse (-scn) and the data pulse (data) and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse (data) is applied.

On the other hand, a positive DC voltage Zdc is supplied to the common sustain electrode Z during the period in which the falling ramp waveform Ramp-down is supplied and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. Each time the sustain pulse (sus) is applied, the cell selected by the address discharge is a surface discharge form between the scan electrode (Y) and the common sustain electrode (Z) by adding the voltage of the wall voltage and the sustain pulse (sus) in the cell This causes a sustain discharge. At the end of the sustain period, an erase signal in the form of a ramp waveform for canceling the sustain discharge can be supplied.

However, the conventional PDP has a problem in that it is difficult to sufficiently maintain the sustain period when a subfield is added to increase the resolution accompanied by an increase in the number of lines and cells or to reduce contour noise in a moving image.

For example, an address period required in one subfield at a resolution of VGA (640 x 480) class takes 3 mu s (width of scan pulse required for one line scan) x 480 = 1.44 ms. The reset period required for each subfield is approximately 300 to 600 µs. Assuming that eight subfields SF1 to SF8 are included in one field period (16.67ms) as shown in FIG. 2, the total reset period and address period required within one frame period at VGA resolution are (1.44ms × 8). ) + ((0.3 to 0.6 ms) x 8) = 13.92 to 16.32 ms. The sustain period except for the reset period and the address period is 16.67 ms (frame period)-(13.92 to 16.32 ms) = 0.35 to 2.75 ms, which is only 2.09 to 16.5% of one frame period. Therefore, if eight subfields are allocated within one frame period at a VGA resolution, the luminance is low due to the absolute shortage of the sustain period, and if the number of subfields is added, the sustain period is allocated within one frame period. Can't be.

When the resolution is increased to XGA (1024 x 768) class, the address period required in one subfield takes 3 mu s (width of scan pulse required for one line scan) x 768 = 2.3 ms. In addition, the reset period required in one subfield is approximately 300 to 600 µs. Assuming that eight subfields SF1 to SF8 are included in the resolution of XGA, the total reset period and address period within one frame period are (2.3 ms x 8) + ((0.3 to 0.6 ms) x 8) = 20.8 to 23.2 ms. If eight subfields are included in the XGA resolution, the sustain period except for the reset period and the address period within one frame period is 16.67 ms (frame period)-(20.8 to 23.2 ms) = -6.53 to 4.13 ms. Therefore, if eight subfields are allocated in one frame in the XGA class, the display period, that is, the sustain period cannot be allocated, and thus resolution over XGA cannot be realized.

In order to solve the problem of lack of driving time, a so-called 'double bank method' for dividing the PDP 40 into the upper half and the lower half and simultaneously scanning the upper half and the lower half as shown in FIG. 5 has been proposed and applied by some manufacturers. 6 shows a drive waveform of the double bank method.

5 and 6, a conventional double bank type PDP apparatus includes a first data driving circuit 41A for supplying video data to the data electrodes Xt1 to Xtm formed on the upper half of the PDP 40. And a second data driver circuit 41A for supplying video data to the data electrodes Xb1 to Xbm formed in the lower half of the PDP 40, and an initialization signal, scan pulses and sustain to the scan electrodes Y1 to Yn. A scan drive circuit 42 for supplying a pulse and a sustain drive circuit 43 for supplying a sustain pulse to the common sustain electrode Z are provided.

In the PDP 40, data electrodes Xt1 to Xtm and Xb1 to Xbm separated from the center are formed on the lower plate so that separate data can be simultaneously supplied to the upper half and the lower half. In addition, the scan electrodes Y1 to Yn and the common sustain electrode Z are formed on the upper surface of the PDP 40 so as to intersect the data electrodes Xt1 to Xtm and Xb1 to Xbm.

The first data driving circuit 41A provides video to the upper data electrodes Xt1 to Xtm to be synchronized with the scan pulse scn which is sequentially supplied to the first to n / 2th scan electrodes Y1 to Y2 / n. Supply the data.

The second data driving circuit 41B includes the lower data electrodes Xb1 to synchronously with the scan pulse scn which is sequentially supplied to the n / 2 + 1 to nth scan electrodes Yn / 2 + 1 to Yn. Xbm) is supplied with video data.

The scan driving circuit 42 simultaneously supplies the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the scan electrodes Y1 to Yn during the reset period. The scan driving circuit 42 simultaneously scans the upper half and the lower half of the PDP 40 during the address period. At this time, scan pulses (-scn) are simultaneously supplied to one scan electrode present in the upper half of the PDP 40 and one scan electrode present in the lower half of the PDP 40.

During the sustain period, the scan driving circuit 42 and the sustain driving circuit 43 alternately operate to supply the sustain pulse SUS to the scan electrodes Y1 to Yn and the common sustain electrode Z.

However, the conventional double bank method can reduce the address period by about 2/1 as compared to the single bank method of the same resolution, but the data driving circuit 41A for driving the data electrodes in the upper half and the data electrodes for driving the lower half Since the data driving circuit 41B is required, the number of integrated circuits of the data driving circuit increases.

Accordingly, it is an object of the present invention to provide a dual scanning method and apparatus for a PDP that reduces the address period without increasing the data drive integrated circuit.

In order to achieve the above object, the dual scanning method of the PDP according to the present invention comprises the steps of supplying a scan pulse of the first polarity to the second scan electrode at the same time as supplying a scan pulse of the first polarity, Selecting one of three data voltages and a base voltage having a different voltage level capable of synchronizing with the scan pulses having different polarities, and supplying the selected data voltage and the base voltage to the data electrode to supply a cell. The data voltage is selected according to two data logic values. The dual scanning apparatus of the plasma display panel according to the present invention supplies a scan pulse of a first polarity to a first scan electrode and simultaneously a second scan voltage. A scan driving circuit for supplying a scan pulse of polarity to the second scan electrode, and three voltage levels having different voltage levels that can be synchronized with the scan pulses of different polarities And a data driving circuit for selecting one of the data voltages and the base voltage and supplying the voltage to the data electrode. The data driving circuit selects a data voltage according to two data logic values. Other objects and features of the will be apparent from the description of the embodiments with reference to the accompanying drawings.

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Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 10.

Referring to FIG. 7, a PDP apparatus according to an exemplary embodiment of the present invention selects one of three voltage levels to supply video data to data electrodes X1 to Xm of the PDP 70. 71, a scan driving circuit 72 for supplying scan pulses having different voltage levels to the scan electrodes Y1 to Yn of the PDP 70, and a sustain for driving the common sustain electrode Z; The driving circuit 73, the timing controller 74 for controlling the driving circuits 71, 72, and 73, and the voltages Va, -Va, and Va + required for the driving circuits 71, 72, and 73, respectively. And a power supply circuit 75 for generating 2Vsc, Vsc, -Vsc, Vs, and Vstup.

The PDP 40 selects two horizontal display lines (or scan lines) every horizontal period according to the voltage difference between the data voltage supplied from the data driving circuit 71 and the scan voltage supplied from the scan driving circuit 72. The data electrodes X1 to Xm formed on the lower plate of the PDP 70 are not separated unlike the conventional double bank method. Scan electrodes Y1 to Yn and a common sustain electrode Z intersecting the data electrodes X1 to Xm are formed on the upper plate of the PDP 70.

The data driving circuit 71 receives three data voltages Va, -Va, and Va + 2Vsc having different voltage levels and polarities, and generates three data according to the data logic values of two cells every horizontal period during the address period. Voltages Va, −Va, and Va + 2Vsc are selected to supply the data electrodes X1 to Xm of the PDP 70.

The scan driving circuit 72 simultaneously supplies signals for initializing the full screen to the scan electrodes Y1 to Yn during the reset period. The scan driving circuit 72 simultaneously supplies the scan voltages Vsc and -Vsc having different polarities to the two scan electrodes Y1 to Yn during the horizontal period during the address period.

During the sustain period, the scan driving circuit 72 and the sustain driving circuit 73 alternately operate to supply the sustain pulses to the scan electrodes Y1 to Yn and the common sustain electrode Z.

8 shows a scan voltage and a data voltage.

As can be seen in FIG. 8, the data driving circuit 71 selects one of three data voltages Va, -Va, and Va + 2Vsc having different polarities and different voltage levels, and the scan driving circuit 71. ) Supplies the positive scan voltage Vsc to one scan electrode and the negative scan voltage -Vsc to the other scan electrodes among the scan voltages Vsc and -Vsc having different polarities.

9 shows the data driving circuit 71 in detail.

Referring to FIG. 9, the data driving circuit 7 may include a first bus line 81a to which Va voltage is input, a second bus line 81b to which −Va voltage is input, and a Va + 2Vsc voltage to be input. The third bus line 81c, the fourth bus line 81d to which the ground voltage GND is input, and the data voltage for selecting the data voltage according to the logic values of the data (top (btm)) corresponding to the two generations. The logic circuit 82 is provided.

The logic circuit 82 selects any one of the three data voltages Va, -Va, Va + 2Vsc or the base voltage by controlling the switch 83 according to the logic value of the data as shown in Table 1 below.

If the logical value of the data is '1', the cell to which the data is supplied is selected. If the logical value of the data is '0', the cell to which the data is supplied is not selected. The selected data voltages Va, -Va, and Va + 2Vsc are shown in Table 1 below. As can be seen from Table 1, the number of possible cases where two cells are selected is four cases as shown in Table 1 below.

data (top, btm) Address data voltage (1,1) Va + 2Vsc (1,0) Va (0,1) -Va (0,0) GND

The address discharge for selecting a cell has a voltage difference between the data voltage and the scan voltage. This is the case.

The data voltage is selected as Va + 2Vsc so that the logic values of the data corresponding to the two cells are (1,1) so that both cells are selected. If the data voltage is Va + 2Vsc, the voltage difference between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn is different in the cells supplied with the scan voltage of -Vsc and the cells supplied with the Vsc. As a result, address discharge occurs in the two cells.

The data voltage is selected as Va or -Va so that one of the two cells is selected as the logic value of the data corresponding to the two cells is (1,0) or (0,1). When the data voltage is Va, the cell to which the scan voltage of -Vsc is supplied has a voltage difference between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn. Since the address discharge occurs, the voltage difference between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn is different in the cell to which the scan voltage of Vsc is supplied. As It becomes smaller and no address discharge occurs. When the data voltage is -Va, the cell to which the scan voltage of -Vsc is supplied has a voltage difference between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn. As While smaller and no address discharge occurs, the cell to which the scan voltage of Vsc is supplied has a voltage difference between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn. Therefore, address discharge occurs.

Since the logic value of the data corresponding to the two cells is (0,0), the data voltage is selected as the ground voltage GND so that both of the cells are unselected. In this case, the voltage difference between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn in both cells is It becomes smaller and no address discharge occurs.

10 illustrates a driving waveform for driving a PDP according to an embodiment of the present invention during one subfield period. The driving waveform of the PDP is generated from the driving circuit of the PDP device shown in FIG.

Referring to FIG. 10, in the PDP according to the embodiment of the present invention, one scan line is selected in the upper half and one scan line in the lower half.

In the reset period, the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down are simultaneously applied to all the scan electrodes Y. Ramp-up causes a slight discharge in the cells of the full screen, resulting in wall charges in the cells of the full screen. Ramp-down generates a weak erase discharge in the cells, thereby eliminating unnecessarily excessive charges during wall charges and space charges generated by the setup discharge, thereby uniforming the wall charges required for address discharge in the cells of the full screen. Is left.

During the address period, the scan driving circuit 72 sequentially supplies the negative scan pulse (-scn) to the scan electrodes Y1 to Yn / 2 present in the upper half of the PDP 70. At the same time, the scan driving circuit 72 sequentially supplies the positive scan pulse scn to the scan electrodes Yn / 2 + 1 to Yn in the lower half of the PDP 70. The data driving circuit 71 supplies the data voltages Va, -Va, Va + 2Vsc, which are synchronized with the scan pulses scn and -scn, to the data electrodes X1 to Xm. As described above, the data driving circuit 71 selects one of three data voltages Va, -Va, and Va + 2Vsc having different polarities and voltage levels according to the logic values of the data corresponding to the two cells. Choose. As the voltage difference between the scan pulses (scn, -scn) and the data pulses (data) and the wall voltage generated during the reset period are added, the voltage difference between the data electrodes (X1 to Xm) and the scan electrodes (Y1 to Yn) is increased. In the above cell, address discharge occurs.

During the period in which the falling ramp waveform Ramp-down is supplied and the address period, the common sustain electrode Z is supplied with a positive DC voltage Zdc.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. Each time the sustain pulse (sus) is applied, the cell selected by the address discharge is a surface discharge form between the scan electrode (Y) and the common sustain electrode (Z) by adding the voltage of the wall voltage and the sustain pulse (sus) in the cell This causes a sustain discharge. At the end of the sustain period, an erase signal in the form of a ramp waveform for canceling the sustain discharge can be supplied.

As described above, the dual scanning method and apparatus of the PDP according to the present invention selects one of three steps of data voltages having different polarities and voltage levels according to the logic value of the data corresponding to the two cells, and scans two scans. By supplying scan voltages of different polarities to the electrodes, two lines can be selected simultaneously. As a result, in the dual scanning method and apparatus of the PDP according to the present invention, since the data electrodes are not divided and the data electrodes can be driven by the minimum data driving circuit, and two lines can be selected at the same time, the address period can be changed. Compared to the banking method, it can be reduced to at least 1/2 or less, and the sustain period, which is the display period, can be sufficiently secured. Furthermore, the dual scanning method and apparatus of the PDP according to the present invention can secure the sustain period even when the PDP increases the number of cells at a high resolution. The number of subfields can be reduced for the purpose of reducing the pseudo contour noise of the video and reducing the quality deterioration in the video.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view showing the electrode arrangement of a conventional three-electrode alternating surface discharge type plasma display panel.

2 is a diagram illustrating a frame structure of a conventional plasma display panel.

3 is a block diagram schematically illustrating a conventional single bank type plasma display panel device.

4 is a waveform diagram showing driving waveforms of a conventional single bank plasma display panel.

5 is a block diagram schematically illustrating a conventional double bank type plasma display panel device.

Fig. 6 is a waveform diagram showing a drive waveform of a conventional double bank plasma display panel.

7 is a block diagram schematically illustrating a plasma display panel device according to an embodiment of the present invention.

FIG. 8 is a waveform diagram illustrating a data voltage generated from the data driver circuit shown in FIG. 7 and a scan voltage generated from the scan driver circuit.

FIG. 9 is a circuit diagram illustrating the data driving circuit shown in FIG. 7 in detail.

FIG. 10 is a waveform diagram illustrating driving waveforms supplied to a plasma display panel according to an exemplary embodiment of the present invention during one subfield period.

<Description of Symbols for Main Parts of Drawings>

1 cell 2 bulkhead

30, 40, 70: plasma display panel 31, 41A, 41B, 71: data driving circuit

32,42,72: scan drive circuit 33,43,73: sustain drive circuit

81a to 81d: Bus line 82: Logic circuit

83: switch

Claims (10)

Supplying a scan pulse of a first polarity to the second scan electrode while supplying a scan pulse of the first polarity to the first scan electrode; Selecting one of three data voltages and a base voltage having different voltage levels that can be synchronized with the scan pulses having different polarities; And selecting a cell by supplying the selected data voltage and the ground voltage to the data electrode. delete delete delete The method of claim 1, And the data voltage is selected according to two data logic values. A scan driving circuit which supplies a scan pulse of a first polarity to the first scan electrode and simultaneously supplies a scan pulse of a second polarity to the second scan electrode; And a data driving circuit for selecting one of three data voltages and a base voltage having different voltage levels that can be synchronized with the scan pulses having different polarities, and supplying the voltage to the data electrodes. Dual scanning device. delete delete delete The method of claim 6, And the data driving circuit selects a data voltage according to two data logic values.