KR100488458B1 - Scanning method and apparatus of plasma display panel - Google Patents

Abstract

The present invention relates to a method and apparatus for scanning a plasma display panel, which reduces the scan time and reduces the cost of the data driving circuit.

The scan method of the PDP according to the embodiment of the present invention has a first electrode, a second electrode and a third electrode having a first and a second scan / sustain driver for supplying a scan pulse to the first and second electrodes, A method for scanning a plasma display panel in which cells are provided at intersections of the electrodes, the method comprising: supplying an initialization signal to at least one of the electrodes to form a wall charge in the cell; Supplying the scan pulse to each of the first electrode and the second electrode simultaneously using a first and a second scan / sustain driver; And supplying data to the third electrode, and simultaneously selecting cells included in at least two lines using scan pulses and wall charges.

Description

SCANNING METHOD AND APPARATUS OF PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for scanning a plasma display panel which reduces the scan time and reduces the cost of a data driving circuit.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development. Recently, a three-electrode AC surface discharge type PDP that lowers the driving voltage using wall charges accumulated in a dielectric has been developed and sold.

Referring to FIG. 1, in the conventional three-electrode AC surface discharge type PDP, n scan electrodes Y1 to Yn and n common sustain electrodes Z have a discharge space therebetween with m address electrodes X1 through. Intersect Xm) and m × n cells 1 are formed at the intersection. A partition 2 is formed between the adjacent address electrodes X1 to Xm to block electrical and optical interference between horizontally adjacent cells 1.

After the scan signals are sequentially applied to the scan electrodes Y1 to Yn to select the scan lines, the sustain pulses are commonly applied to generate the sustain discharge for the selected cells. The common sustain electrodes Z apply sustain pulses alternately with the sustain pulses supplied to the scan electrodes Y1 to Yn to generate sustain discharges for the selected cells. The data electrodes synchronized with the scan signal are applied to the address electrodes X1 to Xm to select the cell 1.

The PDP performs time division driving by dividing one frame period (NTSC system: 16.67 ms) into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and a cell for selecting a cell in the selected scan line, and a sustain period (or display period) for expressing gray scales according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. As described above, each of the eight subfields SF1 to SF8 is divided into a reset period, a scan period, and a display period. Here, the reset period and the address period of each subfield are the same for each subfield, while the display period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased.

3 schematically illustrates a conventional single scan PDP apparatus.

Referring to FIG. 3, the conventional single scan type PDP apparatus includes a data driving circuit 31 for supplying video data to the address electrodes X1 to Xm of the PDP 30, and the scan electrodes Y1 to Yn. Scan driving circuit 32 for supplying an initialization signal, scan pulses and sustain pulses, and sustain drive circuit 33 for supplying sustain pulses to the common sustain electrode (Z).

In the PDP 30, address electrodes X1 to Xm are formed on the lower plate. In addition, the scan electrodes Y1 to Yn and the common sustain electrode Z are formed on the upper surface of the PDP 30 so as to intersect the address electrodes X1 to Xm.

The data driving circuit 31 supplies video data to the address electrodes X1 to Xm so as to be synchronized with the scan pulses sequentially supplied to the scan electrodes Y1 to Yn.

The scan driving circuit 32 simultaneously supplies the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the scan electrodes Y1 to Yn during the reset period. The scan driving circuit 32 sequentially supplies the scan pulses to the scan electrodes Y1 to Yn during the address period.

During the sustain period, the scan driving circuit 32 and the sustain driving circuit 33 alternately operate to supply the sustain pulses to the scan electrodes Y1 to Yn and the common sustain electrode Z.

4 illustrates a driving waveform of the PDP generated from the driving circuit shown in FIG. 3.

Referring to FIG. 4, during the reset period, the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down are simultaneously applied to all scan electrodes Y. FIG. Ramp-up causes a slight discharge in the cells of the full screen, resulting in wall charges in the cells of the full screen. Ramp-down generates a weak erase discharge in the cells, thereby eliminating unnecessarily excessive charges during wall charges and space charges generated by the setup discharge, thereby uniforming the wall charges required for address discharge in the cells of the full screen. Is left. After the reset period, positive wall charges are accumulated in the address electrodes X, and negative wall charges are accumulated in the scan electrodes Y and the sustain electrodes Z.

In the address period, a negative scan pulse (-scn) is sequentially applied to the scan electrodes (Y) and a positive data pulse (data) is applied to the address electrodes (X) so as to be synchronized with the scan pulse (-scn). do. As the voltage difference between the scan pulse (-scn) and the data pulse (data) and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse (data) is applied.

On the other hand, a positive DC voltage Zdc is supplied to the common sustain electrode Z during the period in which the falling ramp waveform Ramp-down is supplied and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the common sustain electrodes Z. FIG. Each time the sustain pulse (sus) is applied, the cell selected by the address discharge is a surface discharge form between the scan electrode (Y) and the common sustain electrode (Z) by adding the voltage of the wall voltage and the sustain pulse (sus) in the cell This causes a sustain discharge. At the end of the sustain period, an erase signal in the form of a ramp waveform for canceling the sustain discharge can be supplied.

However, the conventional PDP has a problem in that it is difficult to sufficiently maintain the sustain period when a subfield is added to increase the resolution accompanied by an increase in the number of lines and cells or to reduce contour noise in a moving image.

For example, assuming that one frame period is time-divided into 12 subfields and that the scan time required for one line is 2 μs, the address period per subfield is 2 μs (required for one line scan) in the resolution of VGA (852 × 480). Scan pulse width) x 480 = 0.96 ms. Assuming that the reset period required in each subfield is approximately 300 to 740 µs, the total reset period and address period required within one frame period are (0.96 ms x 12) + ((0.3 to 0.74 ms) x 12) = 15.12 to 20.4 ms. The sustain period except for the reset period and the address period is never shortened to 16.67 ms (frame period)-(15.12 to 20.4 ms) = 1.55 to 3.73 ms. Therefore, if 12 subfields are allocated within one frame period at the resolution of VGA, the luminance is low due to the absolute shortage of the sustain period, and if the number of subfields is added, the sustain period can be allocated within one frame period. Can not.

When the resolution is increased to XGA (1024 x 768), the address period per subfield takes 2 mu (the width of the scan pulse required for one line scan) x 768 = 1.536 ms. The reset period and the address period required within one frame period are (1.536 ms x 12) + ((0.3 to 0.74 ms) x 12) = 22.0 to 27.3 ms. The sustain period except for the reset period and the address period is 16.67 ms (frame period)-(22.0 to 27.3 ms) =-5.33 to -10.63 ms. Therefore, if 12 subfields are allocated in one frame in the XGA class, the display period, that is, the sustain period cannot be allocated, so that a resolution higher than XGA cannot be realized.

In order to solve the problem of lack of driving time, as shown in FIG. 5, a dual scan method for dividing the PDP 40 into the upper half and the lower half and simultaneously scanning the upper half and the lower half has been proposed and applied in some manufacturers. 6 shows a driving waveform of a dual scan method.

5 and 6, a conventional dual scan type PDP device includes a first data driving circuit 41A for supplying video data to address electrodes Xt1 to Xtm formed at an upper half of the PDP 40. And a second data driver circuit 41A for supplying video data to the address electrodes Xb1 to Xbm formed in the lower half of the PDP 40, and an initialization signal, scan pulses and sustain to the scan electrodes Y1 to Yn. A scan drive circuit 42 for supplying a pulse and a sustain drive circuit 43 for supplying a sustain pulse to the common sustain electrode Z are provided.

In the PDP 40, address electrodes Xt1 to Xtm and Xb1 to Xbm separated from the center are formed on the lower plate so that separate data can be simultaneously supplied to the upper half and the lower half. In addition, the scan electrodes Y1 to Yn and the common sustain electrode Z are formed on the upper surface of the PDP 40 so as to intersect the address electrodes Xt1 to Xtm and Xb1 to Xbm.

The first data driving circuit 41A provides video to the upper address electrodes Xt1 to Xtm to be synchronized with the scan pulse scn which is sequentially supplied to the first to n / 2 scan electrodes Y1 to Y2 / n. Supply the data.

The second data driving circuit 41B includes the lower address electrodes Xb1 to synchronously with the scan pulse scn sequentially supplied to the n / 2 + 1 to nth scan electrodes Yn / 2 + 1 to Yn. Xbm) is supplied with video data.

The scan driving circuit 42 simultaneously supplies the rising ramp waveform Ramp-up and the falling ramp waveform Ramp-down to the scan electrodes Y1 to Yn during the reset period. The scan driving circuit 42 simultaneously scans the upper half and the lower half of the PDP 40 during the address period. At this time, scan pulses (-scn) are simultaneously supplied to one scan electrode present in the upper half of the PDP 40 and one scan electrode present in the lower half of the PDP 40.

During the sustain period, the scan driving circuit 42 and the sustain driving circuit 43 alternately operate to supply the sustain pulse SUS to the scan electrodes Y1 to Yn and the common sustain electrode Z.

However, the conventional dual scan method can reduce the address period by about 2/1 as compared to the single scan method of the same resolution, but the data driving circuit 41A for driving the upper half of the address electrodes and the lower half for address electrodes Since the data driving circuit 41B is required, the number of integrated circuits IC increases, thereby increasing the cost of the data driving circuit and the PDP.

Accordingly, an object of the present invention is to provide a method and apparatus for scanning a PDP, which reduces the scan time and reduces the cost of the data driving circuit.

In order to achieve the above object, the scanning method of the PDP according to the embodiment of the present invention, the first electrode, the second electrode and the third electrode is formed and the first and second electrodes to supply the scan pulse to the first and second electrodes A method for scanning a plasma display panel having a scan / sustain driver, wherein cells are provided at intersections of the electrodes, the method comprising: supplying an initialization signal to at least one of the electrodes to form wall charges in the cell; Steps; Supplying the scan pulse to each of the first electrode and the second electrode simultaneously using a first and a second scan / sustain driver; Supplying data to the third electrode.

The PDP scanning method according to an embodiment of the present invention is characterized by simultaneously selecting cells included in at least two lines using scan pulses and wall charges.

delete

The scan pulse may be shifted sequentially for each line.

The scan method of the PDP according to the embodiment of the present invention further includes supplying a bias voltage which is a reference voltage of the scan pulse to the first and second electrodes.

The voltage of the data is set to an intermediate voltage between the scan pulse voltage and the bias voltage.

In the PDP scanning apparatus according to an embodiment of the present invention, a plasma display panel in which a first electrode, a second electrode, and a third electrode are formed and cells are provided at an intersection of the electrodes, at least one of the electrodes An initialization driver configured to supply an initialization signal to the cell to form wall charges in the cell; First and second scan / sustain drivers for simultaneously supplying scan pulses to the first electrode and the second electrode; And a data driver for supplying data to the third electrode.

The PDP scanning apparatus according to an embodiment of the present invention is characterized by simultaneously selecting cells included in at least two lines using scan pulses and wall charges.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 10.

Referring to FIG. 7, a driving apparatus of a PDP according to an embodiment of the present invention includes a data driving circuit 71 connected to address electrodes X1 to Xm, and a scan signal and a sustain to Y electrodes Y1 to Yn. A first scan / sustain drive circuit 72 for supplying a signal, a second scan / sustain drive circuit 73 for supplying a scan signal and a sustain signal to the Z electrodes Z, and each drive circuit 71 And a power generation unit 75 for supplying the driving voltages necessary for the 72, 73, and timing controllers 74 for controlling the respective driving circuits 71, 72, and 73.

The Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn of the PDP 70 are formed between neighboring cells on the upper substrate 81 as shown in FIG. 10. The address electrodes X1 to Xm of the PDP 70 are formed on the lower substrate 88 so as to intersect the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn. The top plate of the PDP 70 is provided with a dielectric layer 83 covering the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn, and an MgO protective film 84 formed on the dielectric layer 83. The lower plate of the PDP 7 is formed with a dielectric layer 86 covering the address electrodes X1 to Xm and partition walls 85 formed on the dielectric layer 86. The partition wall 85 may be formed in a stripe shape or a closed partition wall. In addition, a phosphor 89 is formed on the partition wall 85 and the dielectric layer 86 on the lower plate of the PDP 72.

The data driving circuit 71 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driving circuit 71 samples the data under the control of the timing controller 74, and then supplies the data to the address electrodes X1 to Xm for each line.

The first scan / sustain driving circuit 72 sequentially supplies negative scan pulses to the Y electrodes Y1 to Yn during the address period of each subfield under the control of the timing controller 74, During the sustain period, sustain pulses for supplying sustain discharge to the selected cells are supplied to the Y electrodes Y1 to Yn.

The second scan / sustain driving circuit 73 sequentially supplies negative scan pulses to the Z electrodes Z1 to Zn during the address period of each subfield under the control of the timing controller 74, Alternatingly with the first scan / sustain driving circuit 72 during the sustain period, the sustain pulse is supplied to the Z electrodes Z1 to Zm.

The power generator 75 is implemented as a DC-DC converter for converting a system power from a main board (not shown) into a pulse width modulation scheme or the like. The driving voltage output from the power generating unit 75 includes a reset voltage Vrst required for the reset period, a data voltage Va for the address period, a scan bias voltage V1, and a negative scan voltage (-Vsc). And the sustain voltage (Vs) necessary for the sustain period.

The timing controller 74 receives a vertical / horizontal synchronization signal and a clock signal, and generates timing control signals necessary for the driving circuits 71, 72, and 73 by using the synchronization signal and the clock signal.

8 illustrates a driving signal supplied in an address period in an arbitrary subfield to explain a scanning method of a PDP according to an embodiment of the present invention. 9 shows the wall charge distribution immediately after the reset period in any cell.

8 and 9, the PDP is driven by dividing into a reset period for initializing all cells, an address period for selecting cells, and a sustain period for maintaining discharge of the selected cells.

In the reset period, the rising ramp signal and the falling ramp signal shown in FIG. 4 or 6 are continuously supplied to the Y electrodes Y1 to Yn. By the rising ramp signal and the falling ramp signal, setup discharges and setdown discharges occur continuously in all cells. As shown in FIG. 9, negative wall charges are accumulated on the Y electrodes Y1 to Yn and Z electrodes Z1 to Zn, and positive wall charges are accumulated on the X electrodes X1 to Xm. The signals supplied in the reset period are not limited to the signals shown in FIG. 4 or 6, but may be any type of signal that satisfies the wall charge distribution condition as shown in FIG. 9. For example, the same waveform may be supplied to the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn as disclosed in Patent Application No. 2002-0024455 filed by the present applicant.

In the address period, a negative scan pulse (-scn) of -Vsc voltage is simultaneously supplied to a pair of Y electrodes Y1 to Yn and Z electrodes Z1 to Zn. The scan pulse -scn is sequentially shifted to the next Y electrodes Y1 to Yn and Z electrodes Z1 to Zn. For example, after the negative scan pulse (-scn) is simultaneously supplied to the first Z electrode Z1 and the first Y electrode Y1 during the first horizontal synchronizing period, the second Z electrode Z2 during the second horizontal synchronizing period. ) And the second Y electrode Y2 are simultaneously supplied with the negative scan pulse (-scn). The negative scan pulse (-scn) is simultaneously supplied to the nth Z electrode Zn and the nth Y electrode Yn during the nth horizontal synchronization period. In synchronization with the scan pulse (−scn), the data pulses of Va voltage are supplied to the m address electrodes X1 to Xm.

Here, the data voltage Va is set to an intermediate voltage between the scan bias voltage V1 and the negative scan voltage -Vsc. For example, when the scan bias voltage V1 is 200 [V] and the negative scan voltage -Vsc is -70 [V], the data voltage Va is set to 65 [V]. The case where address discharge occurs under such a voltage condition is as follows in conjunction with Table 1 and FIG. 10 below.

Address status ON OFF ON OFF Y -70 [V] -70 [V] 200 [V] 200 [V] Z 200 [V] -70 [V] -70 [V] 200 [V]

When -70 [V] is applied to the Y electrodes Y1 to Yn and 200 [V] is applied to the Z electrodes Y1 to Yn, the voltage on the Z electrodes Z1 to Zn is applied by the negative wall charge. This offset causes the voltage to be lower than 200 [V] and the voltage on the Y electrodes Y1 to Yn is higher than 200 [V] because the applied voltage is added by the negative wall charge. As a result, when a data voltage of 65 [V] is applied to the address electrodes X1 to Xm, address discharge occurs between the Y electrodes Y1 to Yn and the address electrodes X1 to Xm. By this address discharge, positive wall charges are accumulated on the Y electrodes Y1 to Yn, and negative wall charges are accumulated on the Z electrodes Z1 to Zn. Therefore, when the sustain pulse of the sustain voltage Vs is first supplied to the Y electrodes Y1 to Yn in the cell in which the address discharge has occurred, discharge may occur between the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn. Since more than a voltage difference is applied, a discharge occurs between the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn in each sustain pulse in the corresponding cell.

On the contrary, -70 [V] is applied to the Z electrodes Z1 to Zn, 200 [V] is applied to the Y electrodes Y1 to Yn, and a data voltage of 65 [V] is applied to the address electrodes X1 to Xm. When this is applied, an address discharge occurs between the Z electrodes Z1 to Zn and the address electrodes X1 to Xm. When a sustain pulse is first applied to the Z electrodes Z1 to Zn of the cell, a sustain discharge occurs.

If -70 [V] is applied to the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn during the address period and 65 [V] is applied to the address electrodes X1 to Xm, the Y electrodes Y1 to Yn. ) And between the address electrodes X1 to Xm or between the Z electrodes Z1 to Zn and the address electrodes X1 to Xm. This discharge causes positive wall charges to accumulate on the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn. When sustain pulses are alternately applied to the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn, positive wall charges are accumulated on both the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn. A voltage lower than the voltage difference between which the discharge can occur is applied between the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn so that sustain discharge does not occur.

On the contrary, if 200 [V] is applied to the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn during the address period, and 65 [V] is applied to the address electrodes X1 to Xm, the Y electrode ( No discharge occurs between Y1 to Yn and the address electrodes X1 to Xm or between the Z electrodes Z1 to Zn and the address electrodes X1 to Xm. Therefore, since the wall charge state of the reset period, i.e., the negative wall charges are accumulated on the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn, the Y electrodes Y1 to Yn are maintained in the cell. In addition, the voltage of the sustain pulses applied to the Z electrodes Z1 to Zn is lowered so that sustain discharge does not occur between the Y electrodes Y1 to Yn or the Z electrodes Z1 to Zn even when the sustain pulses are applied.

As described above, the PDP scanning method and apparatus according to the present invention apply scan pulses to the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn, so that the number of data driving circuits is not increased as in the conventional double scan method. Compared to the conventional single scan method, it is possible to scan twice as many lines at the same time.

As described above, the PDP scanning method and apparatus according to the present invention can scan two or more lines simultaneously by applying scan pulses to the Y electrodes Y1 to Yn and the Z electrodes Z1 to Zn, respectively. Furthermore, the method and apparatus for scanning a PDP according to the present invention can scan a high resolution PDP in a short time even with a single scan without adopting a double scan method that divides the screen and increases the data driving circuit.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view showing the electrode arrangement of a conventional three-electrode alternating surface discharge type plasma display panel.

2 is a diagram illustrating a frame structure of a conventional plasma display panel.

3 is a block diagram schematically illustrating a conventional single scan type plasma display panel device.

4 is a waveform diagram showing driving waveforms of a conventional single scan type plasma display panel.

5 is a block diagram schematically illustrating a conventional dual scan type plasma display panel device.

6 is a waveform diagram showing driving waveforms of a conventional dual scan type plasma display panel.

7 is a block diagram schematically illustrating a plasma display panel device according to an embodiment of the present invention.

8 is a waveform diagram illustrating driving waveforms required for scanning a plasma display panel according to an exemplary embodiment of the present invention.

9 is a cross-sectional view schematically illustrating the distribution of wall charges in a cell in a state in which a reset operation of the plasma display panel according to an exemplary embodiment of the present invention is completed.

FIG. 10 is a cross-sectional view schematically illustrating an address discharge when scan pulses are supplied to the Y and Z electrodes shown in FIG. 8.

<Description of Symbols for Main Parts of Drawings>

74: timing controller 71: data drive circuit

72,73: scan / sustain driving circuit 75: power generation unit

Claims (10)

A plasma display in which a first electrode, a second electrode, and a third electrode are formed and have first and second scan / sustain driving parts for supplying scan pulses to the first and second electrodes, and cells are provided at the intersections of the electrodes. In a method for scanning a panel, Supplying an initialization signal to at least one of the electrodes to form wall charges in the cell; Supplying the scan pulse to each of the first electrode and the second electrode simultaneously using a first and a second scan / sustain driver; Supplying data to the third electrode, And simultaneously selecting cells included in at least two lines by using the scan pulse and the wall charge. delete The method of claim 1, And the scan pulse is sequentially shifted for each line. The method of claim 1, And supplying a bias voltage which is a reference voltage of the scan pulse to the first and second electrodes. The method of claim 4, wherein And the voltage of the data is set to an intermediate voltage between the voltage of the scan pulse and the bias voltage. A plasma display panel in which a first electrode, a second electrode, and a third electrode are formed and cells are provided at an intersection of the electrodes. An initialization driver supplying an initialization signal to at least one of the electrodes to form wall charges in the cell; First and second scan / sustain drivers for simultaneously supplying scan pulses to the first electrode and the second electrode; A data driver configured to supply data to the third electrode; And simultaneously selecting cells included in at least two lines by using the scan pulse and the wall charge. delete The method of claim 6, And the scan pulse is sequentially shifted for each line. The method of claim 6, The first and second scan / sustain driving units, And a bias voltage which is a reference voltage of the scan pulse to the first and second electrodes. The method of claim 9, And the voltage of the data is set to an intermediate voltage between the voltage of the scan pulse and the bias voltage.