KR20040110689A - Method and apparatus for driving plasma display panel - Google Patents

Abstract

PURPOSE: A method and an apparatus for driving a PDP(Plasma Display Panel) are provided to increase driving speed of a PDP by expanding an address driving margin to reduce address time. CONSTITUTION: A first initializing waveform is provided to first and second electrodes to generate a first write discharge and a first erase discharge, thereby first-initializing cells which are formed at cross portions of electrodes. A second initializing waveform is provided to the first and second electrodes to generate a second write discharge and a second erase discharge, thereby initializing the cells. Data is provided to a third electrode and a scan pulse(scan) is provided to at least one of the first and second electrodes, thereby selecting the cells. A sustain pulse(sus) is alternatively provided to the first and second electrodes.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel which stabilizes initialization and reduces an address period.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. Electrodes X1 to Xm are provided.

Cells 1 for displaying any one of red, green and blue are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gradation according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by dividing into a reset period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the reset period, the rising ramp waveform Ramp-up is simultaneously supplied to all the scan electrodes Y in the setup period SU. At the same time, 0 [V] is supplied to the sustain electrode Z and the address electrode X. Dark discharge with little light generated between the scan electrode (Y) and the address electrode (X) and between the scan electrode (Y) and the sustain electrode (Z) in the cells of the full screen by the rising ramp waveform (Ramp-up) Dark discharge occurs. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

In the set-down period SD, after the rising ramp waveform Ramp-up is supplied, it starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up, thereby identifying the base voltage GND or the negative polarity. The falling ramp waveform Ramp-dn falling to the voltage level is simultaneously supplied to the scan electrodes Y. At the same time, the positive sustain voltage Vs is supplied to the sustain electrode Z, and 0 [V] is supplied to the address electrode X. When the falling ramp waveform Ramp-dn is supplied in this way, dark discharge is generated in which light is hardly generated between the scan electrode Y and the sustain electrode Z. Further, no discharge occurs between the scan electrode Y and the address electrode Z in the falling section of the falling ramp waveform Ramp-dn, and dark discharge occurs at the lower limit of the falling ramp waveform Ramp-dn. The discharge occurring in the set down period SD eliminates unnecessary wall charges unnecessary for the address discharge among the wall charges generated in the setup period SU. Looking at the wall charge change in the setup period SU and the setdown period SD, there is almost no wall charge change on the address electrode X, and the negative wall charge of the scan electrode Y decreases. On the other hand, the wall charge of the sustain electrode Z was positive in the set-up period SU, but the negative wall charge accumulated on itself as much as the decrease in the negative wall charge of the scan electrode Y was set-up period. At (SD), its polarity is reversed to negative polarity.

In the address period, the negative scan pulse scan is sequentially supplied to the scan electrodes Y, and the positive data pulse data is supplied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the cell to which the data pulse data is supplied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied. During this address period, the positive pole DC voltage Zdc is supplied to the sustain electrode Z.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is supplied with the wall voltage and the sustain pulse sus added in the cell. Is generated.

After the sustain discharge is completed, an erase ramp waveform (ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase wall charge remaining in the cells of the full screen.

In the conventional PDP, the discharge occurs between the scan electrode (Y) and the sustain electrode (Z) during the recess period and at the same time, the discharge occurs between the scan electrode (Y) and the address electrode (X). There is a problem that becomes unstable depending on the state of the wall charge or the composition of the discharge gas. In addition, in the conventional PDP, when the content of Xe in the discharge gas is increased to increase the efficiency, the delay time of the address discharge, that is, the address jitter value, becomes large, so that the address period becomes longer. As a result, the conventional PDP is unstable in initialization and difficult to drive at high speed.

Accordingly, it is an object of the present invention to provide a method and apparatus for driving a PDP that stabilizes initialization and reduces address periods.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform for driving a conventional PDP.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention.

FIG. 5 is a view schematically showing a change of wall charge distribution in a cell in the reset period shown in FIG. 4.

7 is a waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention.

7 is a waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention.

8 is a waveform diagram illustrating a method of driving a plasma display panel according to a third embodiment of the present invention.

9 is a waveform diagram illustrating a method of driving a plasma display panel according to a fourth embodiment of the present invention.

10 is a waveform diagram illustrating a method of driving a plasma display panel according to a fifth embodiment of the present invention.

11 is a waveform diagram illustrating a method of driving a plasma display panel according to a sixth embodiment of the present invention.

12 is a block diagram illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

121: timing controller 122: data driver

123: scan driver 124: sustain driver

125: drive voltage generator

In order to achieve the above object, a method of driving a PDP according to an embodiment of the present invention supplies a primary initialization waveform to a first electrode and a second electrode to cause a first write discharge and a first erase discharge to the cells, Primary initialization; Supplying a second initialization waveform to the first electrode and the second electrode to cause a second write discharge and a second erase discharge to the cells to initialize the cells secondly; Supplying data to third electrodes and supplying a scan pulse to at least one of the first and second electrodes to select the cells; And displaying sustain pulses by alternately supplying sustain pulses to the first electrodes and the second electrodes.

The first initialization waveform may include a first rising ramp waveform and a first falling ramp waveform supplied to the first electrode; And a square wave supplied to the second electrode in synchronization with the first falling ramp waveform.

The secondary initialization waveform includes a second rising ramp waveform and a second falling ramp waveform which are simultaneously supplied to the first electrode and the second electrode.

The voltage of the first rising ramp waveform and the second rising raft waveform supplied to the first electrode may be different.

The voltage of the first rising ramp waveform supplied to the first electrode is different depending on the subfields.

The supply period of the first rising ramp waveform supplied to the first electrode is different from the supply period of the second rising ramp waveform.

The supply period of the first rising ramp waveform supplied to the first electrode is different depending on the subfields.

The slope of the first rising ramp waveform and the second rising raft waveform supplied to the first electrode may be different from each other.

The slope of the first rising ramp waveform supplied to the first electrode is different depending on the subfields.

The slope of the second rising ramp waveform supplied to the first electrode is different depending on the subfield.

The driving method of the PDP according to the embodiment of the present invention supplies a first initialization waveform to the first electrode and the second electrode to cause a surface discharge between the first electrode and the second electrode and at the same time the first electrode and the Firstly initializing the cells by causing a counter discharge between at least one of the second electrodes and the third electrode; Supplying a secondary initialization waveform to the first electrode and the second electrode to cause a counter discharge between the first electrode and the third electrode, and at the same time to a counter discharge between the second electrode and the third electrode Secondly initializing the cells; Supplying data to the third electrodes and supplying a scan pulse to at least one of the first electrode and the second electrode to face at least one of the first electrode and the second electrode and the third electrode; Selecting a cell by causing a discharge; And displaying sustain pulses by alternately supplying sustain pulses to the first electrodes and the second electrodes to cause surface discharge between the first electrodes and the second electrodes.

The driving apparatus of the PDP according to the embodiment of the present invention supplies the first initialization waveform to the first electrode and the second electrode to cause the first write discharge and the first erase discharge to the cells, thereby initializing the cells and the first. An initialization driver for supplying a secondary initialization waveform to an electrode and the second electrode to cause secondary write discharge and secondary erase discharge to the cells to initialize the cells secondaryly; A cell selection driver supplying data to third electrodes and supplying a scan pulse to at least one of the first and second electrodes to select the cell; And a display driver for supplying sustain pulses alternately to the first electrodes and the second electrodes.

The initialization driver supplies a first rising ramp waveform and a first falling ramp waveform to the first electrode, and supplies a square wave synchronized with the first falling ramp waveform to the second electrode.

The initialization driver supplies a second rising ramp waveform and a second falling ramp waveform to the first electrode and the second electrode simultaneously.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 12.

4 and 5, the driving method of the PDP according to the first embodiment of the present invention includes a reset period for continuously supplying an initialization waveform to the scan electrodes Y twice, an address period for selecting a cell, And a sustain period for displaying the selected cell.

The reset period generates a discharge between the scan electrodes Y and the sustain electrodes Z, and also generates a primary reset period rst1 for generating a discharge between the scan electrodes Y and the address electrodes X. And a secondary reset period rst2 for generating a discharge between the scan electrodes Y and the address electrodes X and for generating a discharge between the sustain electrodes Y and the address electrodes X. FIG. .

During the initial t1 period of the first reset period rst1, the scan electrodes Y are supplied with a rising ramp waveform Ruy1 that rises at a predetermined slope from approximately sustain voltage Vs to the setup voltage Vsetup, and the sustain electrodes The ground voltage GND or 0V is supplied to the Z and the address electrodes X. Then, a write dark discharge occurs between the scan electrodes Y and the sustain electrodes Z in the cells of the full screen, and a write dark discharge occurs between the scan electrodes Y and the address electrodes X at the same time. . As a result of the first set-up discharge, negative wall charges are accumulated on the scan electrodes Y, and positive wall charges are accumulated on the sustain electrodes Z and the address electrodes X.

During the t2 period of the first reset period rst1, the falling ramp waveform Rdy1, which falls from the sustain voltage Vs to the negative voltage, is supplied to the scan electrodes Y, and the positive voltage is supplied to the sustain electrode Z. The square wave pulse of Rsq is supplied. Here, the negative voltage of the falling ramp waveform Rdy1 may be selected as the scan voltage Vscan, and the voltage of the square wave pulse Rsq may be selected as the sustain voltage Vs. During this t2 period, the address electrode X maintains 0 [V] or the ground voltage GND. Then, erase dark discharge is generated between the scan electrodes Y and the address electrodes X and between the scan electrodes Z and the sustain electrodes Z. As a result of this set down discharge, the wall charges on the respective electrodes X, Y, Z are partially erased.

This first reset period rst1 is a secondary reset period that is followed by uniformly stacking the negative wall charges on the scan electrodes Y and the sustain electrodes Z and the positive wall charges on the address electrodes. This will stabilize the initialization drive.

The base voltage GND or 0 [V] is supplied to the electrodes X, Y, and Z during the predetermined rest period after the first reset period rst is over.

During the initial t3 period of the second reset period rst2, the rising ramp waveform Ruy2 rising to the scan electrodes Y and the sustain electrodes Z at a predetermined slope from approximately the sustain voltage Vs to the setup voltage Vsetup. , Ruz) is supplied simultaneously. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. When the rising ramp waveforms Ruy2 and Ruz are simultaneously supplied to the scan electrodes Y and the sustain electrodes Z, the scan electrodes Y and the address electrodes X are formed in the first initialized cells. Second write dark discharge occurs simultaneously between the sustain electrodes Z and the address electrodes X. FIG. As a result, negative wall charges are accumulated on each of the scan electrodes Y and the sustain electrodes Z, and positive wall charges are accumulated on the address electrodes X. FIG.

During the t4 period of the second reset period rst2, the scan ramps Y are supplied with the falling ramp waveform Rdy2 that falls from the sustain voltage Vs to the negative voltage, and at the same time, the sustain electrodes Z are approximately sustained. The falling ramp waveform Rdz, which falls from the voltage Vs to 0 [V] or the ground voltage GND, is supplied. At this time, the address electrode X maintains 0 [V] or the ground voltage GND. The falling ramp waveforms Rdy2 and Rdz generate secondary erasure dark discharge between the scan electrode Y and the address electrode X and between the sustain electrode Z and the address electrode X. As a result of this secondary set-down discharge, unnecessary wall charges unnecessary for address discharge are erased. And uniform wall charges remain in all the cells.

In general, the red, green, and blue subpixels have a variation in the firing voltage according to the characteristics of the phosphor material. When the secondary falling ramp waveform Rdy2 supplied to the scan electrodes Y falls to the negative voltage, the discharge start condition can be made uniform regardless of the variation of the discharge start voltage appearing in the red, green, and blue subpixels. have. Therefore, the erase dark discharge by the second falling ramp waveform Rdy2 increases the driving margin by making the discharge conditions in all the cells uniform.

By the initialization of the secondary reset period, the PDP is maintained at 50 ° C because there is almost no potential difference between the scan electrodes Y and the sustain electrodes Z, and the wall charges formed on the electrodes Y and Z remain almost the same. Even when used in the above high temperature environment, no erroneous discharge caused by the wall charge fluctuation before the address discharge is started occurs.

As a result, the secondary reset period rst2 serves to stabilize the address drive and increase the drive margin by making all cells uniformly initialized.

Comparing the PDP of the present invention and the conventional PDP in the wall charge distribution after the reset period, the conventional PDP has a rising ramp waveform applied only to the scan electrodes Y as shown in FIG. 3 so that the scan electrodes Y and the sustain electrodes As a result of the surface discharge occurring between the electrodes Z, wall charges are accumulated only around the periphery of the scan electrodes Y and the sustain electrodes Z where the electric field is concentrated. In contrast, in the PDP of the present invention, the rising ramp waveforms Ruy1 and Ruz1 are simultaneously applied to the scan electrodes Y and the sustain electrodes Z in the second reset period rst so that the scan electrodes Y and the sustain are sustained. Since there is almost no potential difference between the electrodes Z, opposite discharges occur between the scan electrodes Y and the address electrodes X and between the sustain electrodes Z and the address electrodes X, thereby scanning electrodes. Wall charges are accumulated on almost the entire area of (Y) and the sustain electrodes (Z). For this reason, the PDP of the present invention sufficiently accumulates negative wall charges on the scan electrodes Y, and sufficiently accumulates positive wall charges on the address electrodes X, thereby providing the scan voltage Vscan and data necessary for address discharge. The voltage Vd can be lowered and the delay of address discharge can be reduced.

During the address period, the positive bias voltages Vscan-com and Vz-com are supplied to the scan electrodes Y and the sustain electrodes Z. FIG. Scan pulses falling from the bias voltage Vscan-com to the scan voltage Vscan are sequentially supplied to the scan electrodes Y, and the data pulses of the data voltage Vd are synchronized with the scan pulses. Is supplied to the address electrodes (X). The bias voltages Vscan-com and Vz-com supplied to the scan electrodes Y and the sustain electrodes Z may be set identically or differently. For example, when the bias voltage Vz-com supplied to the sustain electrodes Z is set to be higher than the bias voltage Vscan-com supplied to the scan electrodes Z, the sustain voltage Z is further applied to the sustain electrodes Z during the address period. Large amounts of negative wall charges can accumulate. When a large amount of negative wall charges are accumulated on the sustain electrodes Z, the first sustain pulse su is supplied between the sustain electrodes Z and the scan electrodes Y when the first sustain pulse su is supplied to the sustain electrodes Z. Since the voltage difference becomes larger, discharge is easy and stable, and thus the sustain driving margin is increased. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the reset period are added, an address discharge is generated in the on-cell to which the data pulse is supplied. In the on-cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is supplied.

In the sustain period, sustain pulses sus are alternately supplied to the scan electrodes Y and the sustain electrodes Z. FIG. In the on-cells selected by the address discharge, a sustain voltage is generated between the scan electrode Y and the sustain electrode Z every time the sustain pulse sus is supplied as the wall voltage and the sustain pulse sus in the cell are added.

After the last sustain pulse sus is supplied to the sustain electrodes Z and the sustain discharge is completed, the erase ramp waveforms ersy and ersz are continuously supplied to the scan electrodes Y and the sustain electrodes Z. . The erase ramp waveforms ersy and ersz serve to erase wall charges generated by the sustain discharge. The erase ramp waveforms ersy and ersz may be supplied to one of the scan electrode Z and the sustain electrode Z, or may be omitted. For example, Patent Application No. 10-2000-0012669, Patent Application No. 10-2000-0053214, Patent Application No. 10-2001-0003003, Patent Application No. 10-2001-0006492, Patents, filed by the applicant of the present application In the so-called 'SWSE (Selective Witing and SelectiveErasure) method' proposed through the application 10-2002-0082512, the patent application 10-2002-0082513, the patent application 10-2002-0082576, etc. When the present invention is applied, the erase ramp waveforms ersy and ersz are omitted in the last subfield of the selective write subfield.

6 shows a method of driving a PDP according to a second embodiment of the present invention.

Referring to FIG. 6, the driving method of the PDP according to the second embodiment of the present invention controls the initialization voltage differently according to subfields arranged in one frame period.

In the m (where m is any positive integer) subfield, the primary reset period rst1 includes a t1 period and a t2 period. In the t1 period, the first rising ramp waveform Ruym1, which rises from the sustain voltage Vs to the setup voltage Vsetup, is supplied to the scan electrodes Y, and the sustain electrodes Z are supplied with the ground voltage GND or zero. [V] is supplied. In the t2 period, the first falling ramp waveform Rdym1 that drops from the sustain voltage Vs to the negative voltage is supplied to the scan electrodes Y and the square wave pulse Rsq of the positive voltage is supplied to the sustain electrodes Z. Is supplied.

In the m th subfield, the secondary reset period rst2 includes a t3 period and a t4 period. In this secondary reset period rst2, the same waveform as the primary reset period rst1 is supplied to the scan electrodes Y. FIG. On the other hand, the sustain electrodes Z are supplied with the rising ramp waveform Rumym1 rising up to the setup voltage Vsetup during the t3 period, and the sustain voltage Vs is approximately the ground voltage GND or 0 [V] during the t4 period. A descending ramp waveform Rdz is supplied which descends to.

In the nth subfield, where n is a positive integer different from m, in the first reset period rst1 of the reset period, the second setup voltage Vsetup2 different from the setup voltage Vsetup is applied to the scan electrodes Y. Is supplied and the setup voltage Vsetup is supplied to the scan electrodes Y in the second reset period rst2. Here, the second setup voltage Vsetup2 is lower than the setup voltage Vsetup. The sustain electrodes Z are supplied with the same waveform as the reset period of the mth subfield during the reset period of the nth subfield.

During the reset periods of the mth subfield and the nth subfield, the base voltage GND or 0 [V] is supplied to the address electrodes X.

In the mth subfield and the nth subfield, the driving waveforms of the address period and the sustain period and the operations thereof are substantially the same as in the previous embodiment, and thus a detailed description thereof will be omitted.

This embodiment increases the contrast by lowering the setup voltage of at least one subfield among the plurality of subfields arranged within one frame period in order to increase the contrast. That is, the driving method of the PDP according to the second embodiment of the present invention lowers the voltage of the rising ramp waveform in some subfields in the primary initialization waveform to stabilize the initialization drive of the secondary reset, thereby weakening the setup discharge. If the setup discharge occurs weakly, the amount of light emission in the cell decreases as much, so that the black level is lowered at the contrast ratio, resulting in higher contrast characteristics.

The m th subfield may be selected as at least one subfield disposed initially among the subfields arranged within one frame period, and the n th subfield may select the m th subfield among the subfields arranged within one frame period. At least one subfield may be selected. In addition, the m th subfield and the n th subfield may be alternately or periodically arranged.

Although not shown, the PDP driving method according to the second embodiment of the present invention may control not only the setup voltage of the first reset period but also the setup voltage of the second reset period according to the subfield.

7 shows a method of beating a PDP according to a third embodiment of the present invention.

Referring to FIG. 7, the driving method of the PDP according to the third embodiment of the present invention controls the reset period differently according to the subfields arranged within one frame period.

The m th subfield is substantially the same as the m th subfield of FIG. 6.

The first reset period rstn1 of the nth subfield is set smaller than the first reset period rstm1 of the mth subfield in order to improve contrast and reduce driving time. To this end, the slope of the first rising ramp waveform Ruyn1 supplied to the scan electrodes Y during the first reset period rstn1 of the nth subfield is equal to the first rising ramp waveform Ruym1 of the mth subfield. The sustain period during which the setup voltage Vsetup is the same and is shorter than the first rising ramp waveform Rumym1 of the mth subfield. The driving waveforms supplied to the scan electrodes Y during the second reset period rstn2, the address period, and the sustain period of the nth subfield are substantially the same as the mth subfield.

The same waveforms as the mth subfield are supplied to the sustain electrodes Z during the nth subfield.

During the reset periods of the mth subfield and the nth subfield, the base voltage GND or 0 [V] is supplied to the address electrodes X.

The m th subfield may be selected as at least one subfield disposed initially among the subfields arranged within one frame period, and the n th subfield may select the m th subfield among the subfields arranged within one frame period. At least one subfield may be selected. In addition, the m th subfield and the n th subfield may be alternately or periodically arranged.

8 shows a method of beating a PDP according to a fourth embodiment of the present invention.

Referring to FIG. 8, the driving method of the PDP according to the fourth embodiment of the present invention controls the initialization voltage and the reset period differently according to subfields arranged within one frame period.

The m th subfield is substantially the same as the m th subfield of FIG. 6.

The first reset period rstn1 of the nth subfield is set smaller than the first reset period rstm1 of the mth subfield in order to improve contrast and reduce driving time, and the first rising ramp having a low setup voltage Vsetup2. The waveforms Rdyn1 are supplied to the scan electrodes Z. To this end, the first rising ramp waveform Ruyn1 supplied to the scan electrodes Y during the first reset period rstn1 of the nth subfield starts to rise from approximately the sustain voltage Vs, and thus, The same slope as the first rising ramp waveform Ruym1 is increased to the second setup voltage Vsetup2 lower than the setup voltage Vsetup. The driving waveforms supplied to the scan electrodes Y during the second reset period rstn2, the address period, and the sustain period of the nth subfield are substantially the same as the mth subfield.

The same waveforms as the mth subfield are supplied to the sustain electrodes Z during the nth subfield.

During the reset periods of the mth subfield and the nth subfield, the base voltage GND or 0 [V] is supplied to the address electrodes X.

The m th subfield may be selected as at least one subfield disposed initially among the subfields arranged within one frame period, and the n th subfield may select the m th subfield among the subfields arranged within one frame period. At least one subfield may be selected. In addition, the m th subfield and the n th subfield may be alternately or periodically arranged.

9 illustrates a method of beating a PDP according to a fifth embodiment of the present invention.

9, the driving method of the PDP according to the fifth embodiment of the present invention takes the rising ramp waveform in each of the first reset period rst1 and the second reset period rst2 in consideration of the contrast characteristics and the stabilization of the initialization drive. The slopes of (Ruym1, Ruym2, Ruyn1, Ruyn2) and falling ramp waveforms (Rdym1, Rdym2, Rdyn1, Rdyn2) are controlled differently.

In the t1 period of the first reset period rst1, the first rising ramp waveform Ruym1, which rises from the sustain voltage Vs to the setup voltage Vsetup, is supplied to the scan electrodes Y, and the sustain electrodes Z are supplied. The ground voltage (GND) or 0 [V] is supplied to the. In the t2 period, the first falling ramp waveform Rdym1 that drops from the sustain voltage Vs to the negative voltage is supplied to the scan electrodes Y and the square wave pulse Rsq of the positive voltage is supplied to the sustain electrodes Z. Is supplied. The slope of the first rising ramp waveform Ruym1 and the first falling ramp waveform Rdym1 may be adjusted in consideration of the uniformity of the cell under contrast characteristics and initial conditions of the second reset period.

In the m-th subfield, in the t3 period of the second reset period rst2, the first rising ramp waveform rising from the sustain voltage Vs to the setup voltage Vsetup at a different slope from the first rising ramp waveform Rupm1. Rumym1 is supplied to the scan electrodes Y, and the ground voltage GND or 0 [V] is supplied to the sustain electrodes Z. In the period t4, the first falling ramp waveform Rdym1, which drops from the sustain voltage Vs to the negative voltage at a different slope than the first rising ramp waveform Rupm1, is supplied to the scan electrodes Y and the sustain electrodes ( Square wave pulses Rsq of positive voltage are supplied to Z). The slopes of the second rising ramp waveform Ruym2 and the second falling ramp waveform Rdym2 are selected in consideration of the initialization uniformity of cells and stabilization of address driving.

The rising ramp waveforms Ruyn1 and Ruyn2 and the falling ramp waveforms Rdyn1 and Rdyn2 of the nth subfield are initialized waveforms generated in the mth subfield in consideration of contrast characteristics and initialization uniformity of the driving speed cell. The scan electrodes Y may be supplied at different inclinations from Ruyn1, Ruyn2, Rdyn1, and Rdyn2.

10 and 11 illustrate a method of beating the PDP according to the sixth and seventh embodiments of the present invention.

10 and 11, the driving method of the PDP according to the first embodiment of the present invention includes the setdown voltages V1 and V3 of the first reset period rst1 and the second reset period in consideration of the contrast characteristics and the stabilization of the initialization drive. The setdown voltages V2 and V4 of rst2 are different.

Since the t1 period of the first reset period rst1, the t3 period of the second reset period rst2, the address period and the sustain period are substantially the same as those of the embodiment of FIG. 4, a detailed description thereof will be omitted.

When the setdown voltage V1 of the first falling ramp waveform Rdy1 supplied to the scan electrodes Y is lowered as shown in FIG. 10 during the t2 period of the first reset period rst1, the first erase dark discharge is increased by that much. It occurs larger and as a result, the wall charge uniformity on the scan electrodes Y and the sustain electrodes Z in all the cells before the second reset period is further improved. Therefore, the initialization uniformity of the secondary reset period is improved, and the secondary reset operation is more stabilized.

In contrast, when the set down voltage V4 of the second falling ramp waveform Rdy2 supplied to the scan electrodes Y is lowered as shown in FIG. 11 during the t2 period of the second reset period rst2, the second erase dark discharge is performed. This occurs much larger and as a result, the wall charge uniformity on the scan electrodes Y and the sustain electrodes Z in all the cells before the address period is further improved. Therefore, the uniformity of initialization of the secondary reset period is improved and the address operation is more stabilized.

10 and 11, the setdown voltage of the nth subfield may be set differently from the setdown voltage of the mth subfield in consideration of contrast characteristics and initialization uniformity of the driving speed cell.

12 shows an apparatus for driving a PDP according to an embodiment of the present invention.

Referring to FIG. 12, a driving apparatus of a PDP according to an embodiment of the present invention uses a data driver 122 for supplying data to address electrodes X1 to Xm of the PDP, and scan electrodes Y1 to Yn. A scan driver 123 for driving, a sustain driver 124 for driving the sustain electrode Z as a common electrode, a timing controller 121 for controlling each of the driving units 122, 123, and 124, and A driving voltage generator 125 is provided to supply driving voltages necessary for the driving units 122, 123, and 124.

The data driver 122 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 122 samples and latches data in response to the timing control signal CTRX from the timing controller 121, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 123 controls the initialization waveforms Ruy1, Rdy1, Ruy2, Rdy2, Ruym1, Rdym1, Ruym2, Rdym2, Ruyn1, Rdyn1, Ruyn2 during the reset period under the control of the timing controller 121. At least one of Rdyn2 is supplied to the scan electrodes Y1 to Yn. The scan driver 123 sequentially supplies the scan pulses to the scan electrodes Y1 to Yn during the address period, and the sustain pulses to the scan electrodes Y1 to Yn during the sustain period.

The sustain driver 124 supplies the initialization waveforms Rsq, Ruz, and Rdz shown in FIGS. 6 to 11 to the sustain electrodes Z during the reset period under the control of the timing controller 121. In addition, the sustain driver 124 supplies the bias voltage Vz-com to the sustain electrodes Z during the address period, and alternately operates with the scan driver 123 during the sustain period, thereby sustaining the sustain pulses Z. Will be supplied to

The timing controller 121 receives the vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRY, and CTRZ required for each driving unit, and transmits the timing control signals CTRX, CTRY, and CTRZ to the corresponding driving units 122, 123, and the like. Each driving unit 122, 123, 124 is controlled by supplying the same to the 124. The data control signal CTRX includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element. The scan control signal CTRY includes a switch control signal for controlling on / off time of the energy recovery circuit and the driving switch element in the scan driver 123. The sustain control signal CTRZ includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 124.

The driving voltage generator 125 may include setup voltages Vsetup and Vsetup2, address bias voltages Vscan-com and Vz-com, scan voltages Vscan, sustain voltages Vs, and setdown voltages V1 to V4 and Vz. The data voltage Vd is generated. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

As described above, the method and apparatus for driving a PDP according to the present invention supply almost the same waveform to the scan electrodes and the sustain electrodes to ensure uniformity in all cells and stabilize the driving of the initialization discharge before initializing the cells of the PDP. In order to perform the first initialization for the cells. As a result, the method and apparatus for driving a PDP according to the present invention enables the PDP to be driven at high speed by stabilizing the initialization of the PDP and increasing the address driving margin to reduce the address period.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (21)

A plasma display panel including an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersect the plurality of electrode pairs are formed, and cells are formed at the intersections of the electrodes. In the method for Supplying a first initialization waveform to the first electrode and the second electrode to cause a first write discharge and a first erase discharge to the cells, thereby initializing the cells; Supplying a second initialization waveform to the first electrode and the second electrode to cause a second write discharge and a second erase discharge to the cells to initialize the cells secondly; Supplying data to the third electrodes and supplying a scan pulse to at least one of the first and second electrodes to select the cells; And supplying sustain pulses alternately to the first electrodes and the second electrodes to perform a display. The method of claim 1, The primary initialization waveform is, A first rising ramp waveform and a first falling ramp waveform supplied to the first electrode; And a square wave supplied to the second electrode in synchronization with the first falling ramp waveform. The method of claim 2, The secondary initialization waveform, And a second rising ramp waveform and a second falling ramp waveform supplied simultaneously to the first electrode and the second electrode. The method of claim 3, wherein And the voltage of the first rising ramp waveform and the second rising raft waveform supplied to the first electrode are different. The method of claim 4, wherein And the voltage of the first rising ramp waveform supplied to the first electrode is different depending on the subfields. The method of claim 3, wherein And a supply period of the first rising ramp waveform supplied to the first electrode is different from a supply period of the second rising ramp waveform. The method of claim 6, And a supply period of the first rising ramp waveform supplied to the first electrode is different depending on the subfields. The method of claim 3, wherein And a slope of the first rising ramp waveform and the second rising raft waveform supplied to the first electrode is different. The method of claim 8, The slope of the first rising ramp waveform supplied to the first electrode is different depending on the subfields. The method of claim 8, And a slope of the second rising ramp waveform supplied to the first electrode is different depending on a subfield. A plasma display panel including an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersect the plurality of electrode pairs are formed, and cells are formed at the intersections of the electrodes. In the method for By supplying a primary initialization waveform to the first electrode and the second electrode to cause a surface discharge between the first electrode and the second electrode, at least one of the first electrode and the second electrode and the second electrode Firstly initializing the cells by causing an opposite discharge between three electrodes; Supplying a secondary initialization waveform to the first electrode and the second electrode to cause a counter discharge between the first electrode and the third electrode, and at the same time to a counter discharge between the second electrode and the third electrode Secondly initializing the cells; Supplying data to the third electrodes and supplying a scan pulse to at least one of the first electrode and the second electrode to face at least one of the first electrode and the second electrode and the third electrode; Selecting a cell by causing a discharge; And supplying sustain pulses alternately to the first electrodes and the second electrodes to cause surface discharge between the first electrodes and the second electrodes, thereby performing display. How to drive the panel. A plasma display panel including an upper plate on which a plurality of electrode pairs including first and second electrodes are formed, and a lower plate on which a plurality of third electrodes intersect the plurality of electrode pairs are formed, and cells are formed at the intersections of the electrodes. In the device for The primary initialization waveform is supplied to the first electrode and the second electrode to cause the first write discharge and the first erase discharge to the cells, thereby initializing the cells and the second to the first electrode and the second electrode. An initialization driver for supplying an initialization waveform to cause secondary write discharge and secondary erase discharge to the cells to initialize the cells secondaryly; A cell selection driver supplying data to the third electrodes and supplying a scan pulse to at least one of the first and second electrodes to select the cell; And a display driver for supplying sustain pulses alternately to the first electrodes and the second electrodes to perform the display. The method of claim 12, The initialization driver, And a first rising ramp waveform and a first falling ramp waveform are supplied to the first electrode, and a square wave synchronized with the first falling ramp waveform is supplied to the second electrode. The method of claim 13, The initialization driver, And a second rising ramp waveform and a second falling ramp waveform are simultaneously supplied to the first electrode and the second electrode. The method of claim 14, And a voltage of the first rising ramp waveform and the second rising raft waveform supplied to the first electrode is different. The method of claim 15, And the voltage of the first rising ramp waveform supplied to the first electrode is different depending on the subfields. The method of claim 14, And a supply period of the first rising ramp waveform supplied to the first electrode and a supply period of the second rising ramp waveform differ from each other. The method of claim 17, And a supply period of the first rising ramp waveform supplied to the first electrode is different depending on the subfields. The method of claim 14, And a slope of the first rising ramp waveform and the second rising raft waveform supplied to the first electrode is different from each other. The method of claim 19, The slope of the first rising ramp waveform supplied to the first electrode is different depending on the subfields. The method of claim 19, And a slope of the second rising ramp waveform supplied to the first electrode is different depending on a subfield.