KR100456152B1 - Method and apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel to prevent erroneous discharge in a high temperature environment.

The present invention relates to a method of driving a plasma display panel divided into an initialization period and an address period and a sustain period divided by a setup period and a setdown period, the method comprising: detecting a temperature of the panel and using a setdown voltage to display cells of a full screen; Initializing and adjusting a voltage level of the set down voltage before an address period for selecting a cell according to the detected temperature is started.

According to the present invention by the driving method, the temperature of the plasma display panel is detected and the voltage level of the setdown voltage is set according to the detected temperature. In addition, according to the characteristics of the circuit component for supplying the setdown voltage in a high temperature environment, the setdown voltage is forcibly raised to a desired voltage level before the address is started. Accordingly, the method and apparatus for driving a PDP according to the present invention can prevent mis-discharge in a high temperature environment by setting an optimal address operating condition before the set-down voltage starts addressing regardless of temperature change.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel to prevent erroneous discharge in a high temperature environment.

Plasma Display Panel (hereinafter referred to as "PDP") is used to excite and emit phosphors by using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Will be displayed. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP has an address orthogonal to the scan electrodes Y1 to Yn and the sustain electrode Z, and the scan electrodes Y1 to Yn and the sustain electrode Z. Electrodes X1 to Xm are provided.

Cells 1 for displaying any one of red, green and blue are formed at the intersections of the scan electrodes Y1 to Yn, the sustain electrode Z and the address electrodes X1 to Xm. The scan electrodes Y1 to Yn and the sustain electrode Z are formed on an upper substrate (not shown). On the upper substrate, a dielectric layer and an MgO protective layer (not shown) are stacked. The address electrodes X1 to Xm are formed on the lower substrate (not shown). On the lower substrate, partition walls are formed to prevent optical and electrical interference between horizontally adjacent cells. Phosphors are excited on the lower substrate and the partition walls to be excited by vacuum ultraviolet rays and emit visible light. An inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is injected into the discharge space between the upper substrate and the lower substrate.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2,3,4,5,6) in each subfield. , 7).

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform (Ramp-up) causes a discharge in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. In the set-down period SD, after the rising ramp waveform Ramp-up is supplied, it starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up, thereby identifying the base voltage GND or the negative polarity. A falling ramp waveform Ramp-down falling to the voltage level is simultaneously applied to the scan electrodes Y. Ramp-down causes a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period, the negative scan pulse scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse scan. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied.

The sustain electrode Z is supplied with a positive polarity DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference between the scan electrode Y and the erroneous discharge with the scan electrode Y.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse sus is applied as the wall voltage and the sustain pulse sus are added. This will happen.

After the sustain discharge is completed, ramp waveforms having a small pulse width and a low voltage level are supplied to the sustain electrode Z to erase wall charges remaining in the cells of the full screen.

4 shows a conventional scan electrode driving circuit, and FIG. 5 shows output signals from the scan electrode driving circuit.

4 and 5, the conventional scan electrode driving circuit includes a scan driver 41 connected with a scan electrode Y and having a high potential scan voltage Vsc and a low potential scan voltage (−Vy); A bias detector 42 connected to the scan driver 41 is provided. The low potential scan voltage (-Vy) is a base voltage GND or a specific voltage of negative polarity.

The scan driver 41 is connected in a push-pull form and switches QH of a drive integrated circuit 43 (hereinafter referred to as " IC ") connected to the scan electrode Y through an output node therebetween. , QL and the third switch Q3 connected to the driving IC 43 via the first node n1 and input with the high potential scan voltage Vsc, and the second node n2. A second switch Q2 connected to the IC 43 and to which a low potential scan voltage (-Vy) is input; a fourth switch Q4 connected between the first and second nodes n1 and n2; A first switch Q1 is connected between the two nodes n2 and the negative scan voltage source -Vy.

The first switch QH of the driver IC 43 supplies the scan electrode Y with the high potential scan voltage Vsc supplied via the first node n1, and the second switch of the driver IC 43. QL supplies the scan electrode Y with a setdown voltage or a low potential scan voltage -Vy supplied via the second node n2. The third switch Q3 is turned on during the address period to supply the high potential scan voltage Vsc to the first node n1. The second switch Q2 is turned on during the setdown period SD to supply the second node n2 with a voltage falling to the low potential scan voltage -Vy at a predetermined falling slope determined by the RC time constant. do. The first switch Q1 is turned on during the address period to supply the low potential scan voltage -Vy to the second node n2. The fourth switch Q4 is turned on during the address period to open a current path between the first node n1 and the second node n2 to insulate between the first node n1 and the second node n2. It plays a role.

The bias detector 42 includes a zener diode ZD connected between the second node n2 and the low potential scan voltage source (-Vy), the first and second voltage divider resistors R1 and R2, and the common voltage source Vcc. And third and fourth voltage divider resistors R3 and R4 connected between the low potential scan voltage source -Vy and the comparator 44 connected to the third and fourth nodes n3 and n4.

The first and second voltage divider resistors R1 and R2 divide the voltage on the second node n2 with a predetermined voltage divider resistance ratio and supply the divided voltage Vd to the non-inverting terminal (+) of the comparator 44. . The third and fourth voltage divider resistors R3 and R4 divide the common voltage Vcc by a predetermined voltage divider resistance ratio to generate a reference voltage Vr, and convert the reference voltage Vr into an inverting terminal () of the comparator 44. Supply to-). The reference voltage Vr is set to a voltage in FIG. 5 such that the setdown voltage no longer falls at the -Vyb potential.

The comparator 44 generates a low logic output signal when the set-down detection voltage Vd input to the non-inverting terminal + is greater than the reference voltage Vr (Vd> Vr), and generates a non-inverting terminal (+). When the input setdown detection voltage Vd is equal to or lower than the reference voltage Vr (Vd ≦ Vr), a high logic output signal is generated.

The output signal of the comparator 44 is inverted from low logic to high logic at the beginning of the address period. The timing controller (not shown) turns on the first and third switches Q1 and Q3 and turns off the fourth switch Q4 in response to the high logic output signal of the comparator 44 as shown in FIG. 5. The operating conditions of the address are set by preventing the setdown voltage from dropping below the -Vyb potential. This stop of the setdown voltage at the -Vyb potential is such that an address discharge can occur when the low potential scan voltage (-Vy) and the data voltage (data) are applied to the scan electrode (Y) and the address electrode (X). To leave sufficient wall charge in the cell. The scan pulse scan is supplied to the scan electrodes Y from the time t3 set after the address operation condition is set. That is, from time t3, the switches QH and QL of the driving IC 43 repeatedly turn on / off the scan pulses to supply the scan electrodes Y to each other.

On the other hand, when the conventional PDP is operated in a high temperature environment of 50 ℃ or more as shown in Figure 6 the slope of the ramp ramp (Ramp-down) is smaller than the normal temperature environment. It is estimated that the setdown change in the high temperature environment is caused by the change of wall charge loss and operating conditions in the cell between the normal temperature environment and the high temperature environment.

6 is a waveform diagram showing a change in setdown in a high temperature environment.

In FIG. 6, the solid line shows the ramp ramp down of the normal slope which appears in the normal temperature environment, and the dotted line shows the ramp ramp down that the slope becomes smaller in the high temperature environment of 50 ° C or higher.

Referring to FIG. 6, in the normal temperature environment, when the set-down voltage due to the ramp-down ramp down to the ground voltage GND falls at the time t0, the ramp ramp becomes gentle in the high temperature environment. down only falls to an arbitrary voltage level Vdn higher than the ground voltage GND at time t0. As a result, the conventional PDP is a wall accumulated by the setup discharge generated between the scan electrode (Y) and the sustain electrode (Z) and between the scan electrode (Y) and the address electrode (X) by the rising ramp waveform (Ramp-up) Unnecessary wall charges in the address discharge in the charge are not completely erased and remain in the cell by Vdn. Thus, wall charge remaining in the cell unnecessarily much before the address starts may cause an erroneous discharge even when no data voltage data is applied to the address electrode Z, which can cause an address discharge.

The high temperature mis-discharge phenomenon of the conventional PDP refers to a problem in which a cell that is turned off at the center of the screen occurs when the PDP is operated at a high ambient temperature of about 50 to 70 ° C. These high temperature misfires result from the loss of wall charges during the address period as a result of many experiments and analysis of the experiments. The reason for this is explained based on the change of discharge characteristics in the cell. First, as the internal / external temperature of the cell rises, the insulation characteristics of the dielectric material and the protective layer material in the cell deteriorate, and leakage current occurs and the wall charges leak. . In particular, when the wall charges of the scan electrode Y and the common sustain electrode Z leak, the address discharge is likely to be miss discharged. Second, as the movement of the space charges in the cell caused by the discharge in the high temperature environment becomes active, recombination between the space charge and the electron-lost atom occurs easily, and the wall charges and space charges that contribute to the discharge have a long time. It is lost over time.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a plasma display panel to prevent erroneous discharge in a high temperature environment.

1 is a plan view schematically showing an electrode arrangement of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a frame configuration of an 8-bit default code for implementing 256 gray levels.

3 is a waveform diagram showing a drive waveform for driving a conventional PDP.

4 is a circuit diagram showing a conventional scan electrode driving circuit.

FIG. 5 is a waveform diagram illustrating output signals from the scan electrode driving circuit shown in FIG. 4.

6 is a waveform diagram showing a change in inclination due to high temperature in a conventional falling ramp waveform.

FIG. 7 is a waveform diagram illustrating a setdown voltage changed by a method and apparatus for driving a plasma display panel according to a first embodiment of the present invention.

8 is a circuit diagram illustrating a driving apparatus of a plasma display panel according to a first embodiment of the present invention.

9 is a waveform diagram illustrating a setdown voltage changed by a method and an apparatus for driving a plasma display panel according to a second exemplary embodiment of the present invention.

10 is a circuit diagram illustrating an apparatus for driving a plasma display panel according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

41, 61, 81: scan driver 42, 62, 82: bias detector

43, 63, 83: drive IC 64, 66, 84, 86: comparator

68: switching block 70: temperature sensor

87, 88 AND gate 89: OR gate

In order to achieve the above object, a method of driving a plasma display panel according to an embodiment of the present invention come located in the driving method of the plasma display panel divided into the initialization period and the address and the sustain period are divided into a setup period and a set-down period, the Detecting the temperature of the panel; initializing the cells of the full screen using the setdown voltage; and if the detected temperature is room temperature, the first voltage level of the setdown voltage immediately before the address period starts. The voltage level is set. If the temperature is 50 ° C or higher, the second voltage level is set. The second voltage level may be higher than the first voltage level. The adjusting of the voltage level of the setdown voltage may include comparing the voltage level of the setdown voltage with the first voltage level to obtain a first control signal. Generating a second control signal by comparing the voltage level of the set-down voltage with the second voltage level, and selecting one of the first and second control signals according to the detected temperature. Generating a setdown control signal and forcibly raising a voltage level of the setdown voltage according to the setdown control signal to indicate the address period. Driving of the plasma display panel according to an embodiment of the present invention. The method initializes full screen cells using a setdown voltage with a slope falling to either the room temperature region or the high temperature region . Selecting either one of the voltage level of the first voltage level or the second voltage in accordance with the L'screen; and the set-down area where the voltage is lowered to, and including the step of raising the voltage of the scan electrodes in the selected voltage. The setdown voltage having the slope falling to the room temperature region is forcibly increased in the voltage of the scan electrode at the first voltage level. The setdown voltage having the slope descending to the high temperature region is the scan electrode at the second voltage level. The first voltage level is lower than the second voltage level. The step of raising the set-down voltage to one of the first and second voltage levels includes: Generating a first reference control signal having a high logic state after the second area and a low logic state in other periods, and having a high logic state during the first and second areas and a low logic state in other periods. Generating a second reference control signal having a first reference control signal; Generating a third reference control signal, comparing the voltage level of the setdown voltage with the first voltage level, generating a first control signal, comparing the voltage level of the setdown voltage with the second voltage level Generating a second control signal, generating a first output signal by performing a logical multiplication on the first control signal and the first reference control signal, and performing a logical multiplication on the second control signal and the second reference control signal. Generating a second output signal; generating the setdown control signal by logically combining the first and second output signals; and raising the setdown voltage in response to the setdown control signal. And supplying a high potential voltage of a scan pulse in response to the third reference control signal. The apparatus for driving a plasma display panel according to the present invention includes a temperature detector for detecting a temperature of the panel , a voltage level of a setdown voltage immediately before the address period starts, and a first voltage level when the detected temperature is room temperature. And a control unit for controlling to the second voltage level at a high temperature of 50 ° C. or higher . The second voltage level may be higher than the first voltage level. The setdown controller may include a first comparator configured to generate a first control signal by comparing the voltage level of the setdown voltage with the first voltage level; A second comparator for generating a second control signal by comparing the voltage level of the set down voltage with the second voltage level, and selecting one of the first and second control signals according to a detection signal of the temperature detector; And a selector for generating a control signal and a switch element for instructing the address period in response to the setdown control signal and forcibly raising the voltage level of the setdown voltage. Plasma according to an embodiment of the present invention drive device for a display panel, which falls in any one area of the room temperature region and high temperature region in order to initialize the cells of the entire screen Set-down voltage generator for generating a set-down voltage with the cry portion, and selecting either one voltage level of the first voltage level or second voltage level in accordance with the area that a set-down voltage is lowered and the voltage of the scan electrodes in the selected voltage And a set down controller for raising . The setdown voltage having the slope falling to the room temperature region is forcibly increased in voltage at the scan electrode at the first voltage level. The setdown voltage having the slope descending to the high temperature region is at the second voltage level. The first voltage level is lower than the second voltage level. The set-down control unit has a high logic state after the second area and a low logic state in other periods. Generate a first reference control signal, generate a second reference control signal having a high logic state during the first and second regions and a low logic state during the other periods, and subsequently A control signal generator for generating a third reference control signal indicating an address period, a voltage level of the setdown voltage, A first comparator for comparing the first voltage level to generate a first control signal, a second comparator for generating a second control signal by comparing the voltage level of the set-down voltage and the second voltage level, and the first comparator A first logical product gate that logically multiplies a control signal and the first reference control signal to generate a first output signal, and a second that logically multiplies the second control signal and the second reference control signal to generate a second output signal And a logic sum gate configured to logically sum the first and second output signals to generate the set down control signal, and a switch element for raising the set down voltage in response to the set down control signal. The driving apparatus of the plasma display panel according to an embodiment of the present invention supplies the high potential voltage of the scan pulse in response to the third reference control signal.

Other objects and features of the present invention in addition to the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

A preferred embodiment of the present invention will be described with reference to FIGS. 7 to 10.

Referring to FIG. 7, the driving method of the PDP according to the first embodiment of the present invention detects the temperature of the PDP and adjusts the voltage level of the set-down voltage (Ramp-down) supplied to the scan electrode (Y).

To this end, in the driving apparatus of the PDP according to the first embodiment of the present invention, as shown in FIG. 8, the high potential scan voltage Vsc and the low potential scan voltage −Vy are input and connected to the scan electrode Y. And a bias detector 62 connected to the scan driver 61. The low potential scan voltage (-Vy) is a base voltage GND or a specific voltage of negative polarity.

The scan driver 61 is connected in a push-pull form and switches QH of a drive integrated circuit (hereinafter referred to as "IC") 63 connected to the scan electrode Y through an output node therebetween. , QL and the third switch Q3 connected to the driving IC 63 via the first node n1 and input with the high potential scan voltage Vsc, and the second node n2. A second switch Q2 connected to the IC 63 and to which a low potential scan voltage (-Vy) is input; a fourth switch Q4 connected between the first and second nodes n1 and n2; A first switch Q1 is connected between the two nodes n2 and the negative scan voltage source -Vy.

The first switch QH of the driver IC 63 supplies the scan electrode Y with the high potential scan voltage Vsc supplied via the first node n1, and the second switch of the driver IC 63. QL supplies the scan electrode Y with a setdown voltage or a low potential scan voltage -Vy supplied via the second node n2. The third switch Q3 is turned on during the address period to supply the high potential scan voltage Vsc to the first node n1. The second switch Q2 is turned on during the set down period to supply a voltage falling to the low potential scan voltage -Vy to the second node n2 at a predetermined falling slope determined by the RC time constant. The first switch Q1 is turned on during the address period to supply the low potential scan voltage -Vy to the second node n2. The fourth switch Q4 is turned on during the address period to open a current path between the first node n1 and the second node n2 to insulate between the first node n1 and the second node n2. It plays a role.

The bias detector 62 includes a zener diode ZD connected between the first and second voltage sources -Vyb1 and -Vyb2 having different voltage levels, and the second node n2 and the low potential scan voltage source -Vy. ), The voltage divided by the first and second voltage divider resistors R1 and R2, the first and second voltage divider resistors R1 and R2, and the first and second voltage sources (-Vyb1 and -Vyb2), respectively. Switching blocks for selecting output signals from the first and second comparators 64 and 68 by means of first and second comparators 64 and 68 and detection signals St from the temperature sensor 70. 68 is provided.

Each of the first and second voltages -Vyb1 and -Vyb2 is set to a value for adjusting the amount of wall charges in each cell in the PDP in the normal operation state and the PDP operated in the high temperature environment. That is, the second voltage -Vyb2 supplied from the second voltage source -Vby2 has the same level as the conventional -Vyb shown in FIG. The first voltage -Vby1 supplied from the first voltage source -Vyb1 has a voltage level set to prevent erroneous discharge of the PDP in a high temperature environment according to the temperature detected from the temperature sensor 70.

The reason for setting the first and second voltages -Vyb1 and -Vyb2 differently is to reduce the wall charges accumulated in the cell by the set-up voltage and to set the wall charges in the cell by the set-down voltage to equalize to a certain amount. This is to adjust to the steady state and high temperature environment.

In detail, if the first voltage (-Vyb1) is higher than the second voltage (-Vyb2) in the normal operation state of the PDP, the wall charge remains in an excessive state, so that the scan electrode (Y) and the common sustain electrode without the data voltage (data) are present. Misdischarge between (Z) occurs. On the other hand, when the PDP is operated in a high temperature environment, loss of wall charges coupled to the dielectric layer in the cell causes a rise in driving voltage. As a result, the increase in the driving voltage in the address period has a problem in that the driving voltage increases because the data voltage or the scan pulse supplied to the scan electrode Y must be lowered in the negative direction. In order to solve this problem, the second voltage (-Vyb2) is replaced with the first voltage (-Vyb1) than the second voltage (-Vyb2) in order to leave more wall charges in preparation for loss of wall charges during the set down voltage supply period. It is set high. At this time, the first voltage (-Vyb1) is a voltage level that can cause overdischarge between the scan electrode (Y) and the common sustain electrode (Z) in a normal operation state, but it is suitable for high temperature environment by reducing the loss of wall charge in the high temperature environment. It is the voltage level that can set the amount of wall charge.

The first and second voltage divider resistors R1 and R2 divide the voltage on the second node n2 by a predetermined voltage divider resistance ratio and divide the divided setdown detection voltage Vd into the first and second comparators 64 and 68. Supply to the inverting terminal (+) of respectively.

The non-inverting terminal (+) of the first comparator 64 is supplied with the set-down detection voltage Vd divided by the divided resistance ratios of the first and second resistors R1 and R2, and the inverting terminal (-) It is supplied from the first voltage source -Vyb1 to the first voltage -Vyb1.

When the set down detection voltage Vd input to the non-inverting terminal (+) is greater than the first voltage (-Vyb1) input to the inverting terminal (-) from the first voltage source (-Vyb1) Vd> -Vyb1) When a low logic output signal is generated and the set-down detection voltage Vd input to the non-inverting terminal (+) is less than or equal to the first voltage (-Vyb1) input to the inverting terminal (-) (Vd ≤-Vyb1) Generates a high logic output signal. The output signal of the first comparator 64 is inverted from low logic to high logic at the beginning of the address period.

The non-inverting terminal (+) of the second comparator 66 is supplied with the set-down detection voltage Vd divided by the divided resistance ratio of the first and second resistors R1 and R2, and the inverting terminal (-) It is supplied from the second voltage source -Vyb2 to the second voltage -Vyb2.

When the set down detection voltage Vd input to the non-inverting terminal (+) is greater than the second voltage (-Vyb2) input from the second voltage source (-Vyb2) to the inverting terminal (-), the second comparator 66 ( Vd> -Vyb2) When a low logic output signal is generated and the set-down detection voltage Vd input to the non-inverting terminal (+) is less than or equal to the second voltage (-Vyb2) input to the inverting terminal (-) (Vd ? -Vyb2) Generates a high logic output signal. The output signal of the second comparator 66 is inverted from low logic to high logic at the beginning of the address period.

The switching block 68 selects and outputs output signals from the first and second comparators 64 and 66 according to the temperature detection signal St from the temperature sensor 70 to a timing controller (not shown).

The temperature sensor 70 detects when the temperature of the PDP is higher than a predetermined temperature using a temperature sensor installed in the PDP and supplies a temperature detection signal St to the control terminal of the switching block 68. That is, the temperature sensor 70 detects when the PDP operates at a high temperature or when the panel temperature is higher than a predetermined temperature to generate a temperature detection signal St and supplies the switching block 68 to the switching block 68. In 68, the first comparator 64 is selected. In addition, the temperature sensor 70 detects the PDP when operating at room temperature, generates a temperature detection signal St, and supplies it to the switching block 68 so that the second comparator 66 in the switching block 68 is provided. To be selected.

The timing controller (not shown) turns on the first and third switches Q1 and Q3 in response to an output signal selected and output from the switching block 68 according to the temperature sensor 70 and at the same time the fourth switch ( The operating conditions of the address are set by turning off Q4) so that the setdown voltage does not fall below the first voltage (-Vyb1) or the second voltage (-Vyb2) potential.

Referring to FIG. 7 and FIG. 8, a driving method of the PDP according to the first embodiment of the present invention will be described below. First, when the PDP is in a normal operating state, as described above, the switching block 68 selects the output signal of the second comparator 66 by the temperature sensor 70. In response to the high logic output signal from the second comparator 66 supplied through the switching block 68, the timing controller turns on the first and third switches Q1 and Q3 and at the same time the fourth controller. The operation condition of the address is set by turning off the switch Q4 so that the set-down voltage does not fall below the second voltage (-Vyb2) potential. This stop of the setdown voltage at the second voltage (-Vyb2) potential causes an address discharge to occur when the low potential scan voltage (-Vy) and the data voltage (data) are applied to the scan electrode (Y) and the address electrode (X). To allow sufficient wall charge to remain in the cell. The scan pulse scan is supplied to the scan electrodes Y from the time t2 set after the address operation condition is set. That is, from the time t2, the switches QH and QL of the driving IC 63 repeatedly turn on / off to supply the scan pulse scan to the scan electrodes Y.

On the other hand, the PDP according to the first embodiment of the present invention when operating in a high temperature environment of 50 ℃ or more as described above by the temperature sensor 70 in the switching block 68, the output signal of the first comparator 64 Will be chosen. In response to the high logic output signal from the first comparator 64 supplied through the switching block 68, the timing controller turns on the first and third switches Q1 and Q3 and at the same time the fourth controller. By turning off the switch Q4 so that the setdown voltage does not fall below the first voltage (-Vyb1) potential, the loss of wall charge in a high temperature environment is set so that the amount of wall charge can be set to suit the operating conditions of the address. . This set-down voltage stops at the first voltage (-Vyb1) potential when the low potential scan voltage (-Vy) and the data voltage (data) are applied to the scan electrode (Y) and the address electrode (X) in a high temperature environment. This is to leave enough wall charge in the cell to the extent that a discharge can occur. The scan pulse scan is supplied to the scan electrodes Y from the time t1 set after the address operation condition is set. That is, from the time t1, the switches QH and QL of the driving IC 63 repeatedly turn on / off the scan pulses to supply the scan electrodes Y to each other.

Referring to FIG. 9, the driving method of the PDP according to the second embodiment of the present invention detects the temperature of the PDP and adjusts the slope and voltage level of the set-down voltage Ramp-down supplied to the scan electrode Y. .

As described above, in the driving method of the PDP according to the second embodiment of the present invention, when the normal operation is performed at room temperature, the slope of the set-down voltage ramp-down is a region indicated by a dot, and the slope from the region a to the region b is shown. Have. This slope is a change in the slope according to the characteristics of the circuit components that set the slope of the set-down voltage (Ramp-down), that is, capacitors, resistors, and diodes. This is because the slope of the set-down voltage decreases due to the characteristics of circuit components in a high temperature environment, and this phenomenon causes a slow and weak operation to reduce the wall charges accumulated in the set-up voltage. The amount of wall charge varies depending on when the ramp-down stops.

Accordingly, in the driving method of the PDP according to the second embodiment of the present invention, even if the slope of the set-down voltage (ramp-down) increases at a high temperature, the second voltage (-Vby2) is set as a normal operation period from the time point t1 to the time point t2. Force the set-down voltage (Ramp-down) at the potential. In addition, when the slope of the set-down voltage ramp-down further increases and becomes greater than or equal to the region b, the set-down voltage ramp-down is forcibly increased at the potential of the first voltage -Vyb1 after the time t2. That is, in the method of driving a PDP according to the second embodiment of the present invention, high temperature misdischarge by adjusting the remaining amount of wall charge by time-dividing the phenomenon that the slope of the set-down voltage is decreased by using the characteristics of the circuit components. Can be prevented.

To this end, in the driving apparatus of the PDP according to the second embodiment of the present invention, as shown in FIG. 10, the high potential scan voltage Vsc and the low potential scan voltage −Vy are input and connected to the scan electrode Y. And a bias detector 82 connected to the scan driver 81. The low potential scan voltage (-Vy) is a base voltage (GND) or a specific voltage of negative polarity.

The scan driver 81 is connected in a push-pull form and switches QH of an integrated circuit (hereinafter referred to as " IC ") 83 connected to the scan electrode Y through an output node therebetween. , QL and the third switch Q3 connected to the driving IC 83 via the first node n1 and input with the high potential scan voltage Vsc, and the second node n2. A second switch Q2 connected to the IC 83 and to which the ground voltage source GND is input; a fourth switch Q4 connected between the first and second nodes n1 and n2; a first switch Q1 connected between n2) and the ground voltage source GND.

The first switch QH of the driving IC 83 supplies the scan electrode Y with the high potential scan voltage Vsc supplied via the first node n1, and the second switch of the driving IC 63. QL supplies the scan electrode Y with a setdown voltage or a ground voltage source GND supplied via the second node n2.

The third switch Q3 is turned on during the address period to supply the high potential scan voltage Vsc to the first node n1. To this end, the control signal Cad supplied from the timing controller to the control terminal of the third switch Q3 maintains a high logic level for the address period, while low logic for other periods. By maintaining the level), the address period is indicated.

The second switch Q2 is turned on during the set down period to supply the second node n2 with a voltage falling to the low potential scan voltage or the ground voltage source GND at a predetermined falling slope determined by the RC time constant. .

The first switch Q1 is turned on by the control signal supplied from the bias detector 82 during the address period to supply the base voltage GND to the second node n2.

The fourth switch Q4 is turned on during the address period to open a current path between the first node n1 and the second node n2 to insulate between the first node n1 and the second node n2. It plays a role.

The bias detector 82 may include the first and second voltage sources -Vyb1 and -Vyb2 having different voltage levels, the set-down voltage ramp-down and the first and second voltage sources (-) of the second node n2. First and second comparators 84 and 88 for comparing Vyb1 and Vyb2, respectively, and a first AND to which an output signal Ca and a first reference control signal Cref_1 of the first comparator 84 are supplied. A second logical product gate (hereinafter referred to as an "AND gate") 88 to which the gate 87, the output signal Cb of the second comparator 86, and the second reference control signal Cref_2 are supplied; And a logic sum gate (hereinafter referred to as an "OR gate") 89 for logical sum operation of the output signals of each of the first and second AND gates 87 and 88 to supply the calculation result to the first switch Q1. .

Each of the first and second voltages -Vyb1 and -Vyb2 is set to a value for adjusting the amount of wall charges in each cell in the PDP in the normal operation state and the PDP operated in the high temperature environment. That is, the second voltage -Vyb2 supplied from the second voltage source -Vby2 has the same level as the conventional -Vyb shown in FIG. The first voltage (-Vby1) supplied from the first voltage source (-Vyb1) is set to the minimum value at which the slope of the set-down voltage (Ramp-down) becomes small due to the characteristics of the circuit component in a high temperature environment, and the slope is less than or equal to this. Has a voltage level set in a range not to decrease.

The set-down voltage Ramp-down is supplied to the non-inverting terminal + of the first comparator 84 through the second node n2, and the first voltage is supplied from the first voltage source -Vyb1 to the inverting terminal-. Supplied to (-Vyb1). When the set-down voltage Ramp-down input to the non-inverting terminal (+) is greater than the first voltage (-Vyb1) input to the inverting terminal (-) from the first voltage source (-Vyb1), the first comparator 84 (Ramp-down> -Vyb1) The first voltage (-) which generates the low logic output signal Ca and the set-down voltage Ramp-down input to the non-inverting terminal (+) is input to the inverting terminal (-). When Vyb1) or less (Ramp-down? -Vyb1), a high logic output signal Ca is generated. The start point t2 of the high logic output signal Ca of the first comparator 84 is changed due to a change in the inclination of the set-down voltage ramp-down according to the characteristics of the circuit component in a high temperature environment. do. As such, the output signal Ca of the first comparator 84 is supplied to the first input terminal of the first AND gate 87.

The set-down voltage Ramp-down is supplied to the non-inverting terminal + of the second comparator 86, and the inverting terminal − is supplied from the second voltage source -Vyb2 to the second voltage -Vyb2. When the set-down voltage Ramp-down input to the non-inverting terminal (+) is greater than the second voltage (-Vyb2) input to the inverting terminal (-) from the second voltage source (-Vyb2), the second comparator 86 (Ramp-down> -Vyb2) A second voltage (-) that generates a low logic output signal (Cb) and a set-down voltage (Ramp-down) input to the non-inverting terminal (+) is input to the inverting terminal (-). When Vyb2) or less (Ramp-down? -Vyb2), a high logic output signal Cb is generated. The output signal Cb of the second comparator 66 is inverted from low logic to high logic at the beginning of the address period. The output signal Ca of the second comparator 86 is supplied to the first input terminal of the second AND gate 87.

The first reference control signal Cref_1 is input to a second input terminal of the first AND gate 87 from a timing controller (not shown). Accordingly, the first AND gate 87 performs a logical multiplication on the output signal Ca from the first comparator 84 input to the first input terminal and the first reference control signal Cref_1 input to the second input terminal. It is supplied to the first input terminal of the OR gate 89. The output signal of the first AND gate 87 changes to a high logic state when both of the first reference control signal Cref_1 and the output signal Ca of the first comparator 84 are in a high logic state. Maintain a low logic state at. The first reference control signal Cref_1 has a first voltage (-Vyb1) potential that is set to a minimum value at which the slope of the set-down voltage Ramp-down becomes small in a high temperature environment from the start of the set-down period as shown in FIG. In the normal operation section up to time t2, the low logic state is maintained, and the high logic state is maintained until the start of the address period.

The second reference control signal Cref_2 is input to a second input terminal of the second AND gate 88 from a timing controller (not shown). Accordingly, the second AND gate 88 performs a logical multiplication on the output signal Cb from the second comparator 86 input to the first input terminal and the second reference control signal Cref_2 input to the second input terminal. It is supplied to the second input terminal of the OR gate 89. The output signal of the second AND gate 88 is changed to the high logic state when the second reference control signal Cref_2 and the output signal Cb of the second comparator 86 are both high logic states, and otherwise. Maintain a low logic state at. The second reference control signal Cref_2 is from the start of the setdown period as shown in FIG. 9 to the potential of the first voltage (-Vyb1), that is, the time t2 which is set to the minimum value at which the slope of the setdown voltage Ramp-down becomes small. In the normal operation of, the high logic state is maintained and the low logic state is maintained until the start of the address period.

The OR gate 89 performs a logical sum operation on the output signal from the first AND gate 87 and the output signal from the second AND gate 88 to supply to the control terminal of the first switch Q1.

As described above, when the PDP is in a normal operating state, the bias detector 82 first decreases the slope of the set-down voltage ramp-down time between the time points t1 and t2, that is, the potential of the second voltage (-Vyb2) in the region a. In this case, the turn-on of the first switch Q1 is turned on to raise the set-down voltage ramp-down from the second voltage (-Vyb2) potential so that the set-down voltage ramp-down is lower than the second voltage (-Vyb2) potential. By not dropping, the amount of wall charges is set as an operation condition of the address. That is, the high logic output signal Ca from the second comparator 86 and the second reference control signal Cref_2 in the high logic state are supplied to the second AND gate 88 so that the second AND gate 88 is high. The output signal in the logic state is supplied to the OR gate 89, and the OR gate 89 supplies the output signal in the high logic state to the first switch Q1 to turn on the first switch Q1. The set-down voltage (Ramp-down) is stopped at the second voltage (-Vyb2) potential is the low potential scan voltage (-Vy) and data voltage (data) is applied to the scan electrode (Y) and the address electrode (X) This is to leave enough wall charge in the cell to allow an address discharge to occur. The scan pulse scan is supplied to the scan electrodes Y from the time t3 set after the address operation condition is set. That is, from time t3, the switches QH and QL of the driving IC 83 repeatedly turn on / off the scan pulses to supply the scan electrodes Y to each other.

On the other hand, when the PDP according to the second embodiment of the present invention is operated in a high temperature environment of 50 ° C. or higher, the slope of the ramp-down is after time t2 due to the characteristics of the circuit component according to the high temperature, that is, in the region b. When the voltage falls to the first voltage (-Vyb1) potential, the turn-on of the first switch Q1 is turned on to raise the set-down voltage Ramp-down from the potential of the first voltage (-Vyb1) to set-down voltage (Ramp-down). By not dropping below the first voltage (-Vyb1) potential, the wall charge amount in the high temperature environment is set as the operation condition of the address. That is, the high logic output signal Ca from the first comparator 84 and the first reference control signal Cref_1 in the high logic state are supplied to the first AND gate 87 so that the first AND gate 87 is high. The output signal in the logic state is supplied to the OR gate 89, and the OR gate 89 supplies the output signal in the high logic state to the first switch Q1 to turn on the first switch Q1. The set-down voltage (Ramp-down) is stopped at the first voltage (-Vyb1) potential is the low potential scan voltage (-Vy) and data voltage (data) is applied to the scan electrode (Y) and the address electrode (X) This is to leave enough wall charge in the cell to allow an address discharge in a high temperature environment. The scan pulse scan is supplied to the scan electrodes Y from the time t3 set after the address operation condition is set. That is, from time t3, the switches QH and QL of the driving IC 83 repeatedly turn on / off the scan pulses to supply the scan electrodes Y.

Therefore, after the first switch Q1 is turned on at the time t2 in the high temperature environment, the third switch Q3 is turned on at the time t3. On the other hand, in the normal temperature environment, the first switch Q1 is turned on at any time between the time t1 and the time t2 when the set-down voltage Ramp-down becomes less than or equal to the second voltage (-Vyb2) potential. .

As described above, the method and apparatus for driving the plasma display panel according to the embodiment of the present invention detect the temperature of the plasma display panel and set the voltage level of the setdown voltage according to the detected temperature. In addition, according to the characteristics of the circuit component for supplying the setdown voltage in a high temperature environment, the setdown voltage is forcibly raised to a desired voltage level before the address is started.

Accordingly, the method and apparatus for driving a PDP according to the present invention can prevent mis-discharge in a high temperature environment by setting an optimal address operating condition before the set-down voltage starts addressing regardless of temperature change.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (20)

delete Setup period and Initialization period divided into set-down period Address And Sustain Divided by period plasma display Panel In the driving method, remind Panel Detecting a temperature; Using the setdown voltage Full screen Cells Initializing, remind Address Set the voltage level of the setdown voltage immediately before the start of the period to the first voltage level when the detected temperature is room temperature, and 50 ℃ In the case of the above high temperature, the second voltage level is set. plasma display Panel Driving method. The method of claim 2, And the second voltage level is higher than the first voltage level. The method of claim 2, Adjusting the voltage level of the set down voltage, Generating a first control signal by comparing the voltage level of the set down voltage with the first voltage level; Generating a second control signal by comparing the voltage level of the set down voltage with the second voltage level; Selecting one of the first and second control signals according to the detected temperature to generate a setdown control signal; And forcibly raising the voltage level of the setdown voltage according to the setdown control signal to indicate the address period. Initializing cells of the full screen using a set-down voltage having a slope falling to one of a room temperature region and a high temperature region ; The first voltage level or the second voltage depending on the region in which the setdown voltage falls Voltage Select any one of the voltage levels Scan electrode Increasing the voltage plasma display Panel Driving method. The method of claim 5, wherein And the setdown voltage having a slope falling to the room temperature region is forcibly increased at a voltage of a scan electrode at the first voltage level. The method of claim 5, wherein And the setdown voltage having a slope falling to the high temperature region is forcibly increased at a voltage of a scan electrode at the second voltage level. The method of claim 5, wherein And wherein the first voltage level is lower than the second voltage level. The method of claim 5, wherein Raising the set down voltage to one of the first and second voltage levels, Generating a first reference control signal having a high logic state after the second region and a low logic state in other periods; Generating a second reference control signal having a high logic state during the first and second regions and a low logic state during other periods; Generating a third reference control signal indicative of the address period thereafter to the first reference control signal; Generating a first control signal by comparing the voltage level of the set down voltage with the first voltage level; Generating a second control signal by comparing the voltage level of the set down voltage with the second voltage level; Generating a first output signal by performing a logical multiplication on the first control signal and the first reference control signal; Generating a second output signal by performing a logical multiplication on the second control signal and the second reference control signal; Generating the setdown control signal by logically adding the first and second output signals; And increasing the set down voltage in response to the set down control signal. The method of claim 9, And supplying a high potential voltage of a scan pulse in response to the third reference control signal. delete Setup period and Initialization period divided into set-down period Address And Sustain Divided by period plasma display Panel In the driving method, remind Panel For detecting temperature Temperature detector , remind The address period The voltage level of the setdown voltage immediately before starting is controlled to the first voltage level when the detected temperature is room temperature, and 50 ℃ If higher temperature than Has a control unit for controlling to a second voltage level display Panel Drive system. The method of claim 12, And the second voltage level is higher than the first voltage level. The method of claim 12, The set down control unit, A first comparator configured to generate a first control signal by comparing the voltage level of the set down voltage with the first voltage level; A second comparator configured to generate a second control signal by comparing the voltage level of the set down voltage with the second voltage level; A selector for selecting one of the first and second control signals and generating a set down control signal according to the detection signal of the temperature detector; And a switch element for indicating the address period in response to the set down control signal and forcibly raising the voltage level of the set down voltage. A setdown voltage generator for generating a setdown voltage having a slope falling to one of a room temperature region and a high temperature region to initialize the cells of the full screen; The voltage level of either the first voltage level or the second voltage level is selected according to the area where the setdown voltage falls, and at the selected voltage Scan electrode Set-Down to Raise Voltage Control Characterized in that plasma display Panel Drive system. The method of claim 15, And the setdown voltage having the slope falling to the room temperature region is forced to increase the voltage of the scan electrode at the first voltage level. The method of claim 15, And the setdown voltage having the slope falling to the high temperature region is forcibly increased in voltage at the scan electrode at the second voltage level. The method of claim 15, And the first voltage level is lower than the second voltage level. The method of claim 15, The set down control unit; A first reference control signal having a high logic state after the second region and a low logic state in other periods, and having a high logic state in the first and second regions, and a low logic state in other periods. A control signal generation section for generating a second reference control signal having a second reference control signal, and for generating a third reference control signal instructing the address period thereafter; A first comparator configured to generate a first control signal by comparing the voltage level of the set down voltage with the first voltage level; A second comparator configured to generate a second control signal by comparing the voltage level of the set down voltage with the second voltage level; A first logical product gate configured to logically multiply the first control signal and the first reference control signal to generate a first output signal; A second logical product gate for generating a second output signal by performing a logical multiplication of the second control signal and the second reference control signal; A logic sum gate for generating a set down control signal by logical sum of the first and second output signals; And a switch element for raising the set down voltage in response to the set down control signal. The method of claim 19, And a high potential voltage of a scan pulse in response to the third reference control signal.