KR100426904B1 - 전극간의 접속 구조 및 그 제조 방법 - Google Patents

전극간의 접속 구조 및 그 제조 방법 Download PDF

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Publication number
KR100426904B1
KR100426904B1 KR10-2002-0004093A KR20020004093A KR100426904B1 KR 100426904 B1 KR100426904 B1 KR 100426904B1 KR 20020004093 A KR20020004093 A KR 20020004093A KR 100426904 B1 KR100426904 B1 KR 100426904B1
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KR
South Korea
Prior art keywords
copper wiring
layer
copper
metal
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2002-0004093A
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English (en)
Korean (ko)
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KR20020087338A (ko
Inventor
후지사와마사히꼬
오사끼아끼히꼬
모리모또노보루
Original Assignee
미쓰비시덴키 가부시키가이샤
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Publication of KR20020087338A publication Critical patent/KR20020087338A/ko
Application granted granted Critical
Publication of KR100426904B1 publication Critical patent/KR100426904B1/ko
Assigned to 르네사스 일렉트로닉스 가부시키가이샤 reassignment 르네사스 일렉트로닉스 가부시키가이샤 권리의 전부이전등록 Assignors: 미쓰비시덴키 가부시키가이샤
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR10-2002-0004093A 2001-05-15 2002-01-24 전극간의 접속 구조 및 그 제조 방법 Expired - Fee Related KR100426904B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2001-00144957 2001-05-15
JP2001144957A JP2002343859A (ja) 2001-05-15 2001-05-15 配線間の接続構造及びその製造方法

Publications (2)

Publication Number Publication Date
KR20020087338A KR20020087338A (ko) 2002-11-22
KR100426904B1 true KR100426904B1 (ko) 2004-04-14

Family

ID=18990834

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0004093A Expired - Fee Related KR100426904B1 (ko) 2001-05-15 2002-01-24 전극간의 접속 구조 및 그 제조 방법

Country Status (4)

Country Link
US (2) US6624516B2 (https=)
JP (1) JP2002343859A (https=)
KR (1) KR100426904B1 (https=)
TW (1) TW554478B (https=)

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JP2004095611A (ja) * 2002-08-29 2004-03-25 Fujitsu Ltd 半導体装置およびその製造方法
KR100457057B1 (ko) * 2002-09-14 2004-11-10 삼성전자주식회사 금속막 형성 방법
US20040175926A1 (en) * 2003-03-07 2004-09-09 Advanced Micro Devices, Inc. Method for manufacturing a semiconductor component having a barrier-lined opening
US20040245636A1 (en) * 2003-06-06 2004-12-09 International Business Machines Corporation Full removal of dual damascene metal level
US7265038B2 (en) * 2003-11-25 2007-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a multi-layer seed layer for improved Cu ECP
US6849541B1 (en) * 2003-12-19 2005-02-01 United Microelectronics Corp. Method of fabricating a dual damascene copper wire
JP2005244178A (ja) * 2004-01-26 2005-09-08 Toshiba Corp 半導体装置の製造方法
KR101080401B1 (ko) * 2004-04-23 2011-11-04 삼성전자주식회사 평판 표시장치의 접합구조체 및 그 형성방법과 이를구비하는 평판 표시장치
JP4370206B2 (ja) * 2004-06-21 2009-11-25 パナソニック株式会社 半導体装置及びその製造方法
JP4224434B2 (ja) * 2004-06-30 2009-02-12 パナソニック株式会社 半導体装置及びその製造方法
DE102005023122A1 (de) * 2005-05-19 2006-11-23 Infineon Technologies Ag Integrierte Schaltungsanordnung mit Schichtstapel und Verfahren
US7368379B2 (en) * 2005-08-04 2008-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for semiconductor devices
US8308053B2 (en) * 2005-08-31 2012-11-13 Micron Technology, Inc. Microfeature workpieces having alloyed conductive structures, and associated methods
JP5387695B2 (ja) 2009-12-28 2014-01-15 富士通株式会社 配線構造の形成方法
US8460981B2 (en) 2010-09-28 2013-06-11 International Business Machines Corporation Use of contacts to create differential stresses on devices
US8815671B2 (en) 2010-09-28 2014-08-26 International Business Machines Corporation Use of contacts to create differential stresses on devices
US8835305B2 (en) * 2012-07-31 2014-09-16 International Business Machines Corporation Method of fabricating a profile control in interconnect structures
US9577023B2 (en) * 2013-06-04 2017-02-21 Globalfoundries Inc. Metal wires of a stacked inductor
US9219033B2 (en) * 2014-03-21 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Via pre-fill on back-end-of-the-line interconnect layer
US10825724B2 (en) * 2014-04-25 2020-11-03 Taiwan Semiconductor Manufacturing Company Metal contact structure and method of forming the same in a semiconductor device
US9418951B2 (en) * 2014-05-15 2016-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof
US9496225B1 (en) 2016-02-08 2016-11-15 International Business Machines Corporation Recessed metal liner contact with copper fill

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0751566A3 (en) * 1995-06-30 1997-02-26 Ibm Metal thin film barrier for electrical connections
JPH1167766A (ja) * 1997-08-19 1999-03-09 Sony Corp 半導体装置の製造方法
US6887353B1 (en) * 1997-12-19 2005-05-03 Applied Materials, Inc. Tailored barrier layer which provides improved copper interconnect electromigration resistance
US6127258A (en) 1998-06-25 2000-10-03 Motorola Inc. Method for forming a semiconductor device
JP2000124310A (ja) * 1998-10-16 2000-04-28 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
JP2000183064A (ja) 1998-12-16 2000-06-30 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
JP2000323571A (ja) * 1999-05-14 2000-11-24 Sony Corp 半導体装置の製造方法
US6146517A (en) * 1999-05-19 2000-11-14 Infineon Technologies North America Corp. Integrated circuits with copper metallization for interconnections
US6339258B1 (en) * 1999-07-02 2002-01-15 International Business Machines Corporation Low resistivity tantalum
KR100301057B1 (ko) * 1999-07-07 2001-11-01 윤종용 구리 배선층을 갖는 반도체 소자 및 그 제조방법
JP2001053150A (ja) * 1999-08-12 2001-02-23 Hitachi Ltd 半導体集積回路装置の製造方法
JP2001053151A (ja) 1999-08-17 2001-02-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6323121B1 (en) * 2000-05-12 2001-11-27 Taiwan Semiconductor Manufacturing Company Fully dry post-via-etch cleaning method for a damascene process
US6342448B1 (en) * 2000-05-31 2002-01-29 Taiwan Semiconductor Manufacturing Company Method of fabricating barrier adhesion to low-k dielectric layers in a copper damascene process

Also Published As

Publication number Publication date
KR20020087338A (ko) 2002-11-22
JP2002343859A (ja) 2002-11-29
US6780769B2 (en) 2004-08-24
TW554478B (en) 2003-09-21
US20030205825A1 (en) 2003-11-06
US6624516B2 (en) 2003-09-23
US20020171149A1 (en) 2002-11-21

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