KR100392038B1 - 반도체 집적 회로 장치 - Google Patents

반도체 집적 회로 장치 Download PDF

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Publication number
KR100392038B1
KR100392038B1 KR10-2001-0008964A KR20010008964A KR100392038B1 KR 100392038 B1 KR100392038 B1 KR 100392038B1 KR 20010008964 A KR20010008964 A KR 20010008964A KR 100392038 B1 KR100392038 B1 KR 100392038B1
Authority
KR
South Korea
Prior art keywords
input
circuit
signal
logic
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2001-0008964A
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English (en)
Korean (ko)
Other versions
KR20010083242A (ko
Inventor
고우사이소우헤이
하마다모또쯔구
구로다다다히로
Original Assignee
가부시끼가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 가부시끼가이샤 도시바 filed Critical 가부시끼가이샤 도시바
Publication of KR20010083242A publication Critical patent/KR20010083242A/ko
Application granted granted Critical
Publication of KR100392038B1 publication Critical patent/KR100392038B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR10-2001-0008964A 2000-02-22 2001-02-22 반도체 집적 회로 장치 Expired - Fee Related KR100392038B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000044307A JP3901906B2 (ja) 2000-02-22 2000-02-22 半導体集積回路装置
JP2000-044307 2000-02-22

Publications (2)

Publication Number Publication Date
KR20010083242A KR20010083242A (ko) 2001-08-31
KR100392038B1 true KR100392038B1 (ko) 2003-07-23

Family

ID=18567085

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2001-0008964A Expired - Fee Related KR100392038B1 (ko) 2000-02-22 2001-02-22 반도체 집적 회로 장치

Country Status (4)

Country Link
US (1) US6476639B2 (cg-RX-API-DMAC10.html)
JP (1) JP3901906B2 (cg-RX-API-DMAC10.html)
KR (1) KR100392038B1 (cg-RX-API-DMAC10.html)
TW (1) TW483116B (cg-RX-API-DMAC10.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7006962B1 (en) * 2001-11-29 2006-02-28 Lsi Logic Corporation Distributed delay prediction of multi-million gate deep sub-micron ASIC designs
US9638743B2 (en) * 2014-01-16 2017-05-02 Qualcomm Incorporated State-dependent capacitance estimation
EP3542216B1 (en) 2016-11-18 2026-04-22 Magic Leap, Inc. Multilayer liquid crystal diffractive gratings for redirecting light of wide incident angle ranges
JP7300996B2 (ja) 2017-03-21 2023-06-30 マジック リープ， インコーポレイテッド 回折光学要素を使用した眼結像装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342090A (ja) * 1986-08-07 1988-02-23 Fujitsu Ltd ユニバーサルジョイント
US5391941A (en) * 1993-09-23 1995-02-21 Cypress Semiconductor Corporation Decoder circuitry with balanced propagation delay and minimized input capacitance
US5793551A (en) * 1995-06-07 1998-08-11 Vtc Inc. Amplifier having a differential input capacitance cancellation circuit
JP3178371B2 (ja) 1997-05-06 2001-06-18 日本電気株式会社 半導体集積回路の設計方法

Also Published As

Publication number Publication date
US20010015658A1 (en) 2001-08-23
TW483116B (en) 2002-04-11
JP2001237691A (ja) 2001-08-31
US6476639B2 (en) 2002-11-05
KR20010083242A (ko) 2001-08-31
JP3901906B2 (ja) 2007-04-04

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