KR100385127B1 - 반도체장치제조방법 - Google Patents

반도체장치제조방법 Download PDF

Info

Publication number
KR100385127B1
KR100385127B1 KR1019950051147A KR19950051147A KR100385127B1 KR 100385127 B1 KR100385127 B1 KR 100385127B1 KR 1019950051147 A KR1019950051147 A KR 1019950051147A KR 19950051147 A KR19950051147 A KR 19950051147A KR 100385127 B1 KR100385127 B1 KR 100385127B1
Authority
KR
South Korea
Prior art keywords
film
bipolar transistor
insulating film
emitter
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019950051147A
Other languages
English (en)
Korean (ko)
Inventor
히로유키 미와
히로아키 안모
Original Assignee
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 가부시끼 가이샤 filed Critical 소니 가부시끼 가이샤
Application granted granted Critical
Publication of KR100385127B1 publication Critical patent/KR100385127B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
KR1019950051147A 1994-12-19 1995-12-18 반도체장치제조방법 Expired - Fee Related KR100385127B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6335015A JPH08172139A (ja) 1994-12-19 1994-12-19 半導体装置製造方法
JP94-335015 1994-12-19

Publications (1)

Publication Number Publication Date
KR100385127B1 true KR100385127B1 (ko) 2003-09-06

Family

ID=18283791

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950051147A Expired - Fee Related KR100385127B1 (ko) 1994-12-19 1995-12-18 반도체장치제조방법

Country Status (4)

Country Link
US (1) US5641692A (enExample)
JP (1) JPH08172139A (enExample)
KR (1) KR100385127B1 (enExample)
TW (1) TW289857B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3695029B2 (ja) * 1996-08-14 2005-09-14 ソニー株式会社 半導体装置の製造方法
US6399458B1 (en) 1999-09-21 2002-06-04 International Business Machines Corporation Optimized reachthrough implant for simultaneously forming an MOS capacitor
US6800921B1 (en) 2000-03-01 2004-10-05 International Business Machines Corporation Method of fabricating a polysilicon capacitor utilizing fet and bipolar base polysilicon layers
DE10138648A1 (de) * 2001-08-07 2003-03-06 Infineon Technologies Ag Verfahren zum parallelen Herstellen eines MOS-Transistors und eines Bipolartransistors
US6987039B2 (en) * 2001-10-03 2006-01-17 Texas Instruments Incorporated Forming lateral bipolar junction transistor in CMOS flow
JP3790237B2 (ja) * 2003-08-26 2006-06-28 株式会社東芝 半導体装置の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936959A (ja) * 1982-08-24 1984-02-29 Mitsubishi Electric Corp 半導体装置の製造方法
JPH025463A (ja) * 1988-06-24 1990-01-10 Hitachi Ltd 半導体集積回路装置及びその製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492786B1 (enExample) * 1969-03-28 1974-01-22
NL7017066A (enExample) * 1970-11-21 1972-05-24
JPS52132684A (en) * 1976-04-29 1977-11-07 Sony Corp Insulating gate type field effect transistor
US4325180A (en) * 1979-02-15 1982-04-20 Texas Instruments Incorporated Process for monolithic integration of logic, control, and high voltage interface circuitry
JPS567463A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor device and its manufacture
US4409725A (en) * 1980-10-16 1983-10-18 Nippon Gakki Seizo Kabushiki Kaisha Method of making semiconductor integrated circuit
IT1188309B (it) * 1986-01-24 1988-01-07 Sgs Microelettrica Spa Procedimento per la fabbricazione di dispositivi elettronici integrati,in particolare transistori mos a canale p ad alta tensione
JPH0812918B2 (ja) * 1986-03-28 1996-02-07 株式会社東芝 半導体装置の製造方法
JP2565317B2 (ja) * 1986-12-03 1996-12-18 富士通株式会社 半導体装置の製造方法
JPH0236561A (ja) * 1988-07-27 1990-02-06 Hitachi Ltd 半導体集積回路装置及びその製造方法
US5141881A (en) * 1989-04-20 1992-08-25 Sanyo Electric Co., Ltd. Method for manufacturing a semiconductor integrated circuit
US5288651A (en) * 1989-11-09 1994-02-22 Kabushiki Kaisha Toshiba Method of making semiconductor integrated circuit device including bipolar transistors, MOS FETs and CCD
DE69133446T2 (de) * 1990-11-14 2006-02-09 Samsung Semiconductor, Inc., San Jose BiCMOS-Verfahren mit Bipolartransistor mit geringem Basis-Rekombinationsstrom
US5374569A (en) * 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
US5288652A (en) * 1992-12-18 1994-02-22 Vlsi Technology, Inc. BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936959A (ja) * 1982-08-24 1984-02-29 Mitsubishi Electric Corp 半導体装置の製造方法
JPH025463A (ja) * 1988-06-24 1990-01-10 Hitachi Ltd 半導体集積回路装置及びその製造方法

Also Published As

Publication number Publication date
JPH08172139A (ja) 1996-07-02
TW289857B (enExample) 1996-11-01
US5641692A (en) 1997-06-24

Similar Documents

Publication Publication Date Title
US6518623B1 (en) Semiconductor device having a buried-channel MOS structure
EP0387999B1 (en) Process for forming high-voltage and low-voltage CMOS transistors on a single integrated circuit chip
US4752589A (en) Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate
US4503598A (en) Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
US5468666A (en) Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip
US5897363A (en) Shallow junction formation using multiple implant sources
US5283455A (en) Thin film field effect element having an LDD structure
US4637124A (en) Process for fabricating semiconductor integrated circuit device
US6137146A (en) Bipolar transistor and method of forming BiCMOS circuitry
US6300207B1 (en) Depleted sidewall-poly LDD transistor
KR100279264B1 (ko) 더블 게이트 구조를 갖는 에스·오·아이 트랜지스터 및 그의제조방법
US6879007B2 (en) Low volt/high volt transistor
JPH0351108B2 (enExample)
US5242849A (en) Method for the fabrication of MOS devices
KR100385127B1 (ko) 반도체장치제조방법
EP0091256B1 (en) Cmos device
EP0337823A2 (en) MOS field effect transistor having high breakdown voltage
US7060572B2 (en) MOSFET with short channel structure and formation method thereof
JPS6035558A (ja) 半導体集積回路装置およびその製造方法
JPH06291262A (ja) 半導体装置の製造方法
KR100317688B1 (ko) 반도체장치의 제조방법
KR100318463B1 (ko) 몸체접촉실리콘이중막소자제조방법
US5894155A (en) Metal gate high voltage integrated circuit/process
JPS6025028B2 (ja) 半導体装置の製造方法
EP0568206A2 (en) Bipolar transistor and method of manufacture

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20060513

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20060513

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000