KR100384791B1 - Method for manufacturing capacitor semiconductor memory device - Google Patents
Method for manufacturing capacitor semiconductor memory device Download PDFInfo
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- KR100384791B1 KR100384791B1 KR1019950053299A KR19950053299A KR100384791B1 KR 100384791 B1 KR100384791 B1 KR 100384791B1 KR 1019950053299 A KR1019950053299 A KR 1019950053299A KR 19950053299 A KR19950053299 A KR 19950053299A KR 100384791 B1 KR100384791 B1 KR 100384791B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Abstract
Description
본 발명은 반도체 기억소자의 캐패시터(capacitor) 제조방법에 관한 것으로, 특히 실린더(cylinder)형 캐패시터의 정전용량 증대에 적당하도록 한 반도체 기억소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor of a semiconductor memory device suitable for increasing capacitance of a cylinder type capacitor.
제 1 도는 종래의 반도체 기억소자의 캐패시터 제조방법의 일실시예를 도시한 단면도로서, 이하 첨부된 도면을 참고로 종래의 반도체 기억소자의 캐패시터 제조방법을 설명하면 다음과 같다.1 is a cross-sectional view showing an embodiment of a capacitor manufacturing method of a conventional semiconductor memory device. Hereinafter, a capacitor manufacturing method of a conventional semiconductor memory device will be described with reference to the accompanying drawings.
종래의 반도체 장치의 캐패시터 제조방법에서는 우선 제 1 도의 (가)와 같이, 반도체기판(10) 상에 적층된 층간절연막(11) 위에 질화막(12)을 형성시킨 후에, 캐패시터 접촉부위(A 부위)의 층간절연막과 질화막을 사진식각하여 접촉창 (contact hole)(13)을 형성시킨다.In the conventional capacitor manufacturing method of a semiconductor device, as shown in FIG. 1A, first, the nitride film 12 is formed on the interlayer insulating film 11 laminated on the semiconductor substrate 10, and then the capacitor contact portion (A portion). The interlayer insulating film and the nitride film are photo-etched to form a contact hole 13.
이어서, 제 1 도의 (나)와 같이, 질화막(12)과 접촉창 위에 다결정실리콘층을 형성시키고, 다결정실리콘층 위에 산화막을 형성시킨 후에, 산화막과 다결정실리콘층을 사진식각의 방법으로 반응성 이온식각하여 하부에는 접촉창을 통하여 캐패시터 접촉부위(A 부위)와 접촉하는 다결정실리콘층(14)이 형성되고, 상부에는 기둥산화막(pillar oxide)(15)이 형성되는 캐패시터 전극패턴(capacitor node pattern)(16)을 형성시킨다.Subsequently, as shown in FIG. 1B, a polysilicon layer is formed on the nitride film 12 and the contact window, and an oxide film is formed on the polysilicon layer. Then, the oxide film and the polycrystalline silicon layer are reactive ion etched by photolithography. Thus, a lower portion of the polysilicon layer 14 is formed in contact with the capacitor contact portion (site A) through the contact window, and a capacitor electrode pattern (pillar oxide) 15 is formed on the upper portion (capacitor node pattern) ( 16).
그리고 제 1 도의 (다)와 같이, 캐패시터 전극패턴(16)의 측벽에 다결정실리콘측벽(17)을 형성시킨다.Then, as shown in FIG. 1C, the polysilicon sidewall 17 is formed on the sidewall of the capacitor electrode pattern 16. As shown in FIG.
즉, 캐패시터 전극패턴과 질화막 위에 다결정실리콘층을 형성시킨후에, 이 다결정실리콘층을 이방성 식각하여 캐패시터 전극패턴의 측벽에 다결정실리콘측벽이 형성되도록 한다.In other words, after the polysilicon layer is formed on the capacitor electrode pattern and the nitride film, the polysilicon layer is anisotropically etched to form the polysilicon sidewalls on the sidewalls of the capacitor electrode pattern.
이어서, 제 1 도의 (라)와 같이, 다결정실리콘측벽(17) 사이에서 캐패시터 전극패턴 상부의 기둥 산화막을 습식각의 방법으로 제거하여, 실린더형의 제 1캐패시터 전극(18)을 형성시킨다.Subsequently, as shown in FIG. 1D, the pillar oxide film on the upper portion of the capacitor electrode pattern is removed by the wet etching method between the polysilicon side walls 17 to form the cylindrical first capacitor electrode 18.
그리고 제 1 도의 (마)와 갈이, 제 1캐패시터전극(18) 위에 유전체막(19)과 제 2캐패시터전극(18-1)을 형성시킨다.Then, the dielectric film 19 and the second capacitor electrode 18-1 are formed on the first capacitor electrode 18 as shown in FIG.
즉, 종래의 반도체 기억소자의 캐패시터 제조방법에서는 제 1캐패시터전극을 실린더형으로 형성하여, 면적의 증가로 인해 정전용량이 증가되도록 하고 있다.That is, in the conventional capacitor manufacturing method of the semiconductor memory device, the first capacitor electrode is formed in a cylindrical shape, so that the capacitance increases due to the increase in the area.
그러나 종래의 반도체 기억소자의 캐패시터 제조방법에서는 캐패시터의 정전용량의 증대를 위하여 실린더형의 캐패시터전극의 높이를 증대시켜서, 유전체가 형성되는 캐패시터전극의 표면적을 증가시키고 있으나, 이는 후 공정에서 반도체 기억소자의 평탄화를 저하시키고 있으므로, 정전용량이 한정되는 문제가 발생되었다.However, in the conventional method of manufacturing a capacitor of a semiconductor memory device, the height of the cylindrical capacitor electrode is increased to increase the capacitance of the capacitor, thereby increasing the surface area of the capacitor electrode on which the dielectric is formed. Since the flattening of the was reduced, the problem of limiting the capacitance occurred.
본 발명은 이러한 문제를 해결하기 위하여 안출된 것으로, 정전용량이 증대된 캐피시터의 제조방법을 제공하고자 하는 것이 그 목적이다.The present invention has been made to solve such a problem, and an object thereof is to provide a method of manufacturing a capacitor having an increased capacitance.
본 발명에 의한 반도체 기억소자의 캐패시터 제조방법은 반도체기판 상에 적층된 층간절연막 위에 질화막을 형성시킨 후에, 질화막 위에 제1산화막을 형성시키는 단계와, 제1산화막과, 질화막과, 층간절연막를 선택식각하여 접촉창을 형성시키는 단계와, 접촉창의 측벽에 절연물질측벽을 형성시키는 단계와, 제1산화막을 제거하여, 절연물질측벽이 돌출되도록 하는 단계와, 질화막과, 절연물질측벽과, 접촉창 위에 제1다결정실리콘층을 형성시키고, 다결정실리콘층 위에 제2산화막을 형성시키는 단계와, 제2산화막과 다결정실리콘층을 선택식각하여 캐패시터 전극패턴을 형성시키는 단계와, 캐패시터 전극패턴의 측벽에 다결정실리콘측벽을 형성시키는 단계와, 다결정실리콘측벽 사이의 기둥산화막을 제거하여, 다결정실리콘측벽에 의해 실린더형으로 형성되면서, 상부가 돌출된 절연물질측벽 위에 돌출부가 형성된 제 1캐패시터전극을 형성시키는 단계와, 제 1캐패시터전극 위에 유전체막을 형성시키고, 유전체막 위에 제 2캐패시터전극을 형성시키는 단계를 포함하여 이루어진다.In the method of manufacturing a capacitor of a semiconductor memory device according to the present invention, after forming a nitride film on an interlayer insulating film stacked on a semiconductor substrate, forming a first oxide film on the nitride film, and selectively etching the first oxide film, the nitride film, and the interlayer insulating film. Forming a contact window, forming an insulating material side wall on the sidewall of the contact window, removing the first oxide film so that the insulating material side wall protrudes, a nitride film, an insulating material side wall, and a contact window. Forming a first polycrystalline silicon layer, forming a second oxide film on the polycrystalline silicon layer, selectively etching the second oxide film and the polycrystalline silicon layer to form a capacitor electrode pattern, and forming polycrystalline silicon on the sidewalls of the capacitor electrode pattern Forming the sidewalls, removing the pillar oxide film between the polysilicon sidewalls, and forming a cylindrical shape by the polysilicon sidewalls. As formed, it comprises the steps and, the step of the dielectric film is formed on the first capacitor electrode and forming a second capacitor electrode on the dielectric film to form a first capacitor electrode with a projection formed on the insulating upper protruding material wall.
제 2 도는 본 발명에 의한 반도체 기억소자의 캐패시터 제조방법의 일실시예를 도시한 단면도로서, 이하 첨부된 도면을 참고로 본 발명에 의한 반도체 기억소자의 캐패시터 제조방법을 설명하면 다음과 같다.2 is a cross-sectional view showing an embodiment of a method of manufacturing a capacitor of a semiconductor memory device according to the present invention. Hereinafter, a method of manufacturing a capacitor of the semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.
본 발명에 의한 반도체 기억소자의 캐패시터 제조방법의 일실시예에서는 우선, 제 2 도의 (가)와 같이, 반도체기판(20) 상에 적층된 층간절연막(21) 위에 질화막(22)과 제1산화막(23)을 차례대로 적층하여 형성시키고, 층간절연막과 질화막과 제1산화막을 사진식각의 방법으로 선택식각하여 캐패시터 접촉부위(A' 부위)에 접촉창(14)을 형성시킨다.In one embodiment of the method for manufacturing a capacitor of a semiconductor memory device according to the present invention, first, the nitride film 22 and the first oxide film on the interlayer insulating film 21 laminated on the semiconductor substrate 20 as shown in FIG. (23) are formed by stacking them in turn, and the interlayer insulating film, the nitride film and the first oxide film are selectively etched by photolithography to form the contact window 14 at the capacitor contact portion (A 'portion).
이어서, 제 2 도의 (나)와 같이, 접촉창(24)의 내측벽에 질화막측벽(25)을 형성시킨 후에, 제1산화막을 제거하여 질화막측벽 상부가 돌출되도록 한다.Subsequently, as shown in FIG. 2B, after the nitride film side wall 25 is formed on the inner wall of the contact window 24, the first oxide film is removed so that the upper portion of the nitride film side wall protrudes.
이때, 질화막측벽은 제1산화막과 접촉창 위에 질화막을 형성시킨 후에, 질화막을 이방성 건식식각하여 형성시키며, 돌출된 질화막측벽의 상부 높이는 제1산화막의 두깨로서 조절하거나, 또는 질화막의 이방성 식각정도로서 조절한다.At this time, the nitride film side wall is formed by forming an nitride film on the first oxide film and the contact window, and then the nitride film is formed by anisotropic dry etching, and the upper height of the protruding nitride film side wall is controlled by the thickness of the first oxide film or by the degree of anisotropic etching of the nitride film. do.
그리고 제 2 도의 (다)와 같이, 질화막(22)과, 상부가 돌출된 질화막측벽(25)과, 접촉창 위에 다결정실리콘층(26)을 형성시키고, 다결정실리콘층 위에 제2산화막(27)을 형성시킨다.As shown in FIG. 2C, the nitride film 22, the nitride film side wall 25 protruded from the top, and the polysilicon layer 26 are formed on the contact window, and the second oxide film 27 is formed on the polysilicon layer. To form.
이어서, 제 2 도의 (라)와 같이, 제2산화막과 다결정실리콘층을 사진식각의 방법으로 반응성 이온식각하여 하부에는 하부에는 접촉창을 통하여 캐패시터 접촉부위와 접촉하는 다결정실리콘층(26')이 형성되고, 상부에는 기둥산화막(28)이 형성되는 캐패시터 전극패턴(29)을 형성시킨다.Subsequently, as shown in FIG. 2D, the second oxide film and the polysilicon layer are reactively ion-etched by photolithography, and a polysilicon layer 26 ′ which contacts the capacitor contact portion through a contact window is provided in the lower portion thereof. And a capacitor electrode pattern 29 having a pillar oxide layer 28 formed thereon.
그리고 제 2 도의 (마)와 같이, 캐패시터 전극패턴(29)의 측벽에 다결정실리콘측벽(30)을 형성시킨다.As shown in FIG. 2E, the polysilicon side walls 30 are formed on the sidewalls of the capacitor electrode patterns 29. As shown in FIG.
이어서 제 2 도의 (바)와 같이, 다결정실리콘측벽(30) 사이에서 캐패시터 전극패턴 상부의 기둥산화막을 습식식각하여 다결정실리콘측벽에 의해 실린더형으로 형성되면서, 상부가 돌출된 질화막측벽(25) 위에 돌출부(B 부위)가 형성된 제 1캐패시터전극(31)을 형성시킨다.Subsequently, as shown in FIG. 2B, the pillar oxide film on the upper portion of the capacitor electrode pattern is wet-etched between the polysilicon sidewalls 30 to be cylindrically formed by the polysilicon sidewalls, and the upper side protrudes on the nitride film sidewall 25. The first capacitor electrode 31 having the protrusion B portion is formed.
그리고 제 2 도의 (사)와 같이, 제 1캐패시터전극(31) 위에 유전체막(32)을 형성시키고, 유전체막 위에 제 2캐패시터전극(31-1)을 형성시킨다.As shown in FIG. 2, the dielectric film 32 is formed on the first capacitor electrode 31, and the second capacitor electrode 31-1 is formed on the dielectric film.
본 발명에 의한 반도체 기억소자의 캐패시터 제조방법에서는 캐패시터전극이 2중의 실린더형으로 형성되도록 하여 캐패시터전극의 표면적이 증가되었고, 이로 인하여 캐패시터의 정전용량이 증대되었다.In the method for manufacturing a capacitor of a semiconductor memory device according to the present invention, the capacitor electrode is formed in a double cylindrical shape, thereby increasing the surface area of the capacitor electrode, thereby increasing the capacitance of the capacitor.
제 1 도는 종래의 반도채 기억소자의 캐패시터 제조방법의 일실시예를 도시한 단면도1 is a cross-sectional view showing an embodiment of a method of manufacturing a capacitor of a conventional semiconductor memory device.
제 2 도는 본 발명에 의한 반도체 기억소자의 캐패시터 제조방법의 일실시예를 도시한 단면도2 is a cross-sectional view showing an embodiment of a capacitor manufacturing method of a semiconductor memory device according to the present invention.
※ 도면의 주요부분에 대한 부호의 설명 ※※ Explanation of code about main part of drawing ※
10.20. 반도체기판 11.21. 층간절연막10.20. Semiconductor Substrate 11.21. Interlayer insulation film
12,22. 질화막 13.24. 접촉창12,22. Nitride Film 13.24. Contact window
14.26.26'. 다결정실리콘층 15.28. 기둥산화막14.26.26 '. Polycrystalline Silicon Layer 15.28. Pillar oxide
16,29. 캐패시터 전극패턴 17,30. 다결정실리콘측벽16,29. Capacitor electrode pattern 17,30. Polycrystalline silicon side wall
18.31. 제 1캐패시터전극 18-1.31-1. 제 2캐패시터전극18.31. First Capacitor Electrode 18-1.31-1. Second capacitor electrode
19.32. 유전체막 23. 제1산화막19.32. Dielectric Film 23. First Oxide Film
25. 질화막측벽 27. 제2산화막25. Nitride side wall 27. Second oxide layer
A.A' ; 캐패시터 접촉부위 B ; 돌출부A.A '; Capacitor contact point B; projection part
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JPH0430568A (en) * | 1990-05-28 | 1992-02-03 | Nec Kyushu Ltd | Semiconductor device |
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