JPH0430568A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0430568A JPH0430568A JP13784890A JP13784890A JPH0430568A JP H0430568 A JPH0430568 A JP H0430568A JP 13784890 A JP13784890 A JP 13784890A JP 13784890 A JP13784890 A JP 13784890A JP H0430568 A JPH0430568 A JP H0430568A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- lower electrode
- capacitor part
- photoresist process
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に積み上げ型容量部を有
する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a stacked capacitor section.
従来、半導体装置に形成される積み上げ型容量部は、第
2図に示す様に、拡散層上に形成された下部電極4と絶
縁膜6と上部電極7とから構成され、その上部表面はな
めらかとなっており、またバターニングも直線を基調と
してなされており、それぞれのエツチング面は1枚の平
面状に形成されていた。Conventionally, a stacked capacitor section formed in a semiconductor device is composed of a lower electrode 4 formed on a diffusion layer, an insulating film 6, and an upper electrode 7, as shown in FIG. 2, and the upper surface thereof is smooth. The patterning was also done based on straight lines, and each etched surface was formed into a single plane.
上述した従来の半導体装置の容量部は表面に凹凸がなく
なめらかであるので、電極の絶縁膜に接する表面積で決
まる容量値が小さく、半導体装置のパターンの微細化が
進み容量部の面積が小さくなるとともに容量値はさらに
小さくなり、回路設計上の障害となったり回路動作のマ
ージンが小さくなると同時に、製造した半導体装置の製
品の歩留や品質の低下をもたらしていた。Since the capacitive part of the conventional semiconductor device described above has a smooth surface with no unevenness, the capacitance value determined by the surface area in contact with the insulating film of the electrode is small, and as the pattern of semiconductor devices becomes finer, the area of the capacitive part becomes smaller. At the same time, the capacitance value becomes even smaller, which becomes an obstacle in circuit design and reduces the margin of circuit operation, and at the same time causes a decline in the yield and quality of manufactured semiconductor devices.
本発明の半導体装置は、半導体基板上に順次形成された
下部電極と絶縁膜と上部電極とからなる積み上げ型容量
部を有する半導体装置に於て、前記積み上げ型容量部は
凹凸状に形成されているものである。A semiconductor device of the present invention has a stacked capacitor section including a lower electrode, an insulating film, and an upper electrode sequentially formed on a semiconductor substrate, wherein the stacked capacitor section is formed in an uneven shape. It is something that exists.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(C)は本発明の一実施例を説明するた
めの製造工程順に示した半導体チップの断面図である。FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps to explain one embodiment of the present invention.
まず第1図(a)に示す様に、フォトレジスト工程を用
いた選択拡散法により、半導体基板1の主表面の容量部
形成領域にPまたはAsを導入し不純物の拡散層2を形
成する。次に全面にS i 02等からなる絶縁膜3を
形成したのち、フォトレジスト工程を経て拡散層2の上
にコンタクト開孔を形成する。First, as shown in FIG. 1(a), P or As is introduced into the capacitor formation region on the main surface of the semiconductor substrate 1 to form an impurity diffusion layer 2 by selective diffusion using a photoresist process. Next, after forming an insulating film 3 made of SiO2 or the like over the entire surface, contact openings are formed on the diffusion layer 2 through a photoresist process.
次いで第1図(b)に示す様に、絶縁膜3及びコンタク
ト開孔上にアルミニウム、多結晶シリコンなどの金属薄
膜を形成し、かつ、フォトレジスト工程を経て電荷蓄積
用の下部電極4を形成する。次でこの下部電極4に複数
の溝5を形成する。Next, as shown in FIG. 1(b), a metal thin film such as aluminum or polycrystalline silicon is formed on the insulating film 3 and the contact opening, and a lower electrode 4 for charge storage is formed through a photoresist process. do. Next, a plurality of grooves 5 are formed in this lower electrode 4.
次に第1図(c)に示すように、下部電8ii4と絶縁
JI3の上に容量部の電極間誘電体となるべき絶縁膜6
を5i02等により形成し、さらにその絶縁膜6上にア
ルミニウム、多結晶シリコンなとて上部電極7を形成す
ることにより容量部が完成する。Next, as shown in FIG. 1(c), an insulating film 6 which is to be a dielectric between the electrodes of the capacitive part is placed on the lower electrode 8ii4 and the insulating JI3.
A capacitor section is completed by forming an upper electrode 7 made of aluminum or polycrystalline silicon on the insulating film 6.
このように本実施例によれば、容量部が凹凸状に形成さ
れているため、容量値は大きくなる。As described above, according to this embodiment, since the capacitor portion is formed in an uneven shape, the capacitance value becomes large.
以上説明した様に本発明は、積み上げ型容量部を凹凸状
に形成することにより、電極の表面積で決まる容量値を
大きくすることができる。従って、回路設計上の障害を
無くし、回路動作のマージンを大きくとれ、微細パター
ン化にも十分対応できる半導体装置が得られるという効
果がある。As described above, the present invention can increase the capacitance value determined by the surface area of the electrode by forming the stacked capacitor portion in an uneven shape. Therefore, it is possible to obtain a semiconductor device that eliminates obstacles in circuit design, provides a large margin for circuit operation, and is fully compatible with fine patterning.
第1図(a)〜(c)は、本発明の一実施例を説明する
ための断面図、第2図は従来例の断面図である。
1・・・半導体基板、2・・・拡散層、3・・・絶縁膜
、4・・・下部電極、5・・・溝、6・・・絶縁膜、7
・・・上部電極。FIGS. 1(a) to (c) are sectional views for explaining one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffusion layer, 3... Insulating film, 4... Lower electrode, 5... Groove, 6... Insulating film, 7
...Top electrode.
Claims (1)
部電極とからなる積み上げ型容量部を有する半導体装置
に於て、前記積み上げ型容量部は凹凸状に形成されてい
ることを特徴とする半導体装置。A semiconductor device having a stacked capacitor section including a lower electrode, an insulating film, and an upper electrode sequentially formed on a semiconductor substrate, wherein the stacked capacitor section is formed in an uneven shape. Device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13784890A JPH0430568A (en) | 1990-05-28 | 1990-05-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13784890A JPH0430568A (en) | 1990-05-28 | 1990-05-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0430568A true JPH0430568A (en) | 1992-02-03 |
Family
ID=15208222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13784890A Pending JPH0430568A (en) | 1990-05-28 | 1990-05-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0430568A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100384791B1 (en) * | 1995-12-21 | 2003-08-21 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor semiconductor memory device |
US7749852B2 (en) | 2005-08-10 | 2010-07-06 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with passivation layers on dielectric layers |
-
1990
- 1990-05-28 JP JP13784890A patent/JPH0430568A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100384791B1 (en) * | 1995-12-21 | 2003-08-21 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor semiconductor memory device |
US7749852B2 (en) | 2005-08-10 | 2010-07-06 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with passivation layers on dielectric layers |
US8017490B2 (en) | 2005-08-10 | 2011-09-13 | Samsung Electronics Co., Ltd. | Methods of forming metal-insulator-metal (MIM) capacitors with passivation layers on dielectric layers |
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