KR20040057628A - Method for fabricating capacitor of semicoductor device - Google Patents
Method for fabricating capacitor of semicoductor device Download PDFInfo
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- KR20040057628A KR20040057628A KR1020020084395A KR20020084395A KR20040057628A KR 20040057628 A KR20040057628 A KR 20040057628A KR 1020020084395 A KR1020020084395 A KR 1020020084395A KR 20020084395 A KR20020084395 A KR 20020084395A KR 20040057628 A KR20040057628 A KR 20040057628A
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- film
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- 239000003990 capacitor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000012528 membrane Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 캐패시터 제조방법에 관한 것으로서, 보다 상세하게는 반도체소자의 실린더형 캐패시터 제조시에 캐패시터의 쓰러짐 현상을 방지할 수 있는 반도체소자의 캐패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a capacitor of a semiconductor device capable of preventing the capacitor from falling when manufacturing a cylindrical capacitor of the semiconductor device.
종래기술에 따른 반도체소자의 캐패시터 제조방법을 도 1 및 도 2를 참조하여 설명하면 다음과 같다.A capacitor manufacturing method of a semiconductor device according to the prior art will be described with reference to FIGS. 1 and 2 as follows.
도 1은 종래기술에 따른 반도체소자의 캐패시터의 평면도로서, 전하저장전극만 존재하고 지지대가 형성되어 있지 않은 상태를 도시한 평면도이다.1 is a plan view of a capacitor of a semiconductor device according to the prior art, in which only a charge storage electrode exists and a support is not formed.
도 2a 내지 도 2c는 도 1의 Ⅱ-Ⅱ선에 따른 단면도로서, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views taken along the line II-II of FIG. 1 and are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.
종래기술에 따른 반도체소자의 캐패시터 제조방법을 설명하면, 먼저 도 2a에 도시된 바와같이, 반도체기판(11)상에 절연막(13)을 증착한후 이를 선택적으로 제거하여 플러그형성용 제1콘택홀(15)을 형성한다.Referring to a method of manufacturing a capacitor of a semiconductor device according to the related art, first, as shown in FIG. 2A, an insulating layer 13 is deposited on a semiconductor substrate 11 and then selectively removed to form a first contact hole for plug formation. (15) is formed.
그다음, 상기 제1콘택홀(15)을 포함한 절연막(13)상에 폴리실리콘을 증착하여 제1콘택홀을 매립한후 이를 평탄화시켜 콘택플러그(17)을 형성하고 이어 전체 구조의 상면에 식각정지막(19) 및 희생산화막(21)을 차례로 증착한다.Then, polysilicon is deposited on the insulating film 13 including the first contact hole 15 to fill the first contact hole, and then planarize the contact plug 17 to form a contact plug 17. Then, the etch stop is formed on the upper surface of the entire structure. The film 19 and the sacrificial oxide film 21 are sequentially deposited.
이어서, 도 2b에 도시된 바와같이, 상기 콘택플러그(17)상면을 노출시키면서 캐패시터 형성영역에 해당하는 상기 희생산화막(21)과 식각정지막(19)부분을 순차적으로 제거하여 제2콘택홀(23)을 형성한다.Subsequently, as shown in FIG. 2B, the sacrificial oxide layer 21 and the etch stop layer 19 corresponding to the capacitor formation region are sequentially removed while exposing the top surface of the contact plug 17 to form a second contact hole. 23).
그다음, 상기 제2콘택홀(23)을 포함한 희생산화막(21)상에 일정 두께로 전하저장 전극용 도전막(25)을 증착한후 전하저장전극간 분리를 위한 공정을 통해 상기 희생산화막(21)을 제거하여 실린더형 구조의 캐패시터의 전하저장전극(25a)을 형성한다.Subsequently, a conductive film 25 for charge storage electrodes is deposited on the sacrificial oxide film 21 including the second contact hole 23 at a predetermined thickness, and then the sacrificial oxide film 21 is separated through a process for separation between charge storage electrodes. ) Is removed to form the charge storage electrode 25a of the capacitor of the cylindrical structure.
종래기술에 의하면 종래에는 실린더의 높이가 높은 상태에서 바닥부분에서 주로 지지대를 형성했는데 이렇게 할 경우 그 효과가 미미할 뿐아니라 전하축적 용량의 감소를 초래하므로써 실제 적용시에는 그에 따른 효과가 없다.According to the prior art, the support is formed in the bottom part in the state where the height of the cylinder is high, but this effect is not only insignificant but also causes a decrease in the charge storage capacity.
특히, 도 1 및 도 2c에서와 같이, 전하축적 전극만 존재하고 그 어떤 지지대도 없는 상태가 되므로 인해 결국 실린더형의 캐패시터를 구성하는 전하축적전극이 쓰러지게 되는 현상이 발생하게 된다.In particular, as shown in FIG. 1 and FIG. 2C, since only the charge storage electrode exists and there is no support, a phenomenon in which the charge storage electrode constituting the cylindrical capacitor collapses eventually occurs.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 높은 전하축적 용량을 얻기 위해 적용하는 실린더 캐패시터 형성시의 전하축적 전극의 쓰러짐 현상을 방지할 수 있는 반도체소자의 캐패시터 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, a method of manufacturing a capacitor of a semiconductor device that can prevent the collapse of the charge storage electrode when forming a cylinder capacitor applied to obtain a high charge storage capacity. The purpose is to provide.
도 1은 종래기술에 따른 반도체소자의 캐패시터의 평면도로서, 전하저장전극 만 존재하고 지지대가 형성되어 있지 않은 상태를 도시한 평면도,1 is a plan view of a capacitor of a semiconductor device according to the prior art, a plan view showing a state in which only a charge storage electrode exists and a support is not formed;
도 2a 내지 도 2c는 도 1의 Ⅱ-Ⅱ선에 따른 단면도로서, 종래기술에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도,2A to 2C are cross-sectional views taken along line II-II of FIG. 1, and a process cross-sectional view illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art;
도 3a은 본 발명에 따른 반도체소자의 캐패시터 평면도로서, 전하저장전극의 단축방향에서 지지대를 형성한 경우의 평면도이고, 도 3b는 본 발명에 따른 반도체소자의 캐패시터 평면도로서, 전하저장전극의 장축방향에서 지지대를 형성한 경우의 평면도,3A is a plan view of a capacitor of a semiconductor device according to the present invention, which is a plan view of a case in which a support is formed in a minor direction of the charge storage electrode, and FIG. Floor plan when the support is formed in
도 4a 내지 도 4c는 도 3b의 Ⅳ-Ⅳ선에 따른 단면도로서, 본 발명에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도.4A to 4C are cross-sectional views taken along line IV-IV of FIG. 3B, and are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
31 : 반도체기판 33 : 절연막31 semiconductor substrate 33 insulating film
35 : 플러그 콘택홀 37 : 콘택플러그35: plug contact hole 37: contact plug
39 : 식각정지막 41 : 제1희생산화막39: etching stop film 41: first rare film
43 : 지지대막 45 : 제2희생산화막43: support curtain 45: second rare production film
47 : 전하저장전극용 콘택홀 49 : 폴리실리콘층47: contact hole for charge storage electrode 49: polysilicon layer
49a : 전하저장전극49a: charge storage electrode
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 캐패시터 제조 방법은, 반도체기판상에 식각정지막과 제1희생산화막을 차례로 형성하는 단계; 상기 제1희생산화막상에 라인 형태의 지지대막을 형성하는 단계; 상기 라인 형태의 지지대막을 포함한 제1희생산화막상에 제2희생산화막을 형성하는 단계; 상기 제2희생산화막과 지지대막 및 제1희생산화막을 차례로 식각하여 콘택홀을 형성하는 단계; 및 상기 콘택홀표면상에 전하저장전극을 형성한후 상기 제2희생산화막과 1희생산화막을 제거하여 실린더 형태의 전하저장전극을 완성하는 단계를 포함하여 구성되는 것을 특징으로한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: sequentially forming an etch stop film and a first rare production film on a semiconductor substrate; Forming a support membrane in the form of a line on the first rare production film; Forming a second rare production layer on the first rare production layer including the line-type support layer; Forming a contact hole by sequentially etching the second rare production film, the support layer, and the first rare production film; And forming a charge storage electrode on the surface of the contact hole, and then removing the second rare production film and the rare production film to complete a cylinder-type charge storage electrode.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 캐패시터 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a은 본 발명에 따른 반도체소자의 캐패시터 평면도로서, 전하저장전극의 단축방향에서 지지대를 형성한 경우의 평면도이고, 도 3b는 본 발명에 따른 반도체소자의 캐패시터 평면도로서, 전하저장전극의 장축방향에서 지지대를 형성한 경우의 평면도이다.3A is a plan view of a capacitor of a semiconductor device according to the present invention, which is a plan view of a case in which a support is formed in a minor direction of the charge storage electrode, and FIG. Is a plan view of the case where the support is formed.
도 4a 내지 도 4c는 도 3b의 Ⅳ-Ⅳ선에 따른 단면도로서, 본 발명에 따른 반도체소자의 캐패시터 제조방법을 설명하기 위한 공정단면도이다.4A to 4C are cross-sectional views taken along line IV-IV of FIG. 3B and are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 캐패시터 제조방법에 대해 설명하면, 먼저 도 4a에 도시된 바와 같이, 반도체기판(31)상에 절연막(33)을 증착한후 이를 선택적으로 제거하여 플러그형성용 제1콘택홀(35)을 형성한다.Referring to a method of manufacturing a capacitor of a semiconductor device according to the present invention, as shown in FIG. 4A, first, an insulating film 33 is deposited on a semiconductor substrate 31 and then selectively removed to form a first contact for forming a plug. The hole 35 is formed.
그다음, 상기 제1콘택홀(35)을 포함한 절연막(33)상에 폴리실리콘을 증착하여 제1콘택홀을 매립한후 이를 평탄화시켜 콘택플러그(37)을 형성하고 이어 전체 구조의 상면에 식각정지막(39) 및 제1희생산화막(41)을 차례로 증착한다.Next, polysilicon is deposited on the insulating film 33 including the first contact hole 35 to fill the first contact hole, and then planarize it to form a contact plug 37, and then etch stop on the upper surface of the entire structure. The film 39 and the first rare film 41 are deposited in this order.
이어서, 상기 제1희생산화막(41)상에 실리콘나이트라이드 재질로 이루어진 지지대막(43)을 형성한후 상기 지지대막(43)을 아주 가늘면서 라인 형태로 정의하여 식각한다. 또한, 상기 지지대막(43)은 X축, Y축으로 가늘게 형성하는데, 어느 한쪽만 형성해도 무방하다.Subsequently, after forming the support layer 43 made of silicon nitride on the first rare production layer 41, the support layer 43 is defined as a very thin line and etched. In addition, the support membrane 43 is thinly formed in the X-axis and the Y-axis, but may be formed in any one.
그다음, 상기 어느 한쪽 방향의 지지대막(43)을 형성한후 그 위에 제2희생산화막(45)을 증착한다.Next, after forming the support base film 43 in any one direction, the second thin film 45 is deposited thereon.
이어서, 도 4b에 도시된 바와같이, 상기 콘택플러그(37)상에 전하저장전극을 형성하기 위하여 상기 제2희생산화막(45), 지지대막(43) 및 제1희생산화막(41)을 차례로 식각하여 상기 콘택플러그(37)을 상면을 노출시키는 전하저장전극 형성용 콘택홀(47)을 형성한다.Subsequently, as shown in FIG. 4B, in order to form a charge storage electrode on the contact plug 37, the second rare production layer 45, the support base layer 43, and the first rare production layer 41 are sequentially etched. As a result, a contact hole 47 for forming a charge storage electrode exposing the top surface of the contact plug 37 is formed.
그다음, 상기 전하저장전극 형성용 콘택홀(47)을 포함한 제2희생산화막(45)상에 전하저장 전극용 폴리실리콘층(49)을 증착한후 전하저장전극간을 분리하기 위한 공정을 진행한다.Thereafter, a polysilicon layer 49 for charge storage electrodes is deposited on the second rare metal film 45 including the contact hole 47 for forming a charge storage electrode, and then a process for separating the charge storage electrodes is performed. .
이어서, 도 4c에 도시된 바와같이, 습식식각방법을 통해 상기 제2희생산화막(45)을 제거하고, 제1희생산화막(41)은 상기 지지대막(43)이 없는 부분을 통해 습식 에천트가 들어가 제거되도록 하여 제2희생산화막(45)과 제1희생산화막(41)을 완전히 제거하여 실린더 형태의 전하저장전극(49a)을 형성한다.Subsequently, as shown in FIG. 4C, the second rare production layer 45 is removed by a wet etching method, and the first rare production layer 41 has a wet etchant through the portion without the support layer 43. The second rare production film 45 and the first rare production film 41 are completely removed to form a cylindrical charge storage electrode 49a.
이후, 도면에는 도시하지 않았지만, 상기 전하저장전극(49a)의 표면상에 유전체막과 상부전극을 순차적으로 형성하여 실린더 구조의 캐패시터를 완성한다.Subsequently, although not shown in the drawing, a dielectric film and an upper electrode are sequentially formed on the surface of the charge storage electrode 49a to complete the capacitor of the cylinder structure.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 캐패시터 제조방법에 의하면, 높은 실린더 캐패시터를 형성하더라도 지지대막을 형성하여 캐패시터를 지지해 주게 되므로써 쓰러짐 현상이 발생하는 것을 방지할 수 있다.As described above, according to the method of manufacturing a capacitor of a semiconductor device according to the present invention, even if a high cylinder capacitor is formed, a support layer is formed to support the capacitor, thereby preventing a fall phenomenon.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
Claims (5)
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| KR1020020084395A KR20040057628A (en) | 2002-12-26 | 2002-12-26 | Method for fabricating capacitor of semicoductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100622284B1 (en) * | 2004-06-03 | 2006-09-14 | 삼성전자주식회사 | Method for forming storage node of capacitor |
| KR100655751B1 (en) * | 2004-10-01 | 2006-12-11 | 삼성전자주식회사 | method of manufacturing a semiconductor device |
| KR100900148B1 (en) * | 2007-10-31 | 2009-06-01 | 주식회사 하이닉스반도체 | Semicoductor device and method of fabricating the same |
| KR100948092B1 (en) * | 2006-12-27 | 2010-03-16 | 주식회사 하이닉스반도체 | Method for forming capacitor in semiconductor device |
| KR101357303B1 (en) * | 2007-07-10 | 2014-01-28 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same semiconductor |
-
2002
- 2002-12-26 KR KR1020020084395A patent/KR20040057628A/en not_active Application Discontinuation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100622284B1 (en) * | 2004-06-03 | 2006-09-14 | 삼성전자주식회사 | Method for forming storage node of capacitor |
| KR100655751B1 (en) * | 2004-10-01 | 2006-12-11 | 삼성전자주식회사 | method of manufacturing a semiconductor device |
| KR100948092B1 (en) * | 2006-12-27 | 2010-03-16 | 주식회사 하이닉스반도체 | Method for forming capacitor in semiconductor device |
| KR101357303B1 (en) * | 2007-07-10 | 2014-01-28 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same semiconductor |
| KR100900148B1 (en) * | 2007-10-31 | 2009-06-01 | 주식회사 하이닉스반도체 | Semicoductor device and method of fabricating the same |
| US7767565B2 (en) | 2007-10-31 | 2010-08-03 | Hynix Semiconductor Inc. | Semiconductor device and method of fabricating the same |
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