KR20010004932A - method of forming cylindrical capacitor of semiconductor device - Google Patents
method of forming cylindrical capacitor of semiconductor device Download PDFInfo
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- KR20010004932A KR20010004932A KR1019990025700A KR19990025700A KR20010004932A KR 20010004932 A KR20010004932 A KR 20010004932A KR 1019990025700 A KR1019990025700 A KR 1019990025700A KR 19990025700 A KR19990025700 A KR 19990025700A KR 20010004932 A KR20010004932 A KR 20010004932A
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- A—HUMAN NECESSITIES
- A41—WEARING APPAREL
- A41B—SHIRTS; UNDERWEAR; BABY LINEN; HANDKERCHIEFS
- A41B9/00—Undergarments
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- A—HUMAN NECESSITIES
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- A—HUMAN NECESSITIES
- A41—WEARING APPAREL
- A41B—SHIRTS; UNDERWEAR; BABY LINEN; HANDKERCHIEFS
- A41B2400/00—Functions or special features of shirts, underwear, baby linen or handkerchiefs not provided for in other groups of this subclass
- A41B2400/32—Therapeutic use
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Abstract
Description
본 발명은 반도체 소자의 실린더형 캐패시터 형성 방법에 관한 것으로서, 보다 구체적으로는 실린더 구조의 내벽에 엠보싱 형상이 구비된 캐패시터를 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a cylindrical capacitor of a semiconductor device, and more particularly to a method of forming a capacitor having an embossed shape on the inner wall of the cylinder structure.
최근 반도체 제조 기술의 발달과 더불어 메모리 소자의 수요가 급증함에 따라 좁은 면적에 높은 캐패시턴스를 요구하게 되었다.Recently, with the development of semiconductor manufacturing technology, the demand for memory devices has increased so that high capacitance is required in a small area.
캐패시터의 정전용량(capacitance)은 유전체의 유전율과 면적에 비례하고, 두께에 반비례한다. 그런데, 소자가 고집적화되어 감에 따라, 캐패시터 용량을 극대화하기 위한 방법으로는, 전극간의 유전체를 고유전율을 갖는 절연체를 이용하거나, 전극의 면적을 확대시키는 방법 또는 유전체의 두께를 줄이는 방법 등이 제안되었다. 이에 반도체 메모리 소자의 고집적화에 대한 고용량을 제공하기 위하여, 기존에는 유전체로서 SiO2/Si3N4또는 Ta2O5등이 이용되고, 전극 면적을 확장시키는 방법으로는 스토리지 전극을 실린더 구조로 형성하였다.The capacitance of the capacitor is proportional to the dielectric constant and area of the dielectric and inversely proportional to the thickness. However, as the device becomes more integrated, a method for maximizing the capacitor capacity is proposed by using an insulator having a high dielectric constant for the dielectric between the electrodes, a method of enlarging the electrode area, or reducing the thickness of the dielectric. It became. In order to provide high capacity for high integration of semiconductor memory devices, conventionally, SiO 2 / Si 3 N 4 or Ta 2 O 5 is used as a dielectric, and the storage electrode is formed in a cylindrical structure as a method of expanding the electrode area. It was.
종래의 실린더형 캐패시터를 제조하는 방법은 다음과 같다. 먼저, 반도체 기판 전면에 층간 절연막을 형성하고, 층간 절연막을 식각하여 캐패시터용 콘택홀을 형성한다. 그런 다음, 층간절연막 상에 제 1 폴리실리콘막을 증착하여 콘택홀을 제 1 폴리실리콘으로 매립한다. 이어서, 코어 산화막을 제 1 폴리실리콘상에 증착한다.A method of manufacturing a conventional cylindrical capacitor is as follows. First, an interlayer insulating film is formed over the entire semiconductor substrate, and the interlayer insulating film is etched to form a contact hole for a capacitor. Then, a first polysilicon film is deposited on the interlayer insulating film to fill the contact hole with the first polysilicon. Subsequently, a core oxide film is deposited on the first polysilicon.
그런 다음, 환상 구조의 포토레지스트 패턴을 식각 마스크로 하여 코어 산화막을 식각하므로써, 실린더 구조의 코어 산화막을 형성한다. 그리고 나서, 코어 산화막의 내벽에 제 2 폴리실리콘막을 증착한다. 캐패시터의 표면적을 증가시키기 위해, 울퉁불퉁한 구조인 엠보싱 형상의 준안정성 폴리실리콘(6:Metastable Poly Silicon, 이하 MPS라 영문표기함)을 제 2 폴리실리콘막의 내벽에 증착한다.Then, the core oxide film is etched by using the ring-shaped photoresist pattern as an etching mask, thereby forming a core oxide film having a cylinder structure. Then, a second polysilicon film is deposited on the inner wall of the core oxide film. In order to increase the surface area of the capacitor, an embossed, metastable polysilicon (hereinafter referred to as MPS), which is a rugged structure, is deposited on the inner wall of the second polysilicon film.
이어서, 전체 결과물상에 포토레지스트을 도포하여, 실린더 구조 내부를 포토레지스트로 매립한다. 그런 다음, 화학기계적 연마법으로 전체 결과물을 연마하면, 포토레지스트의 일정 두께가 제거됨과 동시에 코어 산화막도 일정 두께가 제거되므로써, 제 2 폴리실리콘과 MPS 상단이 노출된다. 실린더 구조 내부에 있는 포토레지스트를 제거하면, 실린더 구조이면서 엠보싱 형상을 갖는 캐패시터가 완성된다.Then, photoresist is applied on the entire resultant, and the inside of the cylinder structure is embedded with photoresist. Then, when the entire result is polished by the chemical mechanical polishing method, the predetermined thickness of the photoresist is removed and the core oxide film is also removed, thereby exposing the second polysilicon and the top of the MPS. By removing the photoresist inside the cylinder structure, a capacitor having a cylindrical structure and having an embossed shape is completed.
상기된 종래의 캐패시터 형성 방법에 있어서, MPS를 형성하는 단계에서, 실린더 형상의 제 2 폴리실리콘막의 내외벽이 모두 노출되어 있으므로, MPS는 제 2 폴리실리콘막의 내벽 뿐만이 아니라 외벽에도 형성된다. 이로 인하여, 패턴 간격이 미세한 제 2 폴리실리콘막의 외벽간의 거리가 MPS로 인해 더욱 좁아지게 되므로써, MPS들간에 전기적 쇼트가 발생될 소지가 상당히 높다.In the above-described conventional capacitor forming method, since the inner and outer walls of the cylindrical second polysilicon film are all exposed in the step of forming the MPS, the MPS is formed not only on the inner wall but also on the outer wall of the second polysilicon film. As a result, the distance between the outer walls of the second polysilicon film having a fine pattern interval is further narrowed due to the MPS, so that there is a high possibility that an electric short is generated between the MPSs.
본 발명은 상기된 종래 캐패시터 형성 방법이 안고 있는 문제점을 해소하기 위해 안출된 것으로서, MPS가 실린더 형상의 제 2 폴리실리콘막의 내벽에만 형성되도록 하여, 각 MPS들이 전기적으로 쇼트되는 현상을 방지할 수 있는 반도체 소자의 실린더형 캐패시터 형성 방법을 제공하는데 목적이 있다.The present invention has been made to solve the problems of the conventional capacitor formation method described above, MPS is formed only on the inner wall of the cylindrical second polysilicon film, it is possible to prevent the phenomenon that each MPS is electrically shorted It is an object to provide a method of forming a cylindrical capacitor of a semiconductor device.
도 1 내지 도 7은 본 발명에 따른 캐패시터 형성 방법을 순차적으로 나타낸 단면도.1 to 7 are cross-sectional views sequentially showing a capacitor forming method according to the present invention.
- 도면의 주요 부분에 대한 부호의 설명 -Description of symbols for the main parts of the drawings
1 ; 제 1 절연막 2 ; 콘택홀One ; 1st insulating film 2; Contact hole
3 ; 제 1 폴리실리콘막 4 ; 코어 산화막3; 1st polysilicon film 4; Core oxide film
5 ; 제 2 절연막 6 ; 제 2 폴리실리콘막5; 2nd insulating film 6; Second polysilicon film
7 ; MPS7; MPS
상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 캐패시터 형성 방법은 다음과 같다.In order to achieve the above object, a method of forming a capacitor according to the present invention is as follows.
반도체 기판상에 제 1 절연막을 증착한 후, 제 1 절연막을 식각하여 콘택홀을 형성한다. 코어 산화막을 제 1 절연막상에 증착한 후, 환상 구조의 포토레지스트 패턴을 식각 마스크로 하여 코어 산화막을 식각한 다음 포토레지스트 패턴을 제거하면, 실린더 형상의 코어 산화막이 형성된다. 그런 다음, 코어 산화막과 식각 선택비가 다른 제 2 절연막을 전체 구조 표면에 얇게 증착한 후, 코어 산화막 표면과 제 1 폴리실리콘막 및 제 1 절연막상에 있는 제 2 절연막 부분을 제거하여, 코어 산화막의 측벽에만 제 2 산화막이 남도록 한다.After depositing a first insulating film on the semiconductor substrate, the first insulating film is etched to form contact holes. After the core oxide film is deposited on the first insulating film, the core oxide film is etched using the ring-shaped photoresist pattern as an etching mask, and then the photoresist pattern is removed, thereby forming a cylindrical core oxide film. Then, the second insulating film having a different etching selectivity from the core oxide film is deposited thinly on the entire structure surface, and then the second insulating film portion on the surface of the core oxide film, the first polysilicon film and the first insulating film is removed to remove the core oxide film. The second oxide film remains only on the sidewalls.
제 2 폴리실리콘막을 전체 결과물 표면에 증착한 후, 코어 산화막과 제 2 절연막 상단에 있는 제 2 폴리실리콘막 부분을 식각하여 제거한다. 이어서, 코어 산화막만을 습식 식각하여 제거하면, 코어 산화막과 식각 선택비다 다른 제 2 절연막을 제거되지 않으므로, 실린더 형상의 제 2 폴리실리콘막의 외벽은 제 2 절연막으로 둘러싸이게 된다.After the second polysilicon film is deposited on the entire resultant surface, the core oxide film and the second polysilicon film portion on the top of the second insulating film are etched and removed. Subsequently, when only the core oxide film is wet-etched and removed, since the second insulating film different from the core oxide film and the etching selectivity is not removed, the outer wall of the cylindrical second polysilicon film is surrounded by the second insulating film.
이어서, 엠보싱 형상의 준안정성 폴리실리콘막을 증착하는데, 제 2 폴리실리콘막의 외벽은 제 2 절연막으로 둘러싸여 있으므로, 준안정성 폴리실리콘막은 제 2 폴리실리콘막의 내벽에만 증착된다.Subsequently, an embossed metastable polysilicon film is deposited. Since the outer wall of the second polysilicon film is surrounded by the second insulating film, the metastable polysilicon film is deposited only on the inner wall of the second polysilicon film.
상기된 본 발명의 구성에 의하면, 제 2 폴리실리콘막 증착전에 제 2 절연막을 증착한 후 코어 산화막만을 제거하면, 제 2 폴리실리콘막의 외벽이 제 2 절연막으로 둘러싸이게 된다. 따라서, MPS는 제 2 절연막에는 증착되지 않고 오직 제 2 폴리실리콘막의 내벽에만 증착되므로써, 각각의 MPS가 쇼트되는 경우가 근원적으로 방지된다.According to the above-described configuration of the present invention, if only the core oxide film is removed after the second insulating film is deposited before the deposition of the second polysilicon film, the outer wall of the second polysilicon film is surrounded by the second insulating film. Therefore, the MPS is not deposited on the second insulating film but only on the inner wall of the second polysilicon film, so that the case where each MPS is shorted is fundamentally prevented.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.
도 1 내지 도 7은 본 발명에 따른 실린더형 캐패시터를 제조 과정 순서대로 순차적으로 나타낸 단면도이다.1 to 7 are cross-sectional views sequentially showing a cylindrical capacitor according to the present invention in the order of manufacturing process.
먼저, 도 1에 도시된 바와 같이, 반도체 기판(미도시)상에 제 1 절연막(1)을 증착한 후, 제 1 절연막(1)을 식각하여 콘택홀(2)을 형성한다. 그런 다음, 제 1 폴리실리콘막(3)으로 콘택홀(2)을 매립한 후, 전체 결과물상에 코어 산화막(4)을 증착한다.First, as shown in FIG. 1, after depositing a first insulating film 1 on a semiconductor substrate (not shown), the first insulating film 1 is etched to form a contact hole 2. Then, after filling the contact hole 2 with the first polysilicon film 3, the core oxide film 4 is deposited on the entire resultant.
이어서, 도 2와 같이, 실린더 형상의 포토레지스트 패턴(미도시)을 식각 마스크로 하여 코어 산화막(4)을 식각하므로써, 제 1 폴리실리콘막(3)을 노출시키는 실린더 형상의 코어 산화막(4)을 형성한다. 그런 다음, 본 발명에서 제시되는 제 2 절연막(5)을 전체 결과물 표면에 100Å 이하의 두께로 얇게 증착한다. 여기서, 제 2 절연막(5)으로는 코어 산화막(4)과 식각 선택비가 다른 재질을 사용한다.Next, as shown in FIG. 2, the core oxide film 4 exposing the first polysilicon film 3 by etching the core oxide film 4 by using a cylindrical photoresist pattern (not shown) as an etching mask. To form. Then, the second insulating film 5 proposed in the present invention is thinly deposited on the entire resultant surface to a thickness of 100 kPa or less. As the second insulating film 5, a material having a different etching selectivity from that of the core oxide film 4 is used.
이어서, 도 3과 같이, 전체 결과물에 대해 전면 식각을 실시하여, 코어 산화막(4) 표면과 제 1 절연막(1) 및 제 1 폴리실리콘막(3) 표면에 있는 제 2 절연막(5) 부분을 제거한다. 따라서, 제 2 절연막(5)은 코어 산화막(4)의 측벽에만 남는 스페이서 형태로 구현된다.Subsequently, as shown in FIG. 3, the entire resultant is etched, and the portion of the second insulating film 5 on the surface of the core oxide film 4 and the surface of the first insulating film 1 and the first polysilicon film 3 is removed. Remove Therefore, the second insulating film 5 is implemented in the form of a spacer that remains only on the sidewall of the core oxide film 4.
그런 다음, 도 4와 같이 전체 결과물상에 제 2 폴리실리콘막(6)을 증착한다. 이어서, 도 5를 참조로, 실린더 구조 내부를 필링 산화막(미도시)으로 매립한 후, 전체 결과물 표면을 화학기계적 연마법으로 연마하여 일정 두께를 제거한다. 그러면, 코어 산화막(4)과 제 2 절연막(5) 상단에 있는 제 2 폴리실리콘막(6)이 제거되므로써, 코어 산화막(4)과 제 2 절연막(5) 상단이 노출된다.Then, the second polysilicon film 6 is deposited on the entire resultant product as shown in FIG. 4. Subsequently, referring to FIG. 5, after filling the inside of the cylinder structure with a peeling oxide film (not shown), the entire resultant surface is polished by chemical mechanical polishing to remove a certain thickness. Then, the second polysilicon film 6 on the upper end of the core oxide film 4 and the second insulating film 5 is removed, so that the upper ends of the core oxide film 4 and the second insulating film 5 are exposed.
이어서, 도 6과 같이 코어 산화막(4)을 습식 식각하여 제거한다. 이때, 코어 산화막(4)과 제 2 절연막(5)의 식각 선택비는 서로 다므르로, 제 2 절연막(5)은 식각되지 않고 오직 코어 산화막(4)만이 식각되어 제거된다. 따라서, 제 2 폴리실리콘막(6)이 실린더 형상으로 형성되면서 그의 외벽은 제 2 절연막(5)으로 둘러싸이게 된다.Subsequently, the core oxide film 4 is wet-etched and removed as shown in FIG. 6. At this time, the etching selectivity of the core oxide film 4 and the second insulating film 5 is different from each other, so that the second insulating film 5 is not etched, and only the core oxide film 4 is etched and removed. Therefore, while the second polysilicon film 6 is formed in a cylindrical shape, its outer wall is surrounded by the second insulating film 5.
이러한 상태에서, 엠보싱 형상의 MPS(7)를 증착하면, 도 7과 같이 제 2 절연막(5)에는 MPS(7)가 성장되지 않으므로, 오직 제 2 폴리실리콘막(6)의 내벽에만 MPS(7)가 증착된다. 따라서, 각 실린더 구조의 캐패시터 외벽에는 MPS(7)가 증착되지 않게 되어, MPS(7)로 인한 쇼트가 방지된다.In such a state, when the MPS 7 having the embossed shape is deposited, the MPS 7 is not grown on the second insulating film 5 as shown in FIG. 7, and only the MPS 7 is formed on the inner wall of the second polysilicon film 6. ) Is deposited. Therefore, the MPS 7 is not deposited on the capacitor outer wall of each cylinder structure, and the short caused by the MPS 7 is prevented.
이상에서 설명한 바와 같이 본 발명에 의하면, 실린더 형상의 제 2 폴리실리콘막의 외벽이 제 2 절연막으로 둘러싸이게 하므로써, MPS가 실린더 형상의 캐패시터 외벽에는 형성되지 않고 오직 내벽에만 형성된다. 따라서, 실린더 형상의 캐패시터 외벽에 형성된 MPS로 인한 쇼트 현상이 근원적으로 방지된다.As described above, according to the present invention, the MPS is not formed on the cylindrical capacitor outer wall but only on the inner wall by causing the outer wall of the cylindrical second polysilicon film to be surrounded by the second insulating film. Therefore, a short phenomenon due to the MPS formed on the outer wall of the cylindrical capacitor is fundamentally prevented.
이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100474593B1 (en) * | 2002-07-11 | 2005-03-10 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor in semiconductor device |
KR100517908B1 (en) * | 2003-06-30 | 2005-10-04 | 주식회사 하이닉스반도체 | Semiconductor memory device and method for manufacturing the same |
KR100769791B1 (en) * | 2001-06-27 | 2007-10-25 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
KR100855263B1 (en) * | 2001-12-22 | 2008-09-01 | 주식회사 하이닉스반도체 | A method for manufacturing capacitor of semiconductor device |
KR20160080173A (en) * | 2014-12-29 | 2016-07-07 | 한국항공우주산업 주식회사 | Thickness Measuring Machine and that system |
-
1999
- 1999-06-30 KR KR1019990025700A patent/KR20010004932A/en not_active Application Discontinuation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100769791B1 (en) * | 2001-06-27 | 2007-10-25 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
KR100855263B1 (en) * | 2001-12-22 | 2008-09-01 | 주식회사 하이닉스반도체 | A method for manufacturing capacitor of semiconductor device |
KR100474593B1 (en) * | 2002-07-11 | 2005-03-10 | 주식회사 하이닉스반도체 | Method for manufacturing capacitor in semiconductor device |
KR100517908B1 (en) * | 2003-06-30 | 2005-10-04 | 주식회사 하이닉스반도체 | Semiconductor memory device and method for manufacturing the same |
KR20160080173A (en) * | 2014-12-29 | 2016-07-07 | 한국항공우주산업 주식회사 | Thickness Measuring Machine and that system |
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