KR100769791B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a capacitor of a semiconductor device, in which, in a process of forming a lower electrode of a capacitor in a semicylindrical structure, an oxide film for determining the shape of a lower electrode is divided into a lower oxide film and a lower oxide film And the lower oxide layer for forming the lower structure of the lower electrode is formed uniformly by removing only the upper oxide layer for forming the upper structure of the lower electrode in the cylinder structure according to the difference in etch selectivity, A method of manufacturing a capacitor of a semiconductor device capable of improving the reliability of the process and the capacitance distribution characteristics of the capacitor by improving the uniformity of the capacitance and improving the processability.

Bottom electrode, cup structure, cylinder structure, semi-cylinder, etch selectivity, etch uniformity

Description

[0001] The present invention relates to a method of manufacturing a capacitor of a semiconductor device,             

1A to 1F are sectional views of a device for explaining a method of manufacturing a capacitor of a semiconductor device according to the present invention.

Description of the Related Art

11: semiconductor substrate 12: first interlayer insulating film

13: contact plug 14: second interlayer insulating film

14a: first insulating film 14b: second insulating film

15: lower electrode 15a: lower structure of lower electrode

15b: upper structure of lower electrode 16: metastable poly silicon

17: dielectric film 18: upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly to a method of manufacturing a capacitor of a semiconductor device in which a lower electrode of a capacitor is formed in a semi-cylinder structure.

As the degree of integration of the device increases, the size of the device is reduced, thereby reducing the capacitance of the capacitor.

In recent years, in order to prevent the capacitance of the capacitor from being reduced, the lower electrode is formed in a three-dimensional structure such as a cup structure or a cylinder structure to be formed high, thereby increasing the surface area of the lower electrode, . Among the structure of the lower electrode, the cylindrical structure has higher capacitance than the cup structure, but is structurally unstable, causing the pattern of the lower electrode to collapse or to cause foreign matter (Defect).

In order to solve this problem, a lower electrode is formed by a semi-cylindrical structure in which a lower part of the lower electrode is formed in a cup structure and an upper part is formed in a cylindrical structure. Since the semi-cylindrical structure can lower the height of the entire structure of the lower electrode while maintaining the height of the lower electrode, the structure of the lower electrode can be stabilized and the capacitance can be secured.

Since the height of the semi-cylinder lower electrode is about 1 to 2 占 퐉 and the ratio of the lower electrode formed into the cup structure can be adjusted according to the height of the oxide film at the lower end where the lower electrode of the cup structure is formed, Can be controlled.

The height of the oxide film at the bottom of the structure is controlled by using an etching solution, and the etching time is different depending on the quality of the oxide film. However, in order to secure an electrostatic capacity, it takes a long time to remove the oxide film of about 0.5 to 1.5 탆 in the etching solution.

If the wafer is put in the etching solution for a long time, the uniformity of etching in the wafer becomes poor, and finally the electrostatic capacity distribution in the wafer becomes uneven. Therefore, the electrical characteristics and reliability of the device are deteriorated.

Therefore, in order to solve the above-mentioned problems, the present invention has been made in view of the above problems, and it is an object of the present invention to provide an oxide film for determining the shape of a lower electrode, The lower oxide film is uniformly left to form the lower structure of the lower electrode by removing only the upper oxide film for forming the cylinder structure, thereby improving the etching uniformity and uniformizing the capacitance, And it is an object of the present invention to provide a method of manufacturing a capacitor of a semiconductor device capable of improving capacitance distribution characteristics.

A method of manufacturing a capacitor of a semiconductor device according to the present invention includes sequentially forming a first insulating film and a second insulating film having different etching selection ratios on a semiconductor substrate on which a contact plug is formed in a predetermined region of an interlayer insulating film, Forming a lower electrode by forming a conductive material on the sidewalls of the second and first insulating films and the bottom surface of the first insulating film, and removing the second insulating film; And sequentially forming a dielectric film and an upper electrode on the entire surface including the lower electrode.

The etch selectivity of the first and second insulating films allows the first insulating film to have a selectivity of 3 or more with respect to the second insulating film with respect to the etching solution.

At this time, the first insulating film is formed by using a stable oxide film, or by a material which is not easily removed by HF, BOE or other oxide etching solution. Ideally, the first insulating film is formed of an undoped oxide film using TEOS or SiH ₄ gas do.

The second insulating film is formed of an oxide film having properties opposite to the first insulating film, or an oxide film easily removed in the etching solution, and ideally formed of a doped oxide film using TEOS or SiH ₄ gas.

The ratio of the cup structure, which is the lower structure occupying the lower electrode, is controlled according to the thickness of the first insulating film.

The conductive material is polysilicon, and the surface area of the lower electrode can be further increased by forming the metastable polysilicon on the surface of the lower electrode after removing the second insulating film.

A method for manufacturing a capacitor of a semiconductor device according to another embodiment of the present invention includes forming a lower electrode of a semicylinder structure having a lower structure as a cup structure and a upper structure as a cylinder structure, The sacrificial insulating film and the second sacrificial insulating film of the cylinder structure are formed of insulating films having different etch selectivities so that the cup structure and the cylinder structure ratio of the entire capacitor lower electrode are uniform.

The etch selectivity ratio of the first and second sacrificial insulating films is such that the first sacrificial insulating film has a selectivity of 3 or more with respect to the second sacrificial insulating film for the etching solution.

The first sacrificial insulating layer is formed using a stable oxide film or a material that can not be easily removed by HF, BOE or other oxide etching solution. Ideally, the first sacrificial insulating layer is formed of an undoped oxide film using TEOS or SiH ₄ gas .

The second sacrificial insulating layer is formed of an oxide layer having a property opposite to that of the first sacrificial insulating layer, or an oxide layer easily removed in the etching solution, and ideally a doped oxide layer using TEOS or SiH ₄ gas.

The ratio of the cup structure, which is the lower structure occupying the lower electrode, is controlled according to the thickness of the first sacrificial insulating film.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are sectional views of a device for explaining a method of manufacturing a capacitor of a semiconductor device according to the present invention.

1A, a first interlayer insulating film 12 is formed on a semiconductor substrate 11 formed with various elements including a transistor (not shown) through a normal process, and then a photolithography / The first interlayer insulating film 12 is removed to form a contact hole. A junction region (not shown) of the semiconductor substrate 11 is exposed by the contact hole. A conductive material is embedded in the contact hole to form the contact plug 13.

When the contact plug 13 is formed, a first insulating film 14a and a second insulating film 14b having etch selectivities different from each other are sequentially formed on the entire upper surface to form a second interlayer insulating film 14 of a two-layer structure. The second interlayer insulating film 14 is formed to a thickness of 1 to 3 mu m.

The etching selectivity ratio of the first insulating film 14a and the second insulating film 14b is such that the first insulating film 14a has a selectivity of 3 or more with respect to the second insulating film 14b with respect to the etching solution. That is, the first insulating layer 14a serves as an etching barrier layer in an etching process for removing the second insulating layer 14b in a subsequent process.

Therefore, since the first insulating film 14a remains after the final capacitor is manufactured, the first insulating film 14a can be formed using an oxide film that is stable in terms of physical properties or a material that can not be easily removed by HF, BOE, or other oxide etching solution. That is, the first insulating film (14a) is formed in a sentence prompt oxide film using TEOS gas or SiH _4.

Since the second insulating layer 14b must be removed in the subsequent etching process, the second insulating layer 14b is formed of an oxide layer having properties opposite to the first insulating layer 14b or an oxide layer easily removed in the etching solution. That is, the second insulating film (14b) is formed of a doped oxide film using a ₄ bit TEOS gas and SiH.

Further, it is preferable that the first and second insulating films 14a and 14b have a high selectivity to the etching solution. However, since the types of oxide films are not so many, the first and second insulating films 14a and 14b can be formed and used so that the etching selectivity can be 3 or more.

Referring to FIG. 1B, a predetermined region of the second and first insulating films 14b and 14a, that is, the second interlayer insulating film 14a in a predetermined region is removed by a photolithography / etching process to define a region where the lower electrode is to be formed . A predetermined area of the second and first insulating films 14b and 14a is removed, and the upper surface of the contact plug 13 formed at the lower portion is exposed.

For reference, the second interlayer insulating film 14 is generally referred to as a cap oxide layer or a sacrificial oxide film, and the shape of the capacitor lower electrode to be formed in a subsequent process is determined according to the manner in which the second interlayer insulating film 14 is etched. Among them, the first insulating film 14a is a sacrificial oxide film for forming the lower structure of the lower electrode into a cup structure. The second insulating layer 14b is a sacrificial oxide layer for forming the upper structure of the lower electrode into a cylinder structure and is removed in a subsequent etching process to form the upper structure of the lower electrode into a cylinder structure.

Generally, the height of the lower electrode of the capacitor is determined by the thickness of the second interlayer insulating film 14, and the width of the lower electrode of the capacitor is determined by the width to be etched. In addition, the region where the second interlayer insulating film 14 is etched to form the lower electrode is wider than the contact plug 13. An etch stop layer (not shown) is formed between the first interlayer insulating film 12 and the second interlayer insulating film 14, and in the process of etching a predetermined region of the second interlayer insulating film 14, The interlayer insulating film 12 is not etched by the etch stop layer.

1C, after forming a conductive material layer for the lower electrode on the entire upper surface including the contact plug 13, the conductive material layer for the lower electrode on the second insulating layer 14b is removed to form the second interlayer insulating film 14, And the lower electrodes 15 are formed in the etched regions. The conductive material layer for the lower electrode on the second insulating film 14b is removed by a planarization process such as chemical mechanical polishing.

At this time, the conductive material layer for the lower electrode is formed of polysilicon.

Referring to FIG. 1D, the second insulating layer 14b is removed through a predetermined etching process. At this time, the first insulating film 14a functions as the etching barrier layer due to the etching selectivity difference with respect to the second insulating film 14b, and thus remains as it is without being etched in the etching process of the second insulating film 14b.

As a result, the upper structure 15b of the lower electrode is exposed to have a cylindrical structure, and the lower structure of the lower electrode 15a becomes a cup structure by the remaining first insulating film 14a. The upper structure 15b of the lower electrode can be prevented from being collapsed because the second insulating film 14b is removed to form a cylinder structure but its height is not high.                     

In this case, the ratio of the cup structure occupying in the lower electrode 15 can be adjusted according to the thickness of the remaining first insulating layer 14a. Therefore, by adjusting the thickness of the first insulating layer 14a in FIG. 1A, the ratio of the cup structure occupying in the lower electrode 15 can be controlled. Since the first insulating layer 14a is not etched almost like the etching barrier layer due to the etching selectivity difference with respect to the second insulating layer 14b, the upper structure 15b of the lower electrode is uniformly exposed, Thereby making the capacitance uniform.

In addition, since the capacitance of the cylindrical structure is higher than that of the cup structure, the thickness of the first insulating layer 14a is adjusted by adjusting the ratio of the cup structure in the lower electrode 15, The stability of the structure and the electrostatic capacity can be secured at the same time.

Referring to FIG. 1E, Metastable Poly Silicon 16 is formed on the exposed surface of the lower electrode 15 to further increase the surface area of the lower electrode 15.

Referring to FIG. 1F, a dielectric film 17 and an upper electrode 18 are formed on the entire upper surface including the lower electrode 16. At this time, the dielectric film 17 is formed of an ONO film or Ta ₂ O ₅ and a high dielectric material.

As described above, according to the present invention, the upper structure of the lower electrode to be formed by the cylinder structure is uniformly exposed to uniform the capacitance of the entire capacitor, and the degree of exposure of the upper structure of the lower electrode is controlled to be the thickness of the first insulating film The reliability of the process and the electrical characteristics of the capacitor are improved.

Claims (12)

Sequentially forming a first insulating film and a second insulating film having different etching selection ratios on a semiconductor substrate on which a contact plug is formed in a contact hole of an interlayer insulating film; Sequentially exposing the contact plug by removing the second insulating film and the first insulating film in a region where the lower electrode is to be formed; Forming a lower electrode by forming a conductive material on the sidewalls of the second and first insulating films and the contact plug; Removing the second insulating film; and And sequentially forming a dielectric film and an upper electrode on the first insulating film including the lower electrode. ≪ RTI ID = 0.0 > 11. < / RTI > The method according to claim 1, Wherein the etch selectivity of the first and second insulating films is such that the first insulating film has a selectivity of 3 or more with respect to the second insulating film with respect to the etching solution. The method according to claim 1, The first insulating layer may be formed using an oxide film that is stable in terms of physical properties or may be formed using a material that is not easily removed by HF, BOE, or an oxide etching solution. The second insulating layer may be formed using an oxide film having properties opposite to the first insulating film Or an oxide film which is easily removed in an etching solution. The method according to claim 1, Wherein the first insulating film is formed of an undoped oxide film using TEOS or SiH ₄ gas, and the second insulating film is formed of a doped oxide film using TEOS or SiH ₄ gas. The method according to claim 1, Lt; RTI ID = 0.0 > 1, < / RTI > wherein the conductive material is polysilicon. The method according to claim 1, A lower portion of the lower electrode not exposed to the outer wall by the first insulating layer has a cup structure and an upper portion through which the outer wall is exposed has a cylindrical structure and the ratio of the cup structure in the lower electrode is proportional to the thickness of the first insulating film Wherein the first electrode and the second electrode are electrically connected to each other. The method according to claim 1, And forming metastable polysilicon on the surface of the lower electrode after removing the second insulating film. A method of manufacturing a capacitor of a semiconductor device, wherein the lower structure is a cup structure and the upper structure is a cylinder structure and forms a lower electrode of a semi-cylinder structure, Wherein the first sacrificial insulating film of the cup structure and the second sacrificial insulating film of the cylinder structure are formed of an insulating film having different etch selectivities so that the cup structure and the cylinder structure ratio of the entire capacitor lower electrode are uniform. A method of manufacturing a capacitor of a device. 9. The method of claim 8, Wherein the etch selectivity ratio of the first and second sacrificial insulating films is such that the first sacrificial insulating film has a selectivity of 3 or more with respect to the second sacrificial insulating film with respect to the etching solution. 9. The method of claim 8, The first sacrificial insulating layer may be formed using an oxide film that is stable in terms of physical properties or may be formed using a material that is not easily removed by HF, BOE, or an oxide etch solution. The second sacrificial insulating layer may have properties opposite to the first sacrificial insulating layer And an oxide film which is easily removed in the etching solution. 9. The method of claim 8, Wherein the first sacrificial insulating film is formed of an undoped oxide film using TEOS or SiH ₄ gas and the second sacrificial insulating film is formed of a doped oxide film using TEOS or SiH ₄ gas. 9. The method of claim 8, The lower portion of the lower electrode, which is not exposed to the outer wall by the first sacrificial insulating layer, has a cup structure and the upper portion where the outer wall is exposed has a cylindrical structure. The ratio of the cup structure in the lower electrode is, Wherein the second electrode is adjusted in proportion to the thickness of the first electrode.

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