JPH01283860A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01283860A JPH01283860A JP63112842A JP11284288A JPH01283860A JP H01283860 A JPH01283860 A JP H01283860A JP 63112842 A JP63112842 A JP 63112842A JP 11284288 A JP11284288 A JP 11284288A JP H01283860 A JPH01283860 A JP H01283860A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- silicon layer
- amorphous silicon
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Landscapes
- Weting (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置、特にキャパシタの大きな半導体
装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor device having a large capacitor.
第３図は従来のトレンチ構造のキャパシタの一例として
メモリの断面図を示す。FIG. 3 shows a cross-sectional view of a memory as an example of a conventional trench structure capacitor.
このものはシリコン基板（１）上にトレンチ（２）を形
成し、伝導性を良くするために不純物拡散を行なう。こ
の後、キャパシタ誘電体（絶縁膜）（４）及びフィール
ド酸化膜（６）を形成し、Ｐｏ１ｙ−シリコン電極（６
）を形成する。これでトレンチキャパシタは完成である
。次に絶縁膜（γ）を形成し、その上にゲート電極（８
）を形成後、電極を覆うように再び絶縁膜（７）を形成
し、コンタクト（９）を設けた後、Ｍ配線（至）をつけ
てメモリセルが完ａする。In this method, a trench (2) is formed on a silicon substrate (1), and impurities are diffused to improve conductivity. After this, a capacitor dielectric (insulating film) (4) and a field oxide film (6) are formed, and a Poly-silicon electrode (6) is formed.
) to form. The trench capacitor is now complete. Next, an insulating film (γ) is formed, and a gate electrode (8
), an insulating film (7) is formed again to cover the electrode, a contact (9) is provided, and an M wiring (to) is attached to complete the memory cell.
従来のトレンチ構造は以上のように構成されているので
、キャパシタ容量を増加させるにはトレンチの溝を深く
掘るしかなく、これは技術的にも構造的にも限界がある
という問題点があった。Since the conventional trench structure is configured as described above, the only way to increase the capacitance of the capacitor is to dig deeper into the trench, which has the problem of both technical and structural limitations. .
この発明は上記のような問題点を解消する丸めになされ
たもので、トレンチを深く掘らなくても容量の大きな半
導体装置を得ることを目的とする。The present invention has been developed to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device with a large capacity without digging a deep trench.
この発明に係る半導体装置の製造方法は、トレンチ底部
の中心をもシあげるように円錘状にアモルファス−シリ
コン層を形成し、その上に絶縁膜、電極を形成して、ト
レンチ内のキャパシタ電極面積を増大させることにより
、キャパシタの大きな半導体装置が得られる。In the method for manufacturing a semiconductor device according to the present invention, an amorphous silicon layer is formed in a conical shape so as to raise the center of the trench bottom, an insulating film and an electrode are formed on the amorphous silicon layer, and a capacitor electrode in the trench is formed. By increasing the area, a semiconductor device with a large capacitor can be obtained.
この発明における半導体装置の製造方法は、トレンチ底
部中央をもシ上げるようにアモルファス−シリコン層を
形成することにより、トレンチ内の電極面積を増大させ
、キャパシタの大きな半導体装置を得る。The method of manufacturing a semiconductor device according to the present invention increases the electrode area in the trench by forming an amorphous silicon layer so as to raise the center of the bottom of the trench, thereby obtaining a semiconductor device with a large capacitor.
以下、この発明の一実施例を図に従って説明する。第１
図は、この発明の一実施例による半導体装置の断面構造
を示し、第２図にその製造７０−に従った断面構造の変
化を示す。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows changes in the cross-sectional structure according to its manufacture 70-.
第２図（ａｔはシリコン基板（１）上にトレンチ（２）
を形成し、次にＥＯＲプラズマＯＶＤ法などの異方性デ
ポジション法によりアモルファス−シリコン層（８）を
形成した状態である。この後、（ＨＦ 、ＨＮＯ３）溶
液でエツチングすると、第２図ｆｂ）のように円錘状の
アモルファス−シリコン層が残る。これは異方性デポジ
ション法で形成された膜は膜の生成する面に対して垂直
方向は平行方向よりも付着力が弱いため、エツチングす
ると側壁部分がより速く除かれるためである。これによ
ってキャパシタの電極となる部分の面積が増大する。後
は従来の方法の同様の製造フローで、まず伝導性を良く
するために不純物拡散を行なう。Figure 2 (at is a trench (2) on a silicon substrate (1)
is formed, and then an amorphous silicon layer (8) is formed by an anisotropic deposition method such as EOR plasma OVD method. After this, etching with a (HF, HNO3) solution leaves a conical amorphous silicon layer as shown in FIG. 2fb). This is because a film formed by an anisotropic deposition method has weaker adhesion in a direction perpendicular to the surface on which the film is formed than in a direction parallel to it, so that sidewall portions are removed more quickly when etched. This increases the area of the portion that becomes the electrode of the capacitor. The rest of the manufacturing process is similar to that of conventional methods, and impurity diffusion is first performed to improve conductivity.
この後、キャパシタ誘電体（絶縁膜）（４）及びフィー
ルド酸化膜（６）を形成し、Ｐｏ１ｙ−シリコン電極（
６）を形成する。さらにこの上に絶縁膜（γ）を形成し
、その上にゲート電極（８）を形成後、電極を覆うよう
に再び絶縁膜（γ）を形成し、コンタクト（９）を設け
た後、Ｍ配線α＠を形成すると第１図に示した構造を得
ることができる。After this, a capacitor dielectric (insulating film) (4) and a field oxide film (6) are formed, and a Poly-silicon electrode (
6) Form. Further, an insulating film (γ) is formed on this, a gate electrode (8) is formed on it, an insulating film (γ) is formed again so as to cover the electrode, and a contact (9) is provided. By forming the wiring α@, the structure shown in FIG. 1 can be obtained.
なお上記実施例ではアモルファス−シリコン層（８）の
形成にＥＣＲプラグマを用いたが、アモルファス−シリ
コン層の形成には異方性デポジションのできるものであ
ればよい。In the above embodiment, an ECR pragma was used to form the amorphous silicon layer (8), but any material capable of anisotropic deposition may be used to form the amorphous silicon layer.
以上のように、この発明によればトレンチ底部の中心を
もり上げるように円錘状にアモルファス−シリコン層を
形成し、その上に絶縁膜、電極を形成して、トレンチ内
のキャパシタ電極面積を増大させたので、キャノ・°シ
タの大きな半導体装置が得られる効果がある。As described above, according to the present invention, an amorphous silicon layer is formed in a conical shape so as to raise the center of the bottom of the trench, and an insulating film and an electrode are formed on the amorphous silicon layer, thereby reducing the area of the capacitor electrode in the trench. Since the size of the capacitor is increased, it is possible to obtain a semiconductor device with a large capacitance and a large capacitance.
第１図はこの発明の一実施例による半導体装置の断面図
、第２図はその製造工程に従った断面図、第３図は従来
の半導体装置の断面図である。
（１）はシリコン基板、（２）はトレンチ部、（８）は
アモルファス−８ｉ層、（４）はキャパシタ誘電体、（
５）はフィールド酸化膜、（６）はＰｏ１ｙ−シリコン
電極、（γ）は絶縁膜、（８）はゲート電極、（９）は
コンタクト、（１＠はＭ配線である。
なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of the manufacturing process thereof, and FIG. 3 is a sectional view of a conventional semiconductor device. (1) is a silicon substrate, (2) is a trench part, (8) is an amorphous-8i layer, (4) is a capacitor dielectric, (
5) is a field oxide film, (6) is a Po1y-silicon electrode, (γ) is an insulating film, (8) is a gate electrode, (9) is a contact, and (1@ is an M wiring. The same reference numerals indicate the same or equivalent parts.
Claims (1)
ファス−シリコン層を形成し、これをエッチングするこ
とにより、トレンチ内部に円錘状のアモルファス−シリ
コン層を形成し、この上に誘電体として絶縁膜、さらに
電極を形成して、キャパシタの電極面積を増大させ、大
きな容量を得たことを特徴とする半導体装置の製造方法
。After forming the trench, an amorphous silicon layer is formed by an anisotropic deposition method, and this is etched to form a conical amorphous silicon layer inside the trench, and an insulating film is deposited on top of this as a dielectric. A method of manufacturing a semiconductor device, characterized in that an electrode is further formed to increase the electrode area of the capacitor, thereby obtaining a large capacitance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63112842A JPH0748549B2 (en) | 1988-05-10 | 1988-05-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63112842A JPH0748549B2 (en) | 1988-05-10 | 1988-05-10 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01283860A true JPH01283860A (en) | 1989-11-15 |
| JPH0748549B2 JPH0748549B2 (en) | 1995-05-24 |
Family
ID=14596896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63112842A Expired - Lifetime JPH0748549B2 (en) | 1988-05-10 | 1988-05-10 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0748549B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5245206A (en) * | 1992-05-12 | 1993-09-14 | International Business Machines Corporation | Capacitors with roughened single crystal plates |
| US7109545B2 (en) | 2001-04-19 | 2006-09-19 | Micron Technology, Inc. | Integrated circuit memory with offset capacitor |
| US7115970B2 (en) * | 2001-08-30 | 2006-10-03 | Micron Technology, Inc. | Capacitor for use in an integrated circuit |
-
1988
- 1988-05-10 JP JP63112842A patent/JPH0748549B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5245206A (en) * | 1992-05-12 | 1993-09-14 | International Business Machines Corporation | Capacitors with roughened single crystal plates |
| US5384152A (en) * | 1992-05-12 | 1995-01-24 | International Business Machines Corporation | Method for forming capacitors with roughened single crystal plates |
| US7109545B2 (en) | 2001-04-19 | 2006-09-19 | Micron Technology, Inc. | Integrated circuit memory with offset capacitor |
| US7642591B2 (en) | 2001-04-19 | 2010-01-05 | Micron Technology, Inc. | Multi-resistive integrated circuit memory |
| US8093643B2 (en) | 2001-04-19 | 2012-01-10 | Micron Technology, Inc. | Multi-resistive integrated circuit memory |
| US8878274B2 (en) | 2001-04-19 | 2014-11-04 | Micron Technology, Inc. | Multi-resistive integrated circuit memory |
| US7115970B2 (en) * | 2001-08-30 | 2006-10-03 | Micron Technology, Inc. | Capacitor for use in an integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0748549B2 (en) | 1995-05-24 |
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